CN106297634A - A kind of shift register, gate driver circuit and driving method - Google Patents

A kind of shift register, gate driver circuit and driving method Download PDF

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Publication number
CN106297634A
CN106297634A CN201610794582.4A CN201610794582A CN106297634A CN 106297634 A CN106297634 A CN 106297634A CN 201610794582 A CN201610794582 A CN 201610794582A CN 106297634 A CN106297634 A CN 106297634A
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China
Prior art keywords
film transistor
tft
thin film
signal input
pole
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CN201610794582.4A
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Chinese (zh)
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CN106297634B (en
Inventor
朱桂熠
许作远
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上海天马微电子有限公司
天马微电子股份有限公司
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Priority to CN201610794582.4A priority Critical patent/CN106297634B/en
Publication of CN106297634A publication Critical patent/CN106297634A/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using semiconductor elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit

Abstract

The present invention provides a kind of shift register, wherein: pull-up module electrical connection first input end, the second input and low level signal input, including the first film transistor, the second thin film transistor (TFT) and the 3rd thin film transistor (TFT);Drop-down module electrical connection second clock signal input part and low level signal input, including the 4th thin film transistor (TFT) and the second electric capacity;Output module electrically connects the first clock signal input terminal, second clock signal input part, the first outfan and low level signal input, including the first electric capacity, the 5th thin film transistor (TFT), the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT);Reseting module electrical connection reset signal input and low level signal input, including the 8th thin film transistor (TFT) and the 9th thin film transistor (TFT);Current potential keeps module electrical connection first input end, low level signal input and high level signal input, including the 3rd electric capacity, the tenth thin film transistor (TFT) and the 11st thin film transistor (TFT).

Description

A kind of shift register, gate driver circuit and driving method

Technical field

The present invention relates to Display Technique field, particularly relate to a kind of shift register, gate driver circuit and driving method.

Background technology

At present, each field, to display, includes but not limited to that the requirement of the mobile terminal such as mobile phone, flat board is more and more higher, with Time also improve the requirement to display floater.Display floater frivolous should resist various harsh environment again.

In technical field of display panel, display floater needs to experience long term high temperature work, but under long term high temperature work at present, Technical staff finds that the part of devices characteristic in the gate driver circuit of display floater is susceptible to skew, causes leaking electricity in circuit Flow through big.Gate driver circuit includes that the shift register of composition is the most sensitive, owing to the problem of leakage current is easily caused Interdependent node potential shift thus cause grid output abnormality.

Summary of the invention

For solving the problems referred to above, the present invention provides a kind of shift register, including pull-up module, drop-down module, output mould Block, reseting module, current potential keep module, primary nodal point, secondary nodal point and the 3rd node, wherein:

Described pull-up module electrical connection first input end, the second input and low level signal input are thin including first Film transistor, the second thin film transistor (TFT) and the 3rd thin film transistor (TFT);

Described drop-down module electrical connection second clock signal input part and low level signal input, brilliant including the 4th thin film Body pipe and the second electric capacity;

Described output module electrically connects the first clock signal input terminal, second clock signal input, the first output End and low level signal input, including the first electric capacity, the 5th thin film transistor (TFT), the 6th thin film transistor (TFT) and the 7th thin film Transistor;

Described reseting module electrical connection reset signal input and low level signal input, including the 8th film crystal Pipe and the 9th thin film transistor (TFT);

Described current potential keeps module electrical connection first input end, low level signal input and high level signal input End, including the 3rd electric capacity, the tenth thin film transistor (TFT) and the 11st thin film transistor (TFT).

A kind of gate driver circuit, including a kind of shift register that at least one-level is described above, wherein, described first defeated Entering the end described first outfan for upper level, described second input is described first outfan of next stage.

A kind of driving method, drives a kind of gate driver circuit described above, including the first stage, second stage, the Three stages and fourth stage, wherein,

In the described first stage, described reset signal input output reset signal, the most described first clock signal is defeated Enter to hold output low level signal, described second clock signal input part output high level;

In described second stage, described first input end input high level signal, the most described first clock signal input End input high level signal, described second clock signal input part input low level signal;

In the described phase III, described first input end stops input signal, described first clock signal input terminal output Low level signal, described second clock signal input part output high level signal, the most described first output signal output grid Signal;

At described fourth stage, described first clock signal input terminal output high level signal, described second clock signal Input output low level signal;Now, the high level signal of output signal described in described second input output next stage.

Compared with prior art, technical scheme has one of the following advantages: at 9T2C, i.e. nine film crystals Increase current potential on the basis of pipe and two electric capacity and keep module.Wherein, current potential keep module include two thin film transistor (TFT)s with And an electric capacity, and electrically connect first input end, low level signal input and high level signal input.By increasing electricity Position keeps module, it is ensured that the shift register in gate driver circuit keeps normal work under the long-time condition of high temperature, Wherein the film transistor device in shift register will not cause performance generation drift to cause leakage current because of high temperature.Have Current potential keeps the shift register of module to can ensure that associated film transistor is at or close to low level current potential, it is ensured that output The normal output of signal.

Gate driver circuit is made up of above-mentioned shift register, it is ensured that the normal output of signal;Additionally, also provide for A kind of driving method driving above-mentioned gate driver circuit, keeps coordinating of module and other modules by current potential, it is achieved high temperature Under duty, the normal output of signal.

Accompanying drawing explanation

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this Inventive embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to according to The accompanying drawing provided obtains other accompanying drawing.

The module diagram of a kind of shift register that Fig. 1 provides for the present invention;

The schematic diagram of the pull-up module of a kind of shift register that Fig. 2 provides for the present invention;

The schematic diagram of the drop-down module of a kind of shift register that Fig. 3 provides for the present invention;

The schematic diagram of the output module of a kind of shift register that Fig. 4 provides for the present invention;

The schematic diagram of the reseting module of a kind of shift register that Fig. 5 provides for the present invention;

The current potential of a kind of shift register that Fig. 6 provides for the present invention keeps the schematic diagram of module;

The connection diagram of a kind of shift register that Fig. 7 provides for the present invention;

A kind of driving method that Fig. 8 provides for the present invention.

Detailed description of the invention

Below in conjunction with schematic diagram, a kind of shift register, gate driver circuit and the driving method of the present invention are carried out more detailed Thin description, which show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can revise and be described herein The present invention, and still realize the advantageous effects of the present invention.Therefore, description below is appreciated that for people in the art Member's is widely known, and is not intended as limitation of the present invention.

In prior art, technical staff simulates the characteristic connecting the thin film transistor (TFT) triggering signal, it has been investigated that, this is thin Film transistor is under hot operation, and threshold voltage can occur the situation of left shift, and now leakage current dramatically increases.In order to solve This problem, the present invention provides a kind of shift register with current potential holding module, and this shift register can ensure that above-mentioned thin Film transistor keeps fixing current potential in special time.

As it is shown in figure 1, the module diagram of a kind of shift register that Fig. 1 provides for the present invention.Wherein, present invention displacement Depositor includes pulling up module 1, drop-down module 2, output module 3, reseting module 4, current potential holding module 5, primary nodal point (in figure Not shown), secondary nodal point (not shown) and the 3rd node (not shown).Wherein, primary nodal point, secondary nodal point with And the 3rd node illustrate that the connected mode of the present invention and the definition that carries out.

Pull-up module 1 electrically connects first input end IN, the second input Gn+1 and low level signal input L.Lower drawing-die Block 2 electrically connects second clock signal input part CKV2 and low level signal input L.Output module 3 electrically connects the first clock letter Number input CKV1, second clock signal input part CKV2, the first outfan Gn and low level signal input L.Reset mould Block 4 electrically connects reset signal input RESET and low level signal input L.Current potential keeps module 5 to electrically connect the first input End IN, low level signal input L and high level signal input H.

Connected mode and the effect of modules is illustrated in conjunction with shift register correlation function.As in figure 2 it is shown, figure The schematic diagram of the pull-up module of the 2 a kind of shift registers provided for the present invention.Pull-up module 1 includes the first film transistor M1, the second thin film transistor (TFT) M2 and the 3rd thin film transistor (TFT) M3.Grid electrical connection first input of the first film transistor M1 The second pole electrical connection the of first pole electrical connection the 3rd node K, the first film transistor M1 of end IN, the first film transistor M1 One node PU.The grid of the second thin film transistor (TFT) M2 electrically connects the second input Gn+1, first pole of the second thin film transistor (TFT) M2 The second pole electrical connection low level signal input L of electrical connection primary nodal point PU, the second thin film transistor (TFT) M2, receives low level letter Number.The first pole electrical connection first of grid electrical connection the secondary nodal point PD, the 3rd thin film transistor (TFT) M3 of the 3rd thin film transistor (TFT) M3 The second pole electrical connection low level signal input L of node PU, the 3rd thin film transistor (TFT) M3.

The schematic diagram of the drop-down module of a kind of shift register that Fig. 3 provides for the present invention.Drop-down module 2 includes that the 4th is thin Film transistor M4 and the second electric capacity C2.Wherein, the grid electrical connection primary nodal point PU of the 4th thin film transistor (TFT) M4, the 4th thin film The second pole electrical connection low level signal input of the first pole electrical connection secondary nodal point PD, the 4th thin film transistor (TFT) M4 of transistor L.The second pole electrical connection second of first pole electrical connection the second clock signal input part CKV2, the second electric capacity C2 of the second electric capacity C2 Node PD.

The schematic diagram of the output module of a kind of shift register that Fig. 4 provides for the present invention.Output module 3 includes that the 5th is thin Film transistor M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7 and the first electric capacity C1.Wherein, the first electric capacity C1 Second pole of second pole electrical connection the 5th thin film transistor (TFT) M5 of the first pole electrical connection primary nodal point PU, the first electric capacity C1.5th The first pole electrical connection second clock signal of grid electrical connection the primary nodal point PU, the 5th thin film transistor (TFT) M5 of thin film transistor (TFT) M5 Input CKV2, second pole of the 5th thin film transistor (TFT) M5 electrically connects the first outfan Gn.The grid of the 6th thin film transistor (TFT) M6 Electrical connection secondary nodal point PD, first pole of the 6th thin film transistor (TFT) M6 electrically connects second pole of the first electric capacity C1, and the 6th thin film is brilliant The second pole electrical connection low level signal input L of body pipe M6.7th thin film transistor (TFT) M7 grid electrically connects the first clock signal Input CKV1, first pole of the 7th thin film transistor (TFT) M7 electrically connects second pole of the first electric capacity C1, the 7th thin film transistor (TFT) M7 Second pole electrical connection low level signal input L.

The schematic diagram of the reseting module of a kind of shift register that Fig. 5 provides for the present invention.Reseting module 4 includes that the 8th is thin Film transistor M8 and the 9th thin film transistor (TFT) M9.Wherein, the grid electrical connection reset signal input of the 8th thin film transistor (TFT) M8 End RESET, first pole of the 8th thin film transistor (TFT) M8 electrically connects the first outfan Gn, and the second of the 8th thin film transistor (TFT) M8 is the most electric Connect low level signal input L.The grid electrical connection reset signal input RESET of the 9th thin film transistor (TFT) M9, the 9th is thin The second pole electrical connection low level signal of first pole electrical connection the primary nodal point PU, the 9th thin film transistor (TFT) M9 of film transistor M9 is defeated Enter to hold L.

The current potential of a kind of shift register that Fig. 6 provides for the present invention keeps the schematic diagram of module.Current potential keeps module 5 to wrap Include the tenth thin film transistor (TFT) M10, the 11st thin film transistor (TFT) M11 and the 3rd electric capacity C3.Wherein, first pole of the 3rd electric capacity C3 Second pole electrical connection the 3rd node K of electrical connection first input end IN, the 3rd electric capacity C3.The grid of the tenth thin film transistor (TFT) M10 The first pole electrical connection high level signal input H of electrical connection first input end IN, the tenth thin film transistor (TFT) M10, the tenth thin film Second pole electrical connection the 3rd node K of transistor M10.The grid electrical connection secondary nodal point PD of the 11st thin film transistor (TFT) M11, the The second pole electrical connection of first pole electrical connection the 3rd node K, the 11st thin film transistor (TFT) M11 of 11 thin film transistor (TFT) M11 is low Level signal input L.

Above-mentioned Fig. 2 to Fig. 6 respectively describes pull-up module, drop-down module, output module, reseting module and current potential and keeps The concrete attachment structure of module.Wherein, above-mentioned primary nodal point PU, secondary nodal point PD and the 3rd node K of having elaborated, specifically , primary nodal point PU is second pole of the first film crystal M1, first pole of the second thin film transistor (TFT) M2, the 3rd thin film transistor (TFT) First pole of M3, first pole of the 9th thin film transistor (TFT) M9, the grid of the 4th thin film transistor (TFT) M4, first pole of the first electric capacity C1 And the 5th junction point of grid of thin film transistor (TFT) M5;Secondary nodal point PD is the grid of the 3rd thin film transistor (TFT) M3, the 6th thin The junction point of second pole of the grid of film transistor M6, first pole of the 4th thin film transistor (TFT) M4 and the second electric capacity C2;3rd Node K is first pole of the first film transistor M1, first pole of the 11st thin film transistor (TFT) M11 and the tenth thin film transistor (TFT) The junction point of second pole of M10.

The connection diagram of a kind of shift register that Fig. 7 provides for the present invention, concrete, the first film transistor M1 is extremely 11st thin film transistor (TFT) M11 can be P-type TFT, i.e. when the grid of thin film transistor (TFT) receives low level signal, Thin film transistor (TFT) turns on, and the first signal extremely gone up can be conducted to the second pole;The first film transistor M1 to the 11st thin film is brilliant Body pipe M11 can also be N-type TFT, i.e. when the grid of thin film transistor (TFT) receives high level signal, and thin film transistor (TFT) Conducting, the first signal extremely gone up can be conducted to the second pole.

Concrete, above-mentioned shift register concatenation connects into gate driver circuit, and gate driver circuit is normally at display The non-display area of panel.Wherein, in addition to first order shift register, the first input end IN of other all shift registers is First outfan Gn of upper level shift register, the first input end of the shift register of the first order accesses and triggers signal, should Signal is provided by the integrated drive chips on panel;In addition to the shift register of afterbody, other all shift registers The first outfan Gn that the second input Gn+1 is next stage shift register.

In above-described embodiment, the low level signal input of all thin film transistor (TFT)s electrical connection can be same input, Can also be different inputs, be provided which low level signal.Additionally, above-mentioned first input end, low level signal input, first Clock signal input terminal, second clock signal input part, high level signal input etc. all can be integrated in integrated drive chips Inside, is not described in detail at this, and integrated or external form is included within the scope of the present invention, and the present invention does not do concrete limit System.

In order to better illustrate the operation principle of shift register of the present invention and gate driver circuit, in conjunction with Fig. 7 with And Fig. 8 describes in detail.Wherein, a kind of driving method that Fig. 8 provides for the present invention.Driving method of the present invention is used for driving above-mentioned Gate driver circuit, above-mentioned gate driver circuit is made up of previously described shift register concatenation, and all thin film transistor (TFT)s are equal For N-type TFT, concrete attachment structure repeats no more.This driving method mainly includes four-stage, the specially first rank Section T1, second stage T2, phase III T3 and fourth stage T4.

During first stage T1, first input end IN not yet output signal, the first clock signal input terminal CKV1 is defeated Going out low level signal, second clock signal input part CKV2 exports high level signal, and reset signal input RESET exports reset Signal.Now the input of transistor seconds M2 grid no signal, is off;The first film transistor M1 and the tenth thin film The grid of transistor M10 receives the low level signal of first input end IN and is off;Because second clock signal inputs End CKV2 input high level signal, now the second electric capacity C2 is charged, secondary nodal point PD keep high level signal thus the tenth One thin film transistor (TFT) M11, the 3rd thin film transistor (TFT) M3 and the 6th thin film transistor (TFT) M6 conducting, the 11st thin film transistor (TFT) M11 The second pole, second pole of the second pole and the 6th thin film transistor (TFT) M6 of the 3rd thin film transistor (TFT) M3 receive low level signal input The low level signal of end L output;Because of the 3rd thin film transistor (TFT) M3 conducting, low level signal is caused to transmit to primary nodal point PU, this Time the 4th thin film transistor (TFT) M4 disconnect;During first stage T1, reset signal input RESET exports reset signal, this Time the 8th thin film transistor (TFT) M8 and the 9th thin film transistor (TFT) M9 conducting, low level signal input L output low level signal Enter shift register, carry out reset initialization, the most now the first outfan Gn output low level signal.

During second stage T2, first input end IN output pulse signal, i.e. high level signal, the first clock signal is defeated Entering to hold CKV1 to export high level signal, second clock signal input part CKV2 becomes low level signal.Now, because of first input end IN exports high level signal, and the first film transistor M1 and the tenth thin film transistor (TFT) M10 conducting, the 3rd electric capacity C3 fills Electricity, the 3rd node K is high level, and primary nodal point PU becomes high level;Because the first clock signal input terminal CKV1 exports high level Signal, now the 7th thin film transistor (TFT) M7 conducting, second pole of the 7th thin film transistor (TFT) M7 receives low level signal input L's Low level signal, and the second pole transmitted to the first electric capacity C1;Because of second clock signal input part CKV2 output low level signal, Now the 5th thin film transistor (TFT) is in the on-state by the second pole of low level signal transmission to the 5th thin film transistor (TFT) M5, now First outfan Gn remains unchanged output low level signal;Secondary nodal point PD becomes low level under the effect of the second electric capacity C2.

During phase III, now first input end IN maintains low level signal, the first clock signal input terminal CKV1 Output low level signal, second clock signal input part CKV2 exports high level signal.Because first input end IN maintains low level Signal, now the first film transistor M1 and the tenth thin film transistor (TFT) M10 is off, and now the 3rd node K is Low level state is maintained under the effect of three electric capacity C3;And primary nodal point PU is in high level state on last stage, therefore the 5th Thin film transistor (TFT) M5 turns on, the high level signal transmission of second clock signal input part CKV2 output to the 5th thin film transistor (TFT) M5 The second pole, now because the coupling of the first electric capacity C1 causes primary nodal point PU to be elevated;4th thin film transistor (TFT) M4 because of The high level state of primary nodal point PU and turn on, the second pole receives low level signal and also transmits to secondary nodal point PD, therefore second Node PD maintains low level;Now the first outfan Gn output pulse signal, the transmission of this signal is used for opening and picture to gate line The thin film transistor (TFT) that element electrode connects.

During fourth stage, first input end IN maintains low level signal, the first clock signal input terminal CKV1 output High level signal, second clock signal input part CKV2 output low level signal.Now, because of the effect of the second electric capacity C2, second Node PD becomes low level;The grid of the 7th thin film transistor (TFT) M7 makes the 7th thin film transistor (TFT) M7 lead because receiving high level signal Logical, now low level signal is from the second pole of the second pole transmission to the first electric capacity C1 of the 7th thin film transistor (TFT) M7;Primary nodal point PU turns on input low level signal because of the continuous discharge of the first electric capacity C1 and the 3rd thin film transistor (TFT) M3 and becomes low level;This Time, the tenth thin film transistor (TFT) M10 and the first film transistor M1 is still off, and the 3rd node K becomes because of no signal Change and maintain low level.

In above process, when primary nodal point PU is in low level state, the 3rd node K can maintain low level in the moment State, therefore the difference between the first pole and second pole of the first transistor M1 is able to maintain that in relatively low scope.It is to say, In first input end IN output pulse signal phase process, the 3rd node K becomes high level, and other stages the 3rd node K is all the time Maintain low level state, particularly when the first outfan Gn output low level signal, because of the of the first film transistor M1 One pole electrical connection the 3rd node K, it is possible to maintain low level state all the time, reduce the risk of leakage current, prevent the first film Transistor M1 generating device characteristic deviation and affect the first signal output part Gn signal output.

Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious change, Readjust and substitute without departing from protection scope of the present invention.Therefore, although by above example, the present invention is carried out It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also Other Equivalent embodiments more can be included, and the scope of the present invention is determined by scope of the appended claims.

Claims (11)

1. a shift register, including pull-up module, drop-down module, output module, reseting module, current potential keep module, the One node, secondary nodal point and the 3rd node, wherein:
Described pull-up module electrical connection first input end, the second input and low level signal input, brilliant including the first film Body pipe, the second thin film transistor (TFT) and the 3rd thin film transistor (TFT);
Described drop-down module electrical connection second clock signal input part and low level signal input, including the 4th thin film transistor (TFT) And second electric capacity;
Described output module electrically connects the first clock signal input terminal, second clock signal input part, the first outfan and low Level signal input, including the first electric capacity, the 5th thin film transistor (TFT), the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT);
Described reseting module electrical connection reset signal input and low level signal input, including the 8th thin film transistor (TFT) with And the 9th thin film transistor (TFT);
Described current potential keeps module electrical connection first input end, low level signal input and high level signal input, bag Include the 3rd electric capacity, the tenth thin film transistor (TFT) and the 11st thin film transistor (TFT).
A kind of shift register the most according to claim 1, in described pull-up module,
The grid of described the first film transistor electrically connects described first input end, and the first of described the first film transistor is the most electric Connect described 3rd node, primary nodal point described in the second pole electrical connection the of described the first film transistor;
The grid of described second thin film transistor (TFT) electrically connects described second input, and the first of described second thin film transistor (TFT) is the most electric Connecting described primary nodal point, the second pole of described second thin film transistor (TFT) electrically connects described low level signal input;
The grid of described 3rd thin film transistor (TFT) electrically connects described secondary nodal point, and the first pole of described 3rd thin film transistor (TFT) is electrically connected Connect described primary nodal point, the second pole electrical connection low level signal input of described 3rd thin film transistor (TFT).
3. a kind of shift register as claimed in claim 1, in described drop-down module,
The grid of described 4th thin film transistor (TFT) electrically connects described primary nodal point, and the first pole of described 4th thin film transistor (TFT) is electrically connected Connecing described secondary nodal point, the second pole of described 4th thin film transistor (TFT) electrically connects described low level signal input;
First pole of described second electric capacity electrically connects described second clock signal input part, and the second pole of described second electric capacity is electrically connected Connect described secondary nodal point.
4. a kind of shift register as claimed in claim 1, in described output module,
First pole of described first electric capacity electrically connects described primary nodal point, the second pole electrical connection the described 5th of described first electric capacity Second pole of thin film transistor (TFT);
The grid of described 5th thin film transistor (TFT) electrically connects described primary nodal point, and the first pole of described 5th thin film transistor (TFT) is electrically connected Connecing described second clock signal input part, the second pole of described 5th thin film transistor (TFT) electrically connects described first outfan;
The grid of described 6th thin film transistor (TFT) electrically connects described secondary nodal point, and the first pole of described 6th thin film transistor (TFT) is electrically connected Connecing the second pole of described first electric capacity, the second pole of described 6th thin film transistor (TFT) electrically connects described low level signal input;
The grid of described 7th thin film transistor (TFT) electrically connects described first clock signal input terminal, described 7th thin film transistor (TFT) First pole electrically connects the second pole of described first electric capacity, and the second pole of described 7th thin film transistor (TFT) electrically connects described low level letter Number input.
5. a kind of shift register as claimed in claim 1, in described reseting module,
The grid of described 8th thin film transistor (TFT) electrically connects described reset signal input, the first of described 8th thin film transistor (TFT) Pole electrically connects described first outfan, and the second pole of described 8th thin film transistor (TFT) electrically connects described low level signal input;
The grid of described 9th thin film transistor (TFT) electrically connects described reset signal input, the first of described 9th thin film transistor (TFT) Pole electrically connects described primary nodal point, and the second pole of described 9th thin film transistor (TFT) electrically connects described low level signal input.
6. a kind of shift register as claimed in claim 1, described current potential keeps in module,
First pole of described 3rd electric capacity electrically connects described first input end, and described second pole electrically connects described 3rd node;
The grid of described tenth thin film transistor (TFT) electrically connects described first input end, and the first of described tenth thin film transistor (TFT) is the most electric Connecting described high level signal input, the second pole of described tenth thin film transistor (TFT) electrically connects described 3rd node;
The grid of described 11st thin film transistor (TFT) electrically connects described secondary nodal point, the first pole of described 11st thin film transistor (TFT) Electrically connecting described 3rd node, the second pole of described 11st thin film transistor (TFT) electrically connects described low level signal input.
7. a kind of shift register as claimed in claim 1, wherein, described the first film transistor to described 11st thin film Transistor can be prepared from by any one of non-crystalline silicon, low temperature polycrystalline silicon or oxide semiconductor.
8. a kind of shift register as claimed in claim 1, wherein, described the first film transistor to described 11st thin film Transistor is P-type TFT or N-type TFT.
9. a gate driver circuit, including a kind of shift register described at least one-level claim 1, wherein, described One input is described first outfan of upper level, and described second input is described first outfan of next stage.
10. a driving method, drives a kind of gate driver circuit described in claim 9, including first stage, second-order Section, phase III and fourth stage, wherein,
In the described first stage, described reset signal input output reset signal, the most described first clock signal input terminal Output low level signal, described second clock signal input part output high level;
In described second stage, described first input end input high level signal, the most described first clock signal input terminal is defeated Enter high level signal, described second clock signal input part input low level signal;
In the described phase III, described first input end stops input signal, and described first clock signal input terminal exports low electricity Ordinary mail number, described second clock signal input part output high level signal, the most described first output signal output signal;
In described fourth stage, described first clock signal input terminal output high level signal, described second clock signal inputs End output low level signal;Now, the high level signal of output signal described in described second input output next stage.
11. a kind of driving methods as claimed in claim 10, wherein,
In the described first stage, described primary nodal point keeps electronegative potential with described 3rd node, and described secondary nodal point keeps high electricity Position;
In described second stage, described primary nodal point and described 3rd node become high potential, and described secondary nodal point becomes low electricity Position;
In the described phase III, described primary nodal point current potential is elevated, and described secondary nodal point and described 3rd node become low electricity Position;
In described fourth stage, described primary nodal point, described secondary nodal point and described 3rd node all become electronegative potential.
CN201610794582.4A 2016-08-31 2016-08-31 A kind of shift register, gate driving circuit and driving method CN106297634B (en)

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CN109935188A (en) * 2019-03-08 2019-06-25 合肥京东方卓印科技有限公司 Drive element of the grid, method, gate driving mould group, circuit and display device
CN110148383A (en) * 2019-06-19 2019-08-20 京东方科技集团股份有限公司 Shift register cell and its driving method and gate driving circuit

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CN109935188A (en) * 2019-03-08 2019-06-25 合肥京东方卓印科技有限公司 Drive element of the grid, method, gate driving mould group, circuit and display device
CN110148383A (en) * 2019-06-19 2019-08-20 京东方科技集团股份有限公司 Shift register cell and its driving method and gate driving circuit

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