CN109859701B - Shift register and gate drive circuit - Google Patents
Shift register and gate drive circuit Download PDFInfo
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- CN109859701B CN109859701B CN201811600809.2A CN201811600809A CN109859701B CN 109859701 B CN109859701 B CN 109859701B CN 201811600809 A CN201811600809 A CN 201811600809A CN 109859701 B CN109859701 B CN 109859701B
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Abstract
The present application relates to a shift register and a gate driving circuit. The shift register comprises a pull-up circuit, an output circuit, a pull-down circuit, a first pull-down control circuit and a second pull-down control circuit. The first pull-down control circuit provides a high level signal to the pull-down control node in response to a high level signal, provides a high level signal to the pull-down node in response to a voltage signal of the pull-down control node, and provides low level signals to the pull-down node and the pull-down control node in response to the first switching signal, the second switching signal, and the voltage signal of the pull-up node, respectively. The second pull-down control circuit responds to the first pull-down control signal and the second pull-down control signal, and provides the low level signal for the high level signal input end so as to reduce the time that the high level signal input end is in the direct current high level, thereby reducing the time that the pull-down node is in the direct current high level working state, further reducing the possibility that the threshold voltage of the related thin film transistor drifts, and improving the noise reduction effect.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to a shift register and a gate driving circuit.
Background
The Thin Film Transistor Liquid Crystal Display (TFT-LCD) driver mainly includes a gate driving circuit and a data driving circuit, wherein the gate driving circuit converts an input clock signal through a shift register and then applies the converted clock signal to a gate line of the Liquid Crystal Display panel, and the gate driving circuit and the TFT may be formed in the same process and simultaneously formed on the LCD panel together. The gate driving circuit includes a shift register having a plurality of stages, each of which is connected to a corresponding gate line to output a gate driving signal. Each stage of the gate driving circuit is connected to each other, a start signal is input to a first stage of the stages and sequentially outputs a gate driving signal to the gate line, wherein an input terminal of a current nth stage is connected to an output terminal of an n-2 th stage, a first pull-down signal input terminal is connected to an output terminal of an n +4 th stage, a second pull-down signal input terminal is connected to a pull-down node of an n-1 th stage, a first switching signal input terminal is connected to a pull-up node of the n-1 th stage, and a second switching signal input terminal is connected to a pull-up node of the n +1 th stage.
In the conventional gate driving circuit design, a pull-down node is generally arranged to pull down the potential of an output terminal of a non-output row, but if the pull-down node is in a dc high-level operating state for a long time, the threshold voltage of the related thin film transistor may drift, which affects the noise reduction effect.
Disclosure of Invention
Based on this, the application provides a shift register and a gate driving circuit to improve the condition that the pull-down node is in a dc high level working state for a long time.
An embodiment of the present application provides a shift register, including:
the pull-up circuit is connected with the input signal end of the shift register, is used for responding to an input signal and provides the input signal to a pull-up node;
the output circuit is connected with the pull-up node and the clock signal input end, is used for responding to the voltage signal of the pull-up node and provides a clock signal to the first output end and the second output end of the shift register;
a pull-down circuit connected to the first pull-down signal input terminal, the second pull-down signal input terminal and the pull-down node, for responding to the first pull-down signal, the second pull-down signal and the voltage signal of the pull-down node, and providing a low level signal to the pull-up node of the shift register and the first output terminal of the shift register, respectively;
the first pull-down control circuit is connected with a high level signal input end, a first switch signal input end, a second switch signal input end, a pull-down control node, the pull-down node and the pull-up node, and is used for responding to the high level signal, providing the high level signal to the pull-down control node, responding to a voltage signal of the pull-down control node, providing the high level signal to the pull-down node, responding to the first switch signal, the second switch signal and the voltage signal of the pull-up node, and providing the low level signal to the pull-down node and the pull-down control node respectively; and
and the second pull-down control circuit is connected with the first pull-down control signal input end, the second pull-down control signal input end and the high level signal input end, is used for responding to the first pull-down control signal and the second pull-down control signal, and provides the low level signal for the high level signal input end.
In one embodiment, the first pull-down control circuit comprises:
a first switching branch, connected to a first switching signal input terminal, the pull-down control node and the pull-down node, for responding to the first switching signal and providing the low level signal to the pull-down node and the pull-down control node, respectively;
the second switch branch circuit is connected with the pull-up node, the pull-down control node and the pull-down node, is used for responding to a voltage signal of the pull-up node, and provides the low-level signal to the pull-down node and the pull-down control node respectively;
a third switching branch, connected to the second switching signal input terminal, the pull-down control node and the pull-down node, for responding to the second switching signal and providing the low level signal to the pull-down node and the pull-down control node, respectively; and
and the pull-down input branch is connected with the high-level signal input end, the pull-down control node and the pull-down node, and is used for responding to the high-level signal and providing the high-level signal for the pull-down control node, and responding to a voltage signal of the pull-down control node and providing the high-level signal for the pull-down node.
In one embodiment, the second pull-down control circuit comprises:
a first pull-down control branch, connected to the first pull-down control signal input terminal and the high level signal input terminal, for responding to the first pull-down control signal and providing the low level signal to the high level signal input terminal; and
and the second pull-down control branch is connected with the second pull-down control signal input end and the high level signal input end, is used for responding to the second pull-down control signal and provides the low level signal for the high level signal input end.
In one embodiment, the pull-down circuit comprises:
a first pull-down branch, connected to the first pull-down signal input terminal, for responding to the first pull-down signal and providing a low level signal to a pull-up node of the shift register and a first output terminal of the shift register, respectively;
a second pull-down branch, connected to the second pull-down signal input terminal, for responding to the second pull-down signal and providing a low level signal to the pull-up node of the shift register and the first output terminal of the shift register, respectively; and
and the third pull-down branch is connected with the pull-down node and used for responding to the voltage signal of the pull-down node and respectively providing a low level signal to the pull-up node of the shift register and the first output end of the shift register.
In one embodiment, the pull-up circuit includes:
and the grid electrode and the drain electrode of the first switch tube are connected with the input signal end, and the source electrode of the first switch tube is connected with the pull-up node.
In one embodiment, the output circuit includes:
a grid electrode of the second switch tube is connected with the pull-up node, a drain electrode of the second switch tube is connected with the clock signal input end, and a source electrode of the second switch tube is connected with the first output end of the shift register;
a grid electrode of the third switching tube is connected with the pull-up node, a drain electrode of the third switching tube is connected with the clock signal input end, and a source electrode of the third switching tube is connected with the second output end of the shift register; and
and one end of the capacitor is connected with the pull-up node, and the other end of the capacitor is connected with the first output end of the shift register.
In one embodiment, the first pull-down leg comprises:
a grid electrode of the fourth switching tube is connected with the first pull-down signal input end, a drain electrode of the fourth switching tube is connected with the first output end of the shift register and the capacitor, and a source electrode of the fourth switching tube is connected with the low level voltage signal input end; and
a grid electrode of the fifth switching tube is connected with the first pull-down signal input end, a drain electrode of the fifth switching tube is connected with the pull-up node, and a source electrode of the fifth switching tube is connected with the low-level voltage signal input end;
the second pull-down leg comprises:
a sixth switching tube, a gate of which is connected to the second pull-down signal input terminal, a drain of which is connected to the first output terminal of the shift register and the capacitor, and a source of which is connected to the low level voltage signal input terminal; and
a grid electrode of the seventh switching tube is connected with the second pull-down signal input end, a drain electrode of the seventh switching tube is connected with the pull-up node, and a source electrode of the seventh switching tube is connected with the low-level voltage signal input end;
the third pull-down leg comprises:
a gate of the eighth switching tube is connected with the pull-down node, a drain of the eighth switching tube is connected with the first output end of the shift register and the capacitor, and a source of the eighth switching tube is connected with the low level voltage signal input end; and
and the grid electrode of the ninth switching tube is connected with the pull-down node, the drain electrode of the ninth switching tube is connected with the pull-up node, and the source electrode of the ninth switching tube is connected with the low-level voltage signal input end.
In one embodiment, the pull-down input branch comprises:
a grid electrode and a drain electrode of the tenth switching tube are both connected with the high-level signal input end, and a source electrode of the tenth switching tube is connected with the pull-down control node; and
a grid electrode of the eleventh switch tube is connected with the pull-down control node, a drain electrode of the eleventh switch tube is connected with the high-level signal input end, and a source electrode of the eleventh switch tube is connected with the pull-down node;
the first switching leg includes:
a twelfth switching tube, a gate of which is connected to the first switching signal input terminal, a drain of which is connected to the pull-down control node, and a source of which is connected to the low level signal input terminal; and
a gate of the thirteenth switching tube is connected with the first switching signal input end, a drain of the thirteenth switching tube is connected with the pull-down node, and a source of the thirteenth switching tube is connected with the low level signal input end;
the second switching leg comprises:
a fourteenth switching tube, a gate of which is connected to the pull-up node, a drain of which is connected to the pull-down control node, and a source of which is connected to the low level signal input terminal; and
a fifteenth switching tube, wherein a grid electrode is connected with the pull-up node, a drain electrode is connected with the pull-down node, and a source electrode is connected with the low-level signal input end;
the third switching branch includes:
a sixteenth switching tube, a gate of which is connected to the second switching signal input terminal, a drain of which is connected to the pull-down control node, and a source of which is connected to the low level signal input terminal; and
and the grid electrode of the seventeenth switching tube is connected with the second switching signal input end, the drain electrode of the seventeenth switching tube is connected with the pull-down node, and the source electrode of the seventeenth switching tube is connected with the low level signal input end.
In one embodiment, the first pull-down control branch comprises an eighteenth switching tube, a gate of the eighteenth switching tube is connected with a first pull-down control signal input end, a drain of the eighteenth switching tube is connected with the high-level signal input end, and a source of the eighteenth switching tube is connected with the low-level signal input end; and
the second pull-down control branch comprises a nineteenth switching tube, the grid electrode of the nineteenth switching tube is connected with the second pull-down control signal input end, the drain electrode of the nineteenth switching tube is connected with the high level signal input end, and the source electrode of the nineteenth switching tube is connected with the low level signal input end.
Based on the same inventive concept, the present application further provides a gate driving circuit, including cascaded shift registers of different levels, the shift register including:
the pull-up circuit is connected with the second output end of the (n-2) th-stage shift register, is used for responding to the output signal of the (n-2) th-stage shift register and provides the output signal of the (n-2) th-stage shift register to a pull-up node;
the output circuit is connected with the pull-up node and the clock signal input end, is used for responding to the voltage signal of the pull-up node and provides a clock signal to the first output end and the second output end of the shift register;
the pull-down circuit is connected with the pull-down node of the (n-1) th-stage shift register, the pull-down node of the shift register and the first output end of the (n +4) th-stage shift register, is used for responding to the voltage signal output by the first output end of the (n +4) th-stage shift register and respectively provides a low level signal to the pull-up node of the shift register and the first output end of the shift register;
a first pull-down control circuit, connected to a high level signal input terminal, a pull-up node of the (n +1) th stage register, a pull-up node of the (n-1) th stage shift register, a pull-up node of the shift register, a pull-down control node, and the pull-down node, for providing the high level signal to the pull-down control node in response to the high level signal, providing the high level signal to the pull-down node in response to a voltage signal of the pull-down control node, and providing the low level signal to the pull-down node and the pull-down control node in response to a voltage signal of the pull-up node of the (n +1) th stage register, a voltage signal of the pull-up node of the (n-1) th stage shift register, and a voltage signal of the pull-up node of the shift register, respectively; and
a second pull-down control circuit, connected to the clock signal input terminals of the (n +5) th and (n +6) th stage shift registers, for responding to the clock signals of the (n +5) th and (n +6) th stage shift registers and providing the low level signal to the high level signal input terminal;
wherein N is more than 2 and less than N-6, N is the number of grid lines, and N and N are positive integers.
In summary, the present application provides a shift register and a gate driving circuit. The shift register comprises a pull-up circuit, an output circuit, a pull-down circuit, a first pull-down control circuit and a second pull-down control circuit. The pull-up circuit is connected with the input signal end of the shift register, is used for responding to an input signal and provides the input signal for a pull-up node. The output circuit is connected with the pull-up node and the clock signal input end, is used for responding to the voltage signal of the pull-up node and provides a clock signal to the first output end and the second output end of the shift register. The pull-down circuit is connected with the first pull-down signal input end, the second pull-down signal input end and the pull-down node, is used for responding to the first pull-down signal, the second pull-down signal and the voltage signal of the pull-down node, and provides a low level signal to the pull-up node of the shift register and the first output end of the shift register respectively. The first pull-down control circuit is connected with a high level signal input end, a first switch signal input end, a second switch signal input end, a pull-down control node, a pull-down node and the pull-up node, is used for responding to the high level signal, providing the high level signal for the pull-down control node, responding to a voltage signal of the pull-down control node, providing the high level signal for the pull-down node, responding to the first switch signal, the second switch signal and the voltage signal of the pull-up node, and providing the low level signal for the pull-down node and the pull-down control node respectively. The second pull-down control circuit is connected to the first pull-down control signal input end, the second pull-down control signal input end and the high level signal input end, and is used for responding to the first pull-down control signal and the second pull-down control signal and providing the low level signal for the high level signal input end. In this application, in the non-output stage, the shift register responds to first drop-down control signal and second drop-down control signal, and will low level signal provides high level signal input part, in order to reduce high level signal input part is in the time of direct current high level operating condition, thereby reduces the time that the drop-down node is in direct current high level operating condition, and then reduces the possibility that relevant thin film transistor's threshold voltage takes place to drift, improves the noise reduction effect.
Drawings
FIG. 1 is an electrical schematic diagram of an exemplary display panel;
FIG. 2 is a schematic diagram of a Topson circuit configuration;
FIG. 3 is a schematic diagram of a charging process of a pull-up node in a Tompson circuit;
FIG. 4 is a schematic diagram of an exemplary shift register circuit;
FIG. 5 is a schematic diagram of another exemplary shift register circuit structure;
FIG. 6 is a timing diagram of the signal terminals of the shift register of FIG. 5;
fig. 7 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of a cascade structure of a gate driving circuit provided in the present application;
fig. 9 is a timing diagram of each signal terminal of the shift register of fig. 7.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the embodiments disclosed below.
Referring to fig. 1, the shift register is an important technology in panel design, and has the main advantage of replacing a Gate driver IC (Gate driver IC) to reduce the production cost, which mainly uses an exposure and development technology to generate a logic circuit to drive a Gate signal.
Referring to fig. 2 and fig. 3, the gate driving circuit is developed on the basis of the thompson circuit, and during the scanning process, a precharge signal is provided at the pull-up node q (boost point) to precharge the point, so that the voltage signal at the point is raised to a high potential, and the corresponding switch tube is turned on to output the clock signal.
Referring to fig. 4 and 5, a general shift register includes a main circuit, a secondary pull-down circuit and a secondary pull-down control circuit. Taking the fourth stage shift register in the gate driving circuit composed of 8 cascaded shift registers as an example, the shift register of the fourth stage shift gate driving circuit outputs the scan signal only when the voltage signal of the pull-up node and the clock signal CK4 thereof are at high level, thereby realizing the gate line scan driving function. However, if the pull-down node in the shift register is in a dc high level operating state for a long time, as shown in fig. 6, the threshold voltage of the related thin film transistor may drift, and the noise reduction effect may be affected.
In order to reduce the time of the pull-down node in the dc high level operation state, a shift register is provided, please refer to fig. 7. The shift register includes a pull-up circuit 100, an output circuit 200, a pull-down circuit 300, a first pull-down control circuit 400, and a second pull-down control circuit 500.
The pull-up circuit 100 is connected to the input signal terminal F (n-2) of the shift register, and provides the input signal to a pull-up node q (n) in response to the input signal.
The output circuit 200 is connected to the pull-up node q (n) and an input terminal of a clock signal ck (n) for responding to the voltage signal of the pull-up node q (n) and providing the clock signal to the first output terminal g (n) and the second output terminal f (n) of the shift register.
The pull-down circuit 300 is connected to the first pull-down signal input terminal G (n +4), the second pull-down signal input terminal P (n-1) and the pull-down node P (n), and is configured to respond to the first pull-down signal, the second pull-down signal and the voltage signal of the pull-down node, and provide a low level signal to the pull-up node q (n) of the shift register and the first output terminal G (n) of the shift register, respectively.
The first pull-down control circuit 400 is connected to a high level signal VDD input terminal, a first switching signal input terminal Q (n +1), a second switching signal input terminal Q (n-1), a pull-down control node h (n), the pull-down node p (n), and the pull-up node Q (n) for providing the high level signal to the pull-down control node h (n) in response to the high level signal, providing the high level signal VDD to the pull-down node p (n) in response to the voltage signal of the pull-down control node h (n), and providing the low level signal to the pull-down node and the pull-down control node respectively in response to the first switching signal, the second switching signal, and the voltage signal of the pull-up node Q (n).
The second pull-down control circuit 500 is connected to the first pull-down control signal CK (n +5) input terminal, the second pull-down control signal CK (n +6) input terminal, and the high level signal input terminal, for responding to the first pull-down control signal CK (n +5) and the second pull-down control signal CK (n +6), and providing the low level signal to the high level signal input terminal, respectively.
It can be understood that, in the non-output stage, the shift register responds to the first pull-down control signal CK (n +5) and the second pull-down control signal CK (n +6), and provides the low level signals to the high level signal input ends respectively, so as to reduce the time that the high level signal input ends are in the dc high level operating state, thereby reducing the time that the pull-down nodes p (n) are in the dc high level operating state, further reducing the possibility that the threshold voltages of the associated thin film transistors drift, and improving the noise reduction effect.
In one embodiment, the first pull-down control circuit 400 includes a first switching branch 410, a second switching branch 420, a third switching branch 430, and a pull-down input branch 440.
The first switching branch 410 is connected to a first switching signal Q (n +1) input terminal, the pull-down control node h (n), and the pull-down node p (n) for responding to the first switching signal Q (n +1) and providing the low level signal to the pull-down node p (n) and the pull-down control node h (n), respectively.
The second switching branch 420 is connected to the pull-up node q (n), the pull-down control node h (n) and the pull-down node p (n) for responding to the voltage signal of the pull-up node q (n) and providing the low level signal VSS to the pull-down node p (n) and the pull-down control node h (n), respectively.
The third switching branch 430 is connected to the second switching signal Q (n-1) input terminal, the pull-down control node h (n), and the pull-down node p (n) to respond to the second switching signal Q (n-1) and provide the low level signals to the pull-down node p (n) and the pull-down control node h (n), respectively.
The pull-down input branch 440 is connected to the high level signal VDD input terminal, the pull-down control node h (n), and the pull-down node p (n), and is configured to provide the high level signal VDD to the pull-down control node h (n) in response to the high level signal VDD, and to provide the high level signal VDD to the pull-down node p (n) in response to the voltage signal of the pull-down control node h (n).
In this embodiment, the voltage signal of the pull-up node of the next shift register is used as the first switch signal to control the first switch branch 410, the voltage signal of the pull-up node of the current shift register is used as the second switch branch 420, and the voltage signal of the pull-up node of the previous shift register is used as the second switch signal to control the third switch branch 430, so that the pull-down node maintains a low level signal in the output stage and does not discharge the first output terminal.
In one embodiment, the second pull-down control circuit 500 comprises:
a first pull-down control branch 510 connected to the first pull-down control signal CK (n +5) input terminal and the high level signal input terminal, for responding to the first pull-down control signal CK (n +5) and providing the low level signal VSS to the high level signal input terminal; and
and a second pull-down control branch 520 connected to the second pull-down control signal CK (n +6) input terminal and the high level signal input terminal, for responding to the second pull-down control signal CK (n +6) and providing the low level signal VSS to the high level signal input terminal.
In this embodiment, the first pull-down control branch 510 is controlled by using the clock signal of the (n +5) th stage as the first pull-down control signal of the current stage. The second pull-down control branch 520 is controlled by using the clock signal of the (n +6) th stage as the second pull-down control signal of the current stage.
It can be understood that, in the non-output stage, when the voltage of the pull-down node cannot be reduced by the first pull-down control circuit 400, the time that the high-level signal input terminal is in the dc high-voltage state can be further reduced by the first pull-down control branch 510 and the second pull-down control branch 520, so as to reduce the time that the pull-down node is in the dc high-voltage state, and the voltage signal of the pull-down node in the non-output stage is kept as the ac voltage signal, thereby effectively suppressing the erroneous output caused by the drift of the threshold voltage of the device itself.
In one embodiment, the pull-down circuit 300 includes a first pull-down leg 310, a second pull-down leg 320, and a third pull-down leg 330.
The first pull-down branch 310 is connected to the input terminal of the first pull-down signal G (n +4), and is used for responding to the first pull-down signal G (n +4) and providing a low level signal VSS to the pull-up node q (n) of the shift register and the first output terminal G (n) of the shift register, respectively;
the second pull-down branch 320 is connected to the input end of the second pull-down signal P (n-1), and is used for responding to the second pull-down signal P (n-1) and providing the low level signal VSS to the pull-up node q (n) of the shift register and the first output end g (n) of the shift register, respectively; and
the third pull-down branch 330 is connected to the pull-down node p (n) for responding to the voltage signal of the pull-down node p (n) and providing the low level signal VSS to the pull-up node q (n) of the shift register and the first output terminal g (n) of the shift register, respectively.
In this embodiment, the output signal G (n +4) of the (n +4) th stage is used as the first pull-down signal to control the first pull-down branch 310. The voltage signal P (n-1) of the pull-down node of the (n-1) th stage is used as the second pull-down signal to control the second pull-down branch 320. The third pull-down branch 330 is controlled by the voltage signal of the current level pull-down node p (n). It is understood that the noise reduction effect of the shift register can be improved by discharging the pull-up node q (n) and the first output terminal g (n) uninterruptedly through the first pull-down branch 310, the second pull-down branch 320 and the third pull-down branch 330.
In one embodiment, the pull-up circuit 100 includes a first switch transistor T1. The gate and the drain of the first switch transistor T1 are connected to the input signal F (n-2), and the source is connected to the pull-up node q (n).
In this embodiment, the output signal F (n-2) of the (n-2) th stage is used as the input signal of the present stage, and the gate and the drain of the first switch transistor T1 are connected to the second output terminal of the (n-2) th stage.
In one embodiment, the output circuit 200 includes a second switch transistor T2, a third switch transistor T3, and a capacitor C.
The gate of the second switch transistor T2 is connected to the pull-up node q (n), the drain is connected to the input terminal of the clock signal ck (n), and the source is connected to the first output terminal of the shift register g (n).
The gate of the third switch transistor T3 is connected to the pull-up node q (n), the drain is connected to the clock signal input terminal, and the source is connected to the second output terminal f (n) of the shift register.
The capacitor C has one end connected to the pull-up node q (n), and the other end connected to the first output end g (n) of the shift register, and is configured to maintain the potential of the pull-up node q (n).
In this embodiment, the first output terminal is connected to the scan line to provide a scan signal for the display panel, and the output signal of the second output terminal is used as an n +2 th-level input signal to implement continuous scanning.
In one embodiment, the first pull-down branch 310 includes a fourth switching tube T4 and a fifth switching tube T5.
The gate of the fourth switching tube T4 is connected to the input of the first pull-down signal input G (n +4), the drain is connected to the first output of the shift register and the capacitor C, and the source is connected to the low level voltage signal VSS input.
The gate of the fifth switching transistor T5 is connected to the input terminal of the first pull-down signal input terminal G (n +4), the drain is connected to the pull-up node q (n), and the source is connected to the low-level voltage signal VSS input terminal.
The second pull-down branch 320 includes a sixth switching tube T6 and a seventh switching tube T7.
The sixth switch transistor T6 has a gate connected to the input terminal of the second pull-down signal P (n-1), a drain connected to the first output terminal g (n) of the shift register and the capacitor C, and a source connected to the input terminal of the low level voltage signal VSS.
The gate of the seventh switch transistor T7 is connected to the input terminal of the second pull-down signal P (n-1), the drain is connected to the pull-up node q (n), and the source is connected to the input terminal of the low-level voltage signal VSS.
The third pull-down branch 330 includes an eighth switch tube T8 and a ninth switch tube T9.
The eighth switch transistor T8 has a gate connected to the pull-down node p (n), a drain connected to the first output terminal g (n) of the shift register and the capacitor C, and a source connected to the low level voltage signal VSS input terminal.
The ninth switching tube T9 has a gate connected to the pull-down node p (n), a drain connected to the pull-up node q (n), and a source connected to the low-level voltage signal VSS input terminal.
In one embodiment, the pull-down input branch 440 includes a tenth switching tube T10 and an eleventh switching tube T11.
The tenth switching tube T10 has a gate and a drain both connected to the high level signal VDD input terminal, and a source connected to the pull-down control node h (n).
The eleventh switch tube T11 has a gate connected to the pull-down control node h (n), a drain connected to the high level signal VDD input terminal, and a source connected to the pull-down node p (n).
The first switching branch 410 includes a twelfth switching tube T12 and a thirteenth switching tube T13.
A gate of the twelfth switching tube T12 is connected to the input terminal of the first switching signal Q (n +1), a drain thereof is connected to the pull-down control node h (n), and a source thereof is connected to the low-level signal VSS input terminal; and
the gate of the thirteenth switching transistor T13 is connected to the input terminal of the first switching signal Q (n +1), the drain thereof is connected to a pull-down node p (n), and the source thereof is connected to the input terminal of the low level signal VSS.
The second switching branch 420 includes a fourteenth switching tube T14 and a fifteenth switching tube T15.
The gate of the fourteenth switching tube T14 is connected to the pull-up node q (n), the drain is connected to the pull-down control node h (n), and the source is connected to the low level signal VSS input terminal.
The gate of the fifteenth switching tube T15 is connected to the pull-up node q (n), the drain is connected to the pull-down node p (n), and the source is connected to the low level signal VSS input terminal.
The third switching branch 430 includes a sixteenth switching tube T16 and a seventeenth switching tube T17.
A gate of the sixteenth switching tube T16 is connected to the input terminal of the second switching signal Q (n-1), a drain thereof is connected to the pull-down control node h (n), and a source thereof is connected to the low level signal VSS input terminal; and
the gate of the seventeenth switching transistor T17 is connected to the input terminal of the second switching signal Q (n-1), the drain thereof is connected to a pull-down node p (n), and the source thereof is connected to the input terminal of the low level signal VSS.
In this embodiment, the gates of the twelfth and thirteenth switching tubes T12 and T13 are connected to the pull-up node Q (n +1) of the (n +1) th stage, and are responsive to the voltage signal of the pull-up node Q (n +1) of the (n +1) th stage. The gates of the fourteenth and fifteenth switching tubes T14 and T15 are connected to the pull-up node q (n) of the current stage (i.e., the nth stage) in response to the voltage signal of the pull-up node q (n) of the previous stage. The gates of the sixteenth switch tube T16 and the seventeenth switch tube T17 are connected to the pull-up node Q (n-1) of the (n-1) th stage in response to the voltage signal of the pull-up node Q (n-1) of the (n-1) th stage. Therefore, the control signal can ensure that the pull-down node p (n) of the current stage is kept at the low level for the output periods of the (n-1) th stage, the current stage, and the (n +1) th stage.
In one embodiment, the first pull-down control branch 510 includes an eighteenth switching tube T18, a gate of the eighteenth switching tube T18 is connected to the first pull-down control signal CK (n +5) input terminal, a drain of the eighteenth switching tube is connected to the high-level signal input terminal, and a source of the eighteenth switching tube is connected to the low-level signal VSS input terminal. The second pull-down control branch 520 includes a nineteenth switch T19, a gate of the nineteenth switch T19 is connected to the input terminal of the second pull-down control signal CK (n +6), a drain of the nineteenth switch is connected to the input terminal of the high level signal, and a source of the nineteenth switch is connected to the input terminal of the low level signal VSS.
In this embodiment, the clock signal CK (n +5) of the (n +5) th stage is used as the first pull-down control signal of the present stage, and the gate of the eighteenth switching tube T18 is connected to the input terminal of the clock signal CK (n +5) of the (n +5) th stage. The clock signal CK (n +6) of the (n +6) th stage is used as the second pull-down control signal of the present stage, and the gate of the nineteenth switching tube T19 is connected to the input terminal of the clock signal CK (n +6) of the (n +6) th stage.
In one embodiment, all the switch tubes in the present application are N-type switch tubes.
In one embodiment, the switching tubes are all field effect tubes or all triodes. When the switching tubes all adopt field effect tubes or triodes, circuit design is convenient to carry out. In addition, according to the actual design requirement, a part of the LED lamp adopts a field effect transistor, and the other part of the LED lamp adopts a triode.
Based on the same inventive concept, the present application further provides a gate driving circuit, the gate driving circuit provided in the embodiment of the present application includes cascaded shift registers of different levels, and the cascaded shift registers are shift registers in any of the above embodiments. Specifically, the array substrate grid driving circuit comprises N levels, wherein N is the number of grid lines, and N is more than 2 and less than N-6.
In this embodiment, the shift register includes a pull-up circuit 100, an output circuit 200, a pull-down circuit 300, a first pull-down control circuit 400, and a second pull-down control circuit 500.
The pull-up circuit 100 is connected to the second output terminal of the n-2 th stage shift register, and is configured to respond to the output signal of the n-2 th stage shift register and provide the output signal of the n-2 th stage shift register to a pull-up node q (n).
The output circuit 200 is connected to the pull-up node q (n) and a clock signal input terminal, and is configured to respond to the voltage signal of the pull-up node q (n) and provide a clock signal to the first output terminal and the second output terminal of the shift register.
The pull-down circuit 300 is connected to the pull-down node P (n-1) of the (n-1) th stage shift register, the pull-down node P (n) of the shift register, and the first output terminal G (n +4) of the (n +4) th stage shift register, and is configured to respond to the voltage signals of the pull-down node P (n-1) of the (n-1) th stage shift register, the pull-down node P (n) and the first output terminal of the (n +4) th stage shift register, and provide the low level signal VSS to the pull-up node q (n) of the shift register and the first output terminal of the shift register, respectively.
The first pull-down control circuit 400 is connected to an input terminal of a high level signal VDD, a pull-up node Q (n +1) of an n +1 th stage register, a pull-up node Q (n-1) of an n-1 th stage shift register, a pull-up node Q (n) of the shift register, a pull-down control node h (n), and a pull-down node p (n) for supplying the high level signal VDD to the pull-down control node h (n) in response to the high level signal VDD, supplying the high level signal VDD to the pull-down node p (n) in response to a voltage signal of the pull-up node Q (n +1) of the n +1 th stage register, a voltage signal of the pull-up node Q (n-1) of the n-1 th stage shift register, and a voltage signal of the pull-up node Q (n) of the shift register, the low level signal VSS is supplied to the pull-down node p (n) and the pull-down control node h (n), respectively.
The second pull-down control circuit 500 is connected to the clock signal input terminals of the (n +5) th and (n +6) th stage shift registers, and is configured to respond to the clock signals of the (n +5) th and (n +6) th stage shift registers and provide the low level signal VSS to the high level signal input terminal;
wherein N is more than 2 and less than N-6, N is the number of cascaded shift registers, and N and N are positive integers.
In addition, in the present embodiment, the signal input terminals for the first two stages and the first pull-down circuit 300 for the last four stages are connected to the start signal input terminal.
Fig. 8 is a schematic diagram of a cascade structure of a gate driving circuit, fig. 9 is a timing diagram of each signal terminal of the shift register, and a method for operating an nth-stage shift register in the gate driving circuit according to the embodiment of the present application is described below with reference to fig. 8 and 9, specifically, an operation method for a 4 th-stage shift register in the gate driving circuit including 8 shift registers is described.
In the first stage S1, the clock signals CK4 and CK8 are low level signals, the clock signal CK2 is a high level signal, the high level signal outputted from the shift register of the second stage is that the first switch transistor T1 is turned on to charge the pull-up node Q (4), the pull-up node Q (4) is raised to a high level, the second switch transistor T2 and the third switch transistor T3 are turned on, but the first output terminal G (4) and the second output terminal F (4) are kept at a low level because CK4 considers the low level, and at the same time, the low level signal VSS is supplied to the high level signal input terminal in response to the nineteenth switch transistor T19 of the clock signal CK2 being turned on, and the high level input terminal is a low level voltage signal; the fourteenth and fifteenth switching transistors T14 and T15, which are responsive to the voltage signal of the pull-up node Q (4), are also turned on to supply the low level signal VSS to the pull-down node P (4) and the pull-down control node H (4), so that the pull-down node P (4) is maintained at a low level at this time.
In the second stage S2, the clock signal CK4 is a high level signal, the clock signals CK2 and CK8 are low level signals, the first switch transistor T1 is turned off when the output of the second stage shift register is low level signal, but the pull-up node Q (4) still keeps high level due to the existence of the capacitor C; meanwhile, the clock signal CK4 is at a high level, the potential of the pull-up node Q (4) continues to rise due to the bootstrap effect (boosting) of the capacitor C, and the second switch T2 and the third switch T3, which are responsive to the voltage signal of the pull-up node Q (4), are turned on.
Meanwhile, the fourteenth switching tube T14 and the fifteenth switching tube T15, which are responsive to the voltage signal of the pull-up node Q (4), are also turned on to provide the low level signal VSS to the pull-down node P (4) and the pull-down control node H (4), so that the pull-down node P (4) is kept at a low level at this time, and the eighth switching tube T8 and the ninth switching tube T9 are turned off; a pull-down node P (3) of the third stage shift register maintains a low potential, and a sixth switch responding to a voltage signal of the pull-down node P (3) and a seventh switch tube T7 are turned off; the clock signal CK8 is at low level, the output signal of the first output terminal G (8) of the eighth stage shift register is at low level, and the fourth switch transistor T4 and the fifth switch transistor T5 are turned off to prevent discharging the pull-up node Q (4).
Therefore, the output signals of the first output terminal G (4) and the second output terminal F (4) are high level signals at this time.
In the third stage S3, the clock signals CK2, CK4, and CK8 are low-level signals, and the clock signal CK6 is high-level.
The pull-down node P (3) of the third stage shift register is at a high level in a second half output period of the clock signal CK6, the sixth switching transistor T6 and the seventh switching transistor T7 responding to the voltage signal of the pull-down node P (3) are turned on to discharge the pull-up node Q (4), and the pull-up node Q (4) still maintains a high level due to the capacitor C.
Meanwhile, the pull-up node Q (4) is at a high potential, and the fourteenth switching transistor T14 and the fifteenth switching transistor T15, which are responsive to the pull-up node Q (4), are turned on to provide the low level signal VSS to the pull-down node P (4) and the pull-down control node H (4), so that the pull-down node P (4) is maintained at a low level at this time.
In the fourth stage S4, during the first half period of the fourth stage, the clock signals CK1, CK2, CK3, CK4, CK5 and CK6 are all low level signals, the clock signals CK7 and CK8 are high level signals, the switching tubes in the first pull-down control circuit 400 and the second pull-down control circuit 500 are both turned off, the high level signal input terminal provides a high level signal for the pull-down node P (4), and the voltage signal of the pull-down node P (4) is a high level voltage signal.
In the second half period of the fourth stage, the clock signals CK2, CK3, CK4, CK5, CK6 and CK7 are low level signals, and the clock signals CK1 and CK8 are high level signals, at this time, in response to the eighteenth switching tube T18 of the clock signal CK1 being turned on, the low level signal VSS is supplied to the pull-down node P (4) through the eighteenth switching tube T18, the pull-down node P (4) is discharged, and the voltage signal of the pull-down node P (4) is lowered to a low level voltage signal.
In the fifth stage S5, during the first half of the fifth stage, the clock signals CK3, CK4, CK5, CK6, CK7 and CK8 are low level signals, the clock signals CK1 and CK2 are high level signals, the eighteenth switching tube T18 responding to the clock signal CK1 and the nineteenth switching tube T19 responding to the clock signal CK2 are both turned on, the low level signal VSS is provided to the high level signal input terminal, the high level signal input terminal is a low level voltage signal, the high level signal cannot be provided to the pull-down node P (4), and the pull-down node P (4) is at a low level.
In the second half period of the fifth stage, the clock signals CK1, CK4, CK5, CK6, CK7 and CK8 are low level signals, the clock signals CK2 and CK3 are high level signals, and the nineteenth switching transistor T19 responding to the clock signal CK2 is turned on to supply the low level signal VSS to the high level signal input terminal, which is a low level voltage signal that cannot supply the high level signal to the pull-down node P (4), and the pull-down node P (4) is at a low level.
In the sixth stage S6, during the first half period of the sixth stage, the clock signals CK1, CK2, CK5, CK6, CK7 and CK8 are low level signals, and the clock signals CK3 and CK4 are high level signals, at this time, the switches in the first pull-down control circuit 400 and the second pull-down control circuit 500 are both turned off, the voltage signal of the pull-down control node H (4) is a high level voltage signal, the eleventh switch T11 is turned on, the high level signal VDD is provided to the pull-down node P (4), and the voltage signal of the pull-down node P (4) is a high level voltage signal.
In the second half of the sixth phase, the clock signals CK1, CK2, CK3, CK6, CK7 and CK8 are low level signals, and the clock signals CK4 and CK5 are high level signals, at this time, the switching tubes in the first pull-down control circuit 400 and the second pull-down control circuit 500 are both off, the voltage signal of the pull-down control node H (4) is a high level voltage signal, the eleventh switching tube T11 is on, the high level signal VDD is provided to the pull-down node P (4), and the voltage signal of the pull-down node P (4) is a high level voltage signal.
In summary, the present application provides a shift register and a gate driving circuit. The shift register includes a pull-up circuit 100, an output circuit 200, a pull-down circuit 300, a first pull-down control circuit 400, and a second pull-down control circuit 500. The pull-up circuit 100 is connected to the input signal terminal of the shift register, and provides the input signal to a pull-up node q (n) in response to the input signal. The output circuit 200 is connected to the pull-up node q (n) and a clock signal input terminal, and is configured to respond to the voltage signal of the pull-up node q (n) and provide a clock signal to the first output terminal and the second output terminal of the shift register. The pull-down circuit 300 is connected to the first pull-down signal input terminal G (n +4), the second pull-down signal input terminal P (n-1) and the pull-down node P (n), and is configured to respond to the first pull-down signal input terminal G (n +4), the second pull-down signal P (n-1) and the voltage signal of the pull-down node P (n), and provide the low level signal VSS to the pull-up node q (n) of the shift register and the first output terminal of the shift register, respectively. The first pull-down control circuit 400 is connected to a high level signal VDD input terminal, a first switching signal Q (n +1) input terminal, a second switching signal Q (n-1) input terminal, a pull-down control node h (n), the pull-down node p (n), and the pull-up node Q (n), for providing the high level signal VDD to the pull-down control node H (n) in response to the high level signal VDD, providing the high level signal VDD to the pull-down node P (n) in response to a voltage signal of the pull-down control node H (n), and a voltage signal responsive to a first switching signal Q (n +1), a second switching signal Q (n-1) and the pull-up node Q (n), and supplies the low level signal VSS to the pull-down node p (n) and the pull-down control node h (n), respectively. The second pull-down control circuit 500 is connected to the first pull-down control signal input terminal, the second pull-down control signal input terminal, and the high level signal input terminal, and is configured to respond to the first pull-down control signal and the second pull-down control signal and provide the low level signal VSS to the high level signal input terminal. In this application, in a non-output stage, the shift register responds to the first pull-down control signal and the second pull-down control signal, and provides the low level signal VSS to the high level signal input end respectively, so as to reduce the time that the high level signal input end is in the dc high level working state, thereby reducing the time that the pull-down node p (n) is in the dc high level working state, and further reducing the possibility that the threshold voltage of the related thin film transistor drifts, and improving the noise reduction effect.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A shift register, comprising:
the pull-up circuit is connected with the input signal end of the shift register, is used for responding to an input signal and provides the input signal to a pull-up node;
the output circuit is connected with the pull-up node and the clock signal input end, is used for responding to the voltage signal of the pull-up node and provides a clock signal to the first output end and the second output end of the shift register;
a pull-down circuit connected to the first pull-down signal input terminal, the second pull-down signal input terminal and the pull-down node, for responding to the first pull-down signal, the second pull-down signal and the voltage signal of the pull-down node, and providing a low level signal to the pull-up node of the shift register and the first output terminal of the shift register, respectively;
the first pull-down control circuit is connected with a high level signal input end, a first switch signal input end, a second switch signal input end, a pull-down control node, the pull-down node and the pull-up node, and is used for responding to the high level signal, providing the high level signal to the pull-down control node, responding to a voltage signal of the pull-down control node, providing the high level signal to the pull-down node, responding to the first switch signal, the second switch signal and the voltage signal of the pull-up node, and providing the low level signal to the pull-down node and the pull-down control node respectively; and
the second pull-down control circuit is connected with the first pull-down control signal input end, the second pull-down control signal input end and the high level signal input end, is used for responding to the first pull-down control signal and the second pull-down control signal and provides the low level signal for the high level signal input end;
the input signal is an output signal of an n-2 th-stage shift register, the first pull-down signal is an output signal of an n +4 th-stage shift register, the second pull-down signal is a voltage signal of an n-1 th-stage pull-down node, the first switch signal is a voltage signal of an n +1 th-stage pull-up node of the shift register, the second switch signal is a voltage signal of an n-1 th-stage pull-up node of the shift register, the first pull-down control signal is a clock signal of an n +5 th-stage shift register, and the second pull-down control signal is a clock signal of an n +6 th-stage shift register.
2. The shift register of claim 1, wherein the first pull-down control circuit comprises:
a first switching branch, connected to a first switching signal input terminal, the pull-down control node and the pull-down node, for responding to the first switching signal and providing the low level signal to the pull-down node and the pull-down control node, respectively;
the second switch branch circuit is connected with the pull-up node, the pull-down control node and the pull-down node, is used for responding to a voltage signal of the pull-up node, and provides the low-level signal to the pull-down node and the pull-down control node respectively;
a third switching branch, connected to the second switching signal input terminal, the pull-down control node and the pull-down node, for responding to the second switching signal and providing the low level signal to the pull-down node and the pull-down control node, respectively; and
and the pull-down input branch is connected with the high-level signal input end, the pull-down control node and the pull-down node, and is used for responding to the high-level signal and providing the high-level signal for the pull-down control node, and responding to a voltage signal of the pull-down control node and providing the high-level signal for the pull-down node.
3. The shift register of claim 2, wherein the second pull-down control circuit comprises:
a first pull-down control branch, connected to the first pull-down control signal input terminal and the high level signal input terminal, for responding to the first pull-down control signal and providing the low level signal to the high level signal input terminal; and
and the second pull-down control branch is connected with the second pull-down control signal input end and the high level signal input end, is used for responding to the second pull-down control signal and provides the low level signal for the high level signal input end.
4. The shift register of claim 3, wherein the pull-down circuit comprises:
a first pull-down branch, connected to the first pull-down signal input terminal, for responding to the first pull-down signal and providing a low level signal to a pull-up node of the shift register and a first output terminal of the shift register, respectively;
a second pull-down branch, connected to the second pull-down signal input terminal, for responding to the second pull-down signal and providing a low level signal to the pull-up node of the shift register and the first output terminal of the shift register, respectively; and
and the third pull-down branch is connected with the pull-down node and used for responding to the voltage signal of the pull-down node and respectively providing a low level signal to the pull-up node of the shift register and the first output end of the shift register.
5. The shift register of claim 4, wherein the pull-up circuit comprises:
and the grid electrode and the drain electrode of the first switch tube are connected with the input signal end, and the source electrode of the first switch tube is connected with the pull-up node.
6. The shift register of claim 5, wherein the output circuit comprises:
a grid electrode of the second switch tube is connected with the pull-up node, a drain electrode of the second switch tube is connected with the clock signal input end, and a source electrode of the second switch tube is connected with the first output end of the shift register;
a grid electrode of the third switching tube is connected with the pull-up node, a drain electrode of the third switching tube is connected with the clock signal input end, and a source electrode of the third switching tube is connected with the second output end of the shift register; and
and one end of the capacitor is connected with the pull-up node, and the other end of the capacitor is connected with the first output end of the shift register.
7. The shift register of claim 6,
the first pull-down leg comprises:
a grid electrode of the fourth switching tube is connected with the first pull-down signal input end, a drain electrode of the fourth switching tube is connected with the first output end of the shift register and the capacitor, and a source electrode of the fourth switching tube is connected with the low level voltage signal input end; and
a grid electrode of the fifth switching tube is connected with the first pull-down signal input end, a drain electrode of the fifth switching tube is connected with the pull-up node, and a source electrode of the fifth switching tube is connected with the low-level voltage signal input end;
the second pull-down leg comprises:
a sixth switching tube, a gate of which is connected to the second pull-down signal input terminal, a drain of which is connected to the first output terminal of the shift register and the capacitor, and a source of which is connected to the low level voltage signal input terminal; and
a grid electrode of the seventh switching tube is connected with the second pull-down signal input end, a drain electrode of the seventh switching tube is connected with the pull-up node, and a source electrode of the seventh switching tube is connected with the low-level voltage signal input end;
the third pull-down leg comprises:
a gate of the eighth switching tube is connected with the pull-down node, a drain of the eighth switching tube is connected with the first output end of the shift register and the capacitor, and a source of the eighth switching tube is connected with the low level voltage signal input end; and
and the grid electrode of the ninth switching tube is connected with the pull-down node, the drain electrode of the ninth switching tube is connected with the pull-up node, and the source electrode of the ninth switching tube is connected with the low-level voltage signal input end.
8. The shift register of claim 7,
the pull-down input branch comprises:
a grid electrode and a drain electrode of the tenth switching tube are both connected with the high-level signal input end, and a source electrode of the tenth switching tube is connected with the pull-down control node; and
a grid electrode of the eleventh switch tube is connected with the pull-down control node, a drain electrode of the eleventh switch tube is connected with the high-level signal input end, and a source electrode of the eleventh switch tube is connected with the pull-down node;
the first switching leg includes:
a twelfth switching tube, a gate of which is connected to the first switching signal input terminal, a drain of which is connected to the pull-down control node, and a source of which is connected to the low level signal input terminal; and
a gate of the thirteenth switching tube is connected with the first switching signal input end, a drain of the thirteenth switching tube is connected with the pull-down node, and a source of the thirteenth switching tube is connected with the low level signal input end;
the second switching leg comprises:
a fourteenth switching tube, a gate of which is connected to the pull-up node, a drain of which is connected to the pull-down control node, and a source of which is connected to the low level signal input terminal; and
a fifteenth switching tube, wherein a grid electrode is connected with the pull-up node, a drain electrode is connected with the pull-down node, and a source electrode is connected with the low-level signal input end;
the third switching branch includes:
a sixteenth switching tube, a gate of which is connected to the second switching signal input terminal, a drain of which is connected to the pull-down control node, and a source of which is connected to the low level signal input terminal; and
and the grid electrode of the seventeenth switching tube is connected with the second switching signal input end, the drain electrode of the seventeenth switching tube is connected with the pull-down node, and the source electrode of the seventeenth switching tube is connected with the low level signal input end.
9. The shift register of claim 8,
the first pull-down control branch comprises an eighteenth switching tube, the grid electrode of the eighteenth switching tube is connected with the first pull-down control signal input end, the drain electrode of the eighteenth switching tube is connected with the high level signal input end, and the source electrode of the eighteenth switching tube is connected with the low level signal input end; and
the second pull-down control branch comprises a nineteenth switching tube, a grid electrode of the nineteenth switching tube is connected with the second pull-down control signal input end, a drain electrode of the nineteenth switching tube is connected with the high level signal input end, and a source electrode of the nineteenth switching tube is connected with the low level signal input end.
10. A gate driver circuit comprising cascaded shift registers of respective stages, the shift register comprising:
the pull-up circuit is connected with the second output end of the (n-2) th-stage shift register, is used for responding to the output signal of the (n-2) th-stage shift register and provides the output signal of the (n-2) th-stage shift register to a pull-up node;
the output circuit is connected with the pull-up node and the clock signal input end, is used for responding to the voltage signal of the pull-up node and provides a clock signal to the first output end and the second output end of the shift register;
the pull-down circuit is connected with the pull-down node of the (n-1) th-stage shift register, the pull-down node of the shift register and the first output end of the (n +4) th-stage shift register, is used for responding to the voltage signal output by the first output end of the (n +4) th-stage shift register and respectively provides a low level signal to the pull-up node of the shift register and the first output end of the shift register;
a first pull-down control circuit, connected to a high level signal input terminal, a pull-up node of the (n +1) th stage register, a pull-up node of the (n-1) th stage shift register, a pull-up node of the shift register, a pull-down control node, and the pull-down node, for providing the high level signal to the pull-down control node in response to the high level signal, providing the high level signal to the pull-down node in response to a voltage signal of the pull-down control node, and providing the low level signal to the pull-down node and the pull-down control node in response to a voltage signal of the pull-up node of the (n +1) th stage register, a voltage signal of the pull-up node of the (n-1) th stage shift register, and a voltage signal of the pull-up node of the shift register, respectively; and
a second pull-down control circuit, connected to the clock signal input terminals of the (n +5) th and (n +6) th stage shift registers, for responding to the clock signals of the (n +5) th and (n +6) th stage shift registers and providing the low level signal to the high level signal input terminal;
wherein N is more than 2 and less than N-6, N is the number of grid lines, and N and N are positive integers.
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| TWI406503B (en) * | 2010-12-30 | 2013-08-21 | Au Optronics Corp | Shift register circuit |
| CN102682727B (en) * | 2012-03-09 | 2014-09-03 | 北京京东方光电科技有限公司 | Shift register unit, shift register circuit, array substrate and display device |
| CN103151011B (en) * | 2013-02-28 | 2016-04-27 | 北京京东方光电科技有限公司 | A kind of shift register cell and gate driver circuit |
| CN103985369B (en) * | 2014-05-26 | 2017-02-15 | 深圳市华星光电技术有限公司 | Array substrate row driving circuit and liquid crystal display device |
| KR102536161B1 (en) * | 2016-03-31 | 2023-05-25 | 삼성디스플레이 주식회사 | Scan driver and display apparatus having the same |
| CN108986732B (en) * | 2018-08-13 | 2021-07-23 | 惠科股份有限公司 | Shift register circuit and display device |
-
2018
- 2018-12-26 CN CN201811600809.2A patent/CN109859701B/en active Active
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|---|---|
| CN109859701A (en) | 2019-06-07 |
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