CN113658539B

CN113658539B - GOA circuit

Info

Publication number: CN113658539B
Application number: CN202110966895.4A
Authority: CN
Inventors: 李育智
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2021-08-23
Filing date: 2021-08-23
Publication date: 2023-10-31
Anticipated expiration: 2041-08-23
Also published as: CN113658539A

Abstract

The application discloses a GOA circuit, which comprises a plurality of stages of cascaded GOA units. The N-th GOA unit comprises a pull-up control module, a pre-boosting module, a pull-up module, a pull-down maintenance module and a bootstrap capacitor, wherein N is an integer larger than 0. According to the application, the pre-boosting module is additionally arranged in the GOA unit, and the bootstrap effect of the pre-boosting module is utilized to improve the potential of the first node, so that the starting degree of the transistor block in the pull-up mode is improved, the effect that the driving voltage can still keep the GOA circuit to normally work in a larger threshold voltage deviation range is achieved, and the power consumption of the GOA circuit is reduced.

Description

GOA circuit

Technical Field

The application relates to the technical field of display, in particular to a GOA circuit.

Background

The grid driving technology (Gate Driver on Array, abbreviated as GOA) of the array substrate integrates a grid driving circuit on the array substrate of the display panel to realize a progressive scanning driving mode, so that a grid driving circuit part can be omitted, the display panel has the advantages of reducing production cost and realizing narrow frame design of the panel, and is used for various displays.

For large-size display panels, the voltage drop (RC Delay) of the line is large, so that in order to improve the charging capability of the scanning signals output by the scanning signals, a large driving voltage is required, and the GOA circuit is ensured to normally work in a large threshold voltage drift range. However, a larger driving voltage increases the power consumption of the GOA circuit.

Disclosure of Invention

The application provides a GOA circuit, which can keep the GOA circuit to normally work in a larger threshold voltage range when the driving voltage of the GOA circuit is reduced, so that the power consumption of the GOA circuit is reduced.

The application provides a GOA circuit, which comprises a plurality of stages of cascaded GOA units, wherein the N-th stage GOA unit comprises: the device comprises a pull-up control module, a pre-boosting module, a pull-up module, a pull-down maintenance module and a bootstrap capacitor;

the pull-up control module is connected with the N-m-th level transmission signal and is electrically connected with the first node, and is used for outputting the N-m-th level transmission signal to the first node under the control of the N-m-th level transmission signal;

the pre-boosting module is connected with the N-m-th level transmission signal and the clock signal, is electrically connected with the first node and the second node and is used for pulling the potential of the first node under the control of the N-m-th level transmission signal and the clock signal;

the pull-up module is connected with an N-th clock signal, is electrically connected with the first node, the N-th scanning signal output end and the N-th level transmission signal output end, and is used for outputting the N-th scanning signal and the N-th level transmission signal under the potential control of the first node;

The pull-down module is connected to the n+m-th level transmission signal, the first reference low-level signal and the second reference low-level signal, and is electrically connected to the first node and the N-th scanning signal output end, and is used for pulling down the potential of the first node and the potential of the N-th scanning signal under the control of the n+m-th level transmission signal, the first reference low-level signal and the second reference low-level signal;

the pull-down maintaining module is connected to a control signal, the N-m-th level transmission signal, the first reference low level signal and the second reference low level signal, and is electrically connected to the first node, the second node, the nth level scanning signal output end and the nth level transmission signal output end, and is used for maintaining the potential of the first node and the potential of the nth level transmission signal at the potential of the second reference low level signal and the potential of the nth level scanning signal at the potential of the first reference low level signal;

one end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the nth stage scanning signal output end;

The pull-up control module comprises a first transistor, wherein the grid electrode of the first transistor and the source electrode of the first transistor are connected with the N-m-th level transmission signal, and the drain electrode of the first transistor is electrically connected with the first node;

the pre-boosting module comprises a second transistor and a capacitor, wherein the grid electrode of the second transistor is connected with the N-m-th level transmission signal, the source electrode of the second transistor is connected with the N-1-th level clock signal, the drain electrode of the second transistor and one end of the capacitor are electrically connected with the second node, and the other end of the capacitor is electrically connected with the first node;

the pull-up module comprises a third transistor and a fourth transistor, wherein the grid electrode of the third transistor and the grid electrode of the fourth transistor are electrically connected to the first node, the source electrode of the third transistor and the source electrode of the fourth transistor are both connected with the N-th stage clock signal, the drain electrode of the third transistor is electrically connected to the N-th stage signal output end, and the drain electrode of the fourth transistor is electrically connected to the N-th stage scanning signal output end;

when the N-m-th level transmission signal is at a high potential, the first transistor and the second transistor are both turned on, the potential of the first node is pulled up to the potential of the N-m-th level transmission signal, in the latter half stage of the N-m-th level transmission signal being at the high potential, the N-1-th level clock signal is raised from the low potential to the high potential, the capacitor bootstraps and pulls up the potential of the first node, the third transistor and the fourth transistor are both turned on, the N-th level clock signal is converted from the low potential to the high potential, the third transistor outputs the N-th level transmission signal to the N-th level transmission signal output end, and the fourth transistor outputs the N-th level scanning signal to the N-th level scanning signal output end.

Optionally, in some embodiments of the present application, the GOA circuit receives K clock signals, where the K clock signals are valid when the working cycle of the GOA circuit is sequentially divided;

the clock signal is the clock signal accessed by the N-N-th GOA unit, wherein K is more than or equal to 4,1/2K is more than or equal to m is more than or equal to 1, K, m and N are integers.

Optionally, in some embodiments of the present application, the pull-down module includes a fifth transistor and a sixth transistor;

the grid electrode of the fifth transistor and the grid electrode of the sixth transistor are both connected with the n+m-th level transmission signal, the source electrode of the fifth transistor is connected with the first reference low level signal, the drain electrode of the fifth transistor is electrically connected with the first node, the source electrode of the sixth transistor is connected with the second reference low level signal, and the drain electrode of the sixth transistor is electrically connected with the N-th level scanning signal output end.

Optionally, in some embodiments of the present application, the pull-down maintaining module includes a first pull-down maintaining unit, and the first pull-down maintaining unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

The gate of the seventh transistor, the gate of the eighth transistor, the gate of the ninth transistor, the gate of the tenth transistor, the drain of the eleventh transistor, the drain of the twelfth transistor, and the drain of the thirteenth transistor are all electrically connected to a third node, the source of the seventh transistor, the source of the eighth transistor, the source of the ninth transistor, the source of the twelfth transistor, and the source of the thirteenth transistor are all connected to the first reference low level signal, the drain of the seventh transistor is electrically connected to the second node, the drain of the eighth transistor is electrically connected to the first node, the drain of the ninth transistor is electrically connected to the N-stage signal output terminal, the source of the tenth transistor is connected to the second reference low level signal, the drain of the tenth transistor is electrically connected to the N-stage signal output terminal, the gates of the eleventh transistor and the eleventh transistor are all connected to the N-stage signal input terminal, and the drain of the thirteenth transistor are all connected to the N-stage signal input terminal.

Optionally, in some embodiments of the present application, the control signal is the nth stage clock signal, and the first pull-down maintaining unit further includes a fourteenth transistor;

a gate of the fourteenth transistor is connected to a complementary clock signal, a source of the fourteenth transistor is connected to the first reference low level signal, and a drain of the fourteenth transistor is electrically connected to the third node;

wherein the potential of the complementary clock signal is kept inverted from the potential of the nth stage clock signal.

Optionally, in some embodiments of the present application, the nth stage GOA unit further includes a first reset module;

the first reset module is connected to a reset signal, the first reference low-level signal and the second reference low-level signal, and is electrically connected to the first node, the nth scanning signal output end and the nth transmission signal output end, and is used for resetting the potential of the first node, the potential of the nth scanning signal and the potential of the nth transmission signal under the control of the reset signal, the first reference low-level signal and the second reference low-level signal.

Optionally, in some embodiments of the present application, the first reset module includes a thirty-first transistor, a thirty-second transistor, and a thirty-third transistor;

The gate of the thirty-first transistor, the gate of the thirty-second transistor and the gate of the thirty-third transistor are all connected to the reset signal, the source of the thirty-first transistor and the source of the thirty-second transistor are both connected to the first reference low level signal, the drain of the thirty-first transistor is electrically connected to the first node, the drain of the thirty-second transistor is electrically connected to the N-th stage signal output end, the source of the thirty-third transistor is connected to the second reference low level signal, and the drain of the thirty-third transistor is electrically connected to the N-th stage scanning signal output end.

Optionally, in some embodiments of the present application, the pull-down maintaining module further includes a second pull-down maintaining unit, the control signal includes a first low frequency clock signal and a second low frequency clock signal, and a gate of the eleventh transistor and a source of the eleventh transistor are both connected to the first low frequency clock signal;

the second pull-down maintaining unit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twenty first transistor;

The grid electrode of the fifteenth transistor, the grid electrode of the sixteenth transistor, the grid electrode of the seventeenth transistor, the grid electrode of the eighteenth transistor, the drain electrode of the nineteenth transistor, the drain electrode of the twentieth transistor and the drain electrode of the twenty first transistor are all electrically connected to a third node, the source electrode of the fifteenth transistor, the source electrode of the sixteenth transistor, the source electrode of the seventeenth transistor, the source electrode of the twenty first transistor and the source electrode of the twenty first transistor are all connected to the first reference low level signal, the drain electrode of the fifteenth transistor is electrically connected to the second node, the drain electrode of the sixteenth transistor is electrically connected to the first node, the drain electrode of the seventeenth transistor is electrically connected to an N-th stage transmission signal output end, the source electrode of the eighteenth transistor is connected to the second reference low level signal, the drain electrode of the eighteenth transistor is electrically connected to the N-th stage scanning signal output end, the grid electrode of the nineteenth transistor and the nineteenth transistor are all connected to the N-th node, and the nineteenth transistor are connected to the N-th stage transmission signal.

Optionally, in some embodiments of the present application, the nth stage GOA unit further includes a second reset module;

the second resetting module is connected to a resetting signal and the first reference low-level signal, and is electrically connected to the first node, and is used for resetting the potential of the first node under the control of the resetting signal.

The application provides a GOA circuit, which comprises a plurality of stages of cascaded GOA units. The N-th GOA unit comprises a pull-up control module, a pre-boosting module, a pull-up module, a pull-down maintenance module and a bootstrap capacitor, wherein N is an integer larger than 0. According to the application, the pre-boosting module is arranged in the GOA unit, and the bootstrap effect of the pre-boosting module is utilized to improve the potential of the first node, so that the starting degree of the transistor in the pull-up module is improved, the effect that the driving voltage is reduced and the GOA circuit can still normally work within a larger threshold voltage deviation range is achieved, and the power consumption of the GOA circuit is further reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a first structure of an N-th GOA unit according to the present application;

FIG. 2 is a schematic diagram of a second structure of an Nth GOA unit according to the present application;

FIG. 3 is a timing diagram of clock signals of an N-th GOA unit according to the present application;

FIG. 4 is a schematic diagram of a planar structure of a GOA circuit according to the present application;

FIG. 5 is a schematic circuit diagram of the N-th GOA unit shown in FIG. 1;

FIG. 6 is a timing diagram of a partial scan signal output from an Nth GOA unit according to the present application;

FIG. 7 is a schematic diagram of the relationship between the driving voltage and the threshold bias voltage provided by the present application;

FIG. 8 is a schematic circuit diagram of the N-th GOA unit shown in FIG. 2;

fig. 9 is a schematic structural diagram of a display panel provided by the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and description only, and is not intended to limit the application.

The present application provides a GOA circuit, which is described in detail below. It should be noted that the following description order of the embodiments is not intended to limit the preferred order of the embodiments of the present application.

Since the source and drain of the transistor used in the present application are symmetrical, the source and drain may be interchanged. In the present application, in order to distinguish between two electrodes of a transistor except a gate electrode, one of the electrodes is called a source electrode and the other electrode is called a drain electrode. In the present application, the middle terminal of the switching transistor is defined as the gate, the signal input terminal is defined as the source, and the signal output terminal is defined as the drain according to the embodiment in the drawings.

Referring to fig. 1 and 2, fig. 1 is a schematic diagram of a first structure of an nth stage GOA unit according to the present application. Fig. 2 is a second schematic structural diagram of an nth stage GOA unit according to the present application. The GOA circuit comprises a plurality of stages of GOA units in cascade connection. The nth stage GOA unit 100 includes: a pull-up control module 101, a pre-boost module 102, a pull-up module 103, a pull-down module 104, a pull-down maintenance module 105, and a bootstrap capacitor Cbt1.

The pull-up control module 101 is connected to the N-m-th level transmission signal ST (N-m) and is electrically connected to the first node QN. The pull-up control module 101 is configured to output the nth-mth level transmission signal ST (N-m) to the first node QN under control of the nth-mth level transmission signal ST (N-m). Wherein N and m are integers greater than 0, and N > m.

The pre-boost module 102 is connected to the N-m-th stage transmission signal ST (N-m) and the clock signal CK (N-N), and is electrically connected to the first node QN and the second node a. The pre-boost module 102 is configured to pull down the potential of the first node QN high under the control of the N-m-th stage pass signal ST (N-m) and the clock signal CK (N-N).

The pull-up module 103 is connected to the clock signal CK (N) of the present stage and is electrically connected to the first node QN, the nth stage scan signal output terminal C, and the nth stage pass signal output terminal B. The pull-up module 103 is configured to output an nth stage scan signal G (N) and an nth stage pass signal ST (N) under potential control of the first node QN.

The pull-down module 104 is connected to the n+m-th stage transmission signal ST (n+m), the first reference low level signal VSSQ, and the second reference low level signal VSSG, and is electrically connected to the first node QN and the nth stage scanning signal output terminal C. The pull-down module 104 is configured to pull down the potential of the first node QN and the potential of the nth stage scan signal G (N) under the control of the n+mth stage pass signal ST (n+m), the first reference low level signal VSSQ, and the second reference low level signal VSSG.

The pull-down maintaining module 105 is connected to the control signal, the N-m-th stage transmission signal ST (N-m), the first reference low level signal VSSQ and the second reference low level signal VSSG, and is electrically connected to the first node QN, the second node a, the N-th stage scanning signal output terminal C and the N-th stage transmission signal output terminal B. The pull-down maintaining module 105 is configured to maintain the potential of the first node QN and the potential of the nth stage transmission signal ST (N) at the potential of the second reference low level signal VSSG and maintain the potential of the nth stage scanning signal G (N) at the potential of the first reference low level signal VSSQ.

It should be noted that, in some embodiments of the present application, as shown in fig. 1, the control signal accessed by the pull-down maintaining module 105 is the present-stage clock signal CK (N). In still other embodiments of the present application, as shown in fig. 2, the control signals accessed by the pull-down maintenance module 105 include a first low frequency clock signal LC1 and a second low frequency clock signal LC2. The following embodiments of the present application will be described in detail and are not described in detail herein.

One end of the bootstrap capacitor Cbt1 is electrically connected to the first node QN. The other end of the bootstrap capacitor Cbt1 is electrically connected to the nth stage scan signal output terminal C.

Therefore, in the application, by adding the pre-boosting module 102 in the nth stage GOA unit 100, the bootstrap effect of the pre-boosting module 102 is utilized to increase the potential of the first node QN, so that the opening degree of the transistor in the pull-up module 103 can be increased. Under the condition of ensuring a larger threshold voltage deviation range of the GOA circuit, the driving voltage can be reduced, and further the power consumption is reduced.

Further, the GOA circuit receives K clock signals. The K clock signals are active in successive cycles of the GOA circuit. That is, in the GOA circuit, every K GOA units is one hierarchical cycle. Every K GOA units are connected with K clock signals in a one-to-one correspondence mode. In the present application, the clock signal CK (N-N) is the clock signal accessed by the N-N-th GOA unit. Wherein, K is more than or equal to 4,1/2K is more than or equal to m is more than or equal to n is more than or equal to 1, and K, m and n are integers. Wherein the clock signal is a high frequency clock signal.

In the GOA circuit, for the first m stages of GOA units, N is less than or equal to m, and then the N-m stages of the transmission signals ST (N-m) are not present. Thus, in the first m-stage GOA unit, a start signal may be set instead of the nth-m-stage pass signal ST (N-m). Similarly, for an N-N th GOA unit, when N.ltoreq.n, the clock signal CK (N-N) is absent. In this case, a further signal replacement may also be provided, which is not described in detail here.

It is understood that the GOA circuit includes at least two clock signals CK. For example, the GOA circuit includes 2 clock signals CK1-CK2; the GOA circuit comprises 4 clock signals CK1-CK4; the GOA circuit comprises 8 clock signals CK1-CK8; the GOA circuit includes 12 clock signals CK1-CK12. Of course, the application is not limited to the examples described above. In the application, the GOA circuit at least comprises 4 high-frequency clock signals, so that an equation that 1/2K is more than or equal to m is more than or equal to N is more than or equal to 1 is established, and further normal cascade transmission of each GOA unit is ensured, so that the pre-boosting module 102 normally works under the control of the N-m-th level transmission signal ST (N-m) and the clock signal CK (N-N), and the bootstrap effect on the first node QN is realized.

The following embodiments of the present application will be described by taking the GOA circuit with 6 clock signals CK1-CK6 as an example. Specifically, referring to fig. 3 and 4, fig. 3 is a timing chart of clock signals provided by the present application.

Fig. 4 is a schematic plan view of a GOA circuit according to the present application. Wherein the waveforms of the signals of the clock signals CK1-CK6 are all the same, and the timings are different. Due to the arrangement of the clock signals CK1-CK6, every 6 GOA units in the GOA circuit are in a cascade cycle. That is, each GOA unit is correspondingly connected with a clock signal.

Further, when 6 clock signals CK1-CK6 are provided in the GOA circuit, k=6. Then 3.gtoreq.m.gtoreq.n.gtoreq.1. At this time, when m=3, n=3; or when m=3, n=2; further, when m=3 and n=1, or when m=2, n=1 and the like are also satisfied. The following examples of the present application are given by way of example only, with k=6, m=3, n=1, but are not to be construed as limiting the application.

The transistors used in the present application may include a P-type transistor that is turned on when the gate is at a low level, turned off when the gate is at a high level, and/or an N-type transistor that is turned on when the gate is at a high level, and turned off when the gate is at a low level. The transistors in the following embodiments of the present application are described by taking N-type transistors as examples, but the present application is not limited thereto.

Referring to fig. 5, fig. 5 is a circuit schematic of the nth stage GOA unit shown in fig. 1. Wherein the pull-up module 103 includes a first transistor T1. The gate of the first transistor T1 and the source of the first transistor T1 are both connected to the N-3 rd level transmission signal ST (N-3). The drain of the first transistor T1 is electrically connected to the first node QN.

Wherein the pre-boost module 102 includes a second transistor T2 and a capacitor Cbt2. The gate of the second transistor T2 is connected to the N-3 rd stage pass signal ST (N-3). The source of the second transistor T2 is connected to the N-1 stage clock signal CK (N-1). The drain of the second transistor T2 and one end of the capacitor Cbt2 are electrically connected to the second node a. The other end of the capacitor Cbt2 is electrically connected to the first node QN.

The pull-up module 103 includes a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 and the gate of the fourth transistor T4 are electrically connected to the first node QN. The source of the third transistor T3 and the source of the fourth transistor T4 are both connected to the present stage clock signal CK (N). The drain of the third transistor T3 is electrically connected to the N-th stage signal output terminal B. The drain of the fourth transistor T4 is electrically connected to the nth stage scan signal output terminal C.

The pull-down module 104 includes a fifth transistor T5 and a sixth transistor T6. The gates of the fifth transistor T5 and the sixth transistor T6 are connected to the n+3-th level transmission signal ST (n+3). The source of the fifth transistor T5 is connected to the first reference low level signal VSSQ. The drain of the fifth transistor T5 is electrically connected to the first node QN. The source of the sixth transistor T6 is connected to the second reference low level signal VSSG. The drain of the sixth transistor T6 is electrically connected to the nth stage scan signal output terminal C.

The pull-down maintaining module 105 includes a first pull-down maintaining unit 1051. The first pull-down maintaining unit 1051 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.

The gates of the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are electrically connected to the third node P1. The source of the seventh transistor T7, the source of the eighth transistor T8, the source of the ninth transistor T9, the source of the twelfth transistor T12, and the source of the thirteenth transistor T13 are all connected to the first reference low level signal VSSQ. The drain of the seventh transistor T7 is electrically connected to the second node a. The drain of the eighth transistor T8 is electrically connected to the first node QN. The drain of the ninth transistor T9 is electrically connected to the nth stage signal output terminal ST (N). The source of the tenth transistor T10 is connected to the second reference low level signal VSSG. The drain of the tenth transistor T10 is electrically connected to the nth stage scan signal output terminal C. The gate of the eleventh transistor T11 and the source of the eleventh transistor T11 are both connected to the control signal. The gate of the twelfth transistor T12 is electrically connected to the first node QN. The gate of the thirteen transistor T13 is connected to the N-3 rd stage pass signal ST (N-3).

In the present application, the control signal for the gate of the eleventh transistor T11 and the source of the eleventh transistor T11 is the present-stage clock signal CK (N).

Further, the first pull-down maintaining unit 1051 further includes a fourteenth transistor T14.

Specifically, the gate of the fourteenth transistor T14 is connected to the complementary clock signal XCK. The source of the fourteenth transistor T14 is connected to the first reference low level signal VSSQ. The drain of the fourteenth transistor T14 is electrically connected to the third node P1.

Wherein the potential of the complementary clock signal XCK is kept inverted from the potential of the present stage clock signal CK (N). That is, when the potential of the present-stage clock signal CK (N) is high, the potential of the complementary clock signal XCK is low. When the potential of the present stage clock signal CK (N) is low, the potential of the complementary clock signal XCK is high. The fourteenth transistor T14 is configured to periodically pull the potential of the third node P1 low under the control of the complementary clock signal XCK and the first reference low-level signal VSSQ, so as to avoid the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 from operating in the PBTS (Positive Bias Temperature Stress ) state for a long time, which causes a positive drift of the threshold voltage of the thin film transistor, and affects the pull-down maintenance capability, thereby avoiding the GOA circuit from being disabled and further prolonging the service life of the GOA circuit.

Further, the nth stage GOA unit 100 further includes a first reset module 106. The first Reset module 106 is connected to the Reset signal Reset, the first reference low level signal VSSQ, and the second reference low level signal VSSG, and is electrically connected to the first node QN, the nth stage scan signal output terminal C, and the nth stage signal output terminal B. The first Reset module 106 is configured to Reset the potential of the first node QN, the potential of the nth stage scan signal G (N), and the potential of the nth stage transfer signal ST (N) under the control of the Reset signal Reset, the first reference low level signal VSSQ, and the second reference low level signal VSSG.

The first reset module 106 includes a thirty-first transistor T31, a thirty-second transistor T32, and a thirty-third transistor T33. The gate of the thirty-first transistor T31, the gate of the thirty-third transistor T32, and the gate of the thirty-third transistor T33 are all connected to the Reset signal Reset. The source of the thirty-first transistor T31 and the source of the thirty-first transistor T32 are both connected to the first reference low level signal VSSQ. The drain of the thirty-first transistor T31 is electrically connected to the first node QN. The drain of the thirty-second transistor T32 is electrically connected to the drain. The nth stage signals output terminal B. The source of the thirty-third transistor T33 is connected to the second reference low level signal VSSG. The drain of the thirty-third transistor T33 is electrically connected to the nth stage scan signal output terminal C.

Specifically, the nth stage GOA unit 100 shown in fig. 4 includes the following operations:

first, before a frame starts, the Reset signal Reset will be set high, and the thirty-first transistor T31, the thirty-second transistor T32, and the thirty-third transistor T33 are turned on. So that the potential of the first node QN and the potential of the nth stage transfer signal ST (N) are the same as the initial potential of the first reference low level VSSQ, and the initial potential of the nth stage scan signal G (N) is the same as the potential of the second reference low level signal VSSG. After that, the Reset signal Reset is shifted from the high level to the low level, so that the thirty-first transistor T31, the thirty-second transistor T32, and the thirty-third transistor T33, the nth stage GOA unit 100 waits for the next time.

Therefore, the first reset module 106 can reset the potentials of the first node QN, the nth stage scan signal G (N), and the nth stage transfer signal ST (N) before starting a frame, so as to avoid abnormal display caused by charge residues and further improve the stability of the GOA circuit.

Then, when the N-3 rd stage pass signal ST (N-3) rises to a high potential, the first transistor T1 is turned on. The potential of the first node Q (N) is pulled up to the potential of the N-3 rd level transmission signal ST (N-3). At the same time, the second transistor T2 is turned on. In the latter half region where the N-3 rd stage transfer signal ST (N-3) is at a high level, the N-1 ST stage clock signal CK (N-1) rises from a low level to a high level. The potential of the first node QN is further pulled up by the bootstrap effect of the capacitor Cbt 2. Since the potential of the first node QN is high, the third transistor T3 and the fourth transistor T4 are turned on. Further, the present stage clock signal CK (N) transitions from a low potential to a high potential, thereby outputting the present stage transfer signal ST (N) at the present stage transfer signal output terminal B through the third transistor T3, and outputting the nth stage scan signal G (N) at the nth stage scan signal output terminal C through the fourth transistor T4.

At this time, since the potential of the first node QN is high, the twelfth transistor T12 is turned on. Since the N-3 rd stage pass signal ST (N-3) is at a high potential, the thirteenth transistor T13 is turned on. Therefore, the potential of the third node P1 is low, and the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned off. Even when the clock signal CK (N) of the present stage is changed from low to high, the potential of the third node P1 remains low while the eleventh transistor T11 is turned on.

Thus, since the potential of the first node QN is further raised by the pre-boost module 102, the third transistor T3 and the fourth transistor T4 can be rapidly and sufficiently turned on, thereby reducing the rising time and falling time of the nth stage scan signal G (N) output by the nth stage GOA unit 100 and improving the charging capability of the display panel. And further, the GOA circuit is ensured to normally work in a larger threshold deviation range, and the power consumption of the GOA circuit is reduced.

Next, the n+3-th stage transfer signal ST (n+3) rises to a high potential, and the fifth transistor T5 and the sixth transistor T6 are turned on. The first node QN communicates with the first reference low level signal VSSQ, and the nth stage scan signal output terminal C communicates with the second reference low level VSSG. That is, the potential of the first node Q (N) is pulled down to the potential of the first reference low level signal VSSQ, and the potential of the nth stage scan signal G (N) is pulled down to the potential of the second reference low level VSSG. At this time, since the potential of the first node QN is pulled down to the potential of the first reference low level signal VSSQ, the tenth transistor T10 and the eleventh transistor T11 are turned off.

Thus, the pull-down module 104 can directly pull down the potential of the nth stage scan signal G (N), thereby reducing the falling time of the nth stage scan signal G (N).

Finally, the clock signal CK (N) of the present stage rises to a high level, and the complementary clock signal XCK is low. And, the potential of the first node QN and the N-3 rd level transmission signal are both low. Thus, the eleventh transistor T11 is turned on. The twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are all turned off. The potential of the third node P1 rises. Thus, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned on. Thereby maintaining the potential of the first node QN and the potential of the nth stage transmission signal ST (N) at the potential of the second reference low level signal VSSG and the potential of the nth stage scanning signal G (N) at the potential of the first reference low level signal VSSQ.

In the present application, the voltage of the first reference low level signal VSSQ is smaller than the voltage of the second reference low level signal VSSG. Then when the potential of the first node QN is maintained at the potential of the first reference low level signal VSSQ and the potential of the nth stage scan signal G (N) is maintained at the potential of the second reference low level signal VSSG. The gate-source voltage of the fourth transistor T4 is equal to a difference between the first reference low level signal VSSQ and the second reference low level signal VSSG. Since the voltage of the first reference low level signal VSSQ is less than the voltage of the second reference low level signal VSSG, the gate-source voltage of the fourth transistor T4 is less than 0, and the fourth transistor T4 may be completely turned off, thereby avoiding leakage of the fourth transistor T4.

Further, referring to fig. 6 and 7, fig. 6 is a timing chart of a partial scan signal outputted from an nth stage GOA unit according to the present application. FIG. 7 is a schematic diagram showing the relationship between the driving voltage and the threshold bias voltage according to the present application.

As can be seen from FIG. 6, the rise time and fall time of the scan signals G1-G6 outputted from the GOA circuit provided by the present application are small. Thereby, the scanning line corresponding to each stage GOA is fully charged. Fig. 5 shows only a part of the scan signal of the GOA circuit, and is not to be construed as limiting the present application.

In fig. 7, the abscissa is the driving Voltage (VGH) in volts (V) required for the GOA circuit to operate. The ordinate is the threshold bias voltage of the thin film transistor (fourth transistor T4) in volts. Wherein, the curve L1 represents the relationship between the driving voltage and the threshold bias voltage when the capacitance value of Cbt2 is 10pF (nano-meter). The curve L1 represents the relationship between the driving voltage and the threshold bias voltage when the capacitance of Cbt2 is 0pF, i.e. when the pre-boost module 102 is not provided in the GOA circuit.

Specifically, the curves L1 and L2 are obtained by performing an electrical simulation test on the ingan tft under the conditions of the driving voltage vgh=28v, the first reference low level signal vssq= -14V, and the second reference low level signal vssg= -10V.

As can be seen from fig. 7, for the GOA circuit without the pre-boost module 102, the driving voltage needs to be set to 28V in order to allow the thin film transistor to normally operate at the threshold bias of 12V in the forward direction. Whereas for GOA circuits containing pre-boost module 102 (Cbt 2 set to 10 pF), the drive voltage need only be set to 19V if a threshold bias of 12V in the forward direction is to be obtained. Therefore, the GOA circuit of the present application can effectively reduce the driving voltage while maintaining the same threshold bias. That is, the GOA of the present application can ensure that the GOA circuit works normally within a larger threshold deviation range under the same driving voltage.

Referring to fig. 8, fig. 8 is a circuit schematic of the nth stage GOA unit shown in fig. 2. The difference from the nth stage GOA unit 100 shown in fig. 2 is at least that in the nth stage GOA unit 100 provided in this embodiment, the pull-down maintaining module 105 further includes a second pull-down maintaining unit 1052.

Wherein the control signal includes a first low frequency clock signal LC1 and a second low frequency clock signal LC2. The fourteenth transistor T14 is not provided in the first pull-down maintaining unit 1051. The gate of the eleventh transistor T11 and the source of the eleventh transistor T11 are both connected to the first low frequency clock signal LC1.

The second pull-down maintaining unit 1052 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, and a twenty first transistor T21.

Specifically, the gate of the fifteenth transistor T15, the gate of the sixteenth transistor T16, the gate of the seventeenth transistor T17, the gate of the eighteenth transistor T18, the drain of the nineteenth transistor, the drain of the twentieth transistor T20 and the drain of the twenty first transistor T21 are electrically connected to the third node P1. The source of the fifteenth transistor T15, the source of the sixteenth transistor T16, the source of the seventeenth transistor T17, the source of the twentieth transistor T20, and the source of the twenty-first transistor T21 are all connected to the first reference low level signal VSSQ. The drain of the fifteenth transistor T15 is electrically connected to the second node a. The drain of the sixteenth transistor T16 is electrically connected to the first node QN. The drain of the seventeenth transistor T17 is electrically connected to the nth stage signal output terminal B. The source of the eighteenth transistor T18 is connected to the second reference low level signal VSSG. The drain of the eighteenth transistor T18 is electrically connected to the nth stage scan signal output terminal C. The gate of the nineteenth transistor T19 and the source of the nineteenth transistor T19 are both connected to the second low frequency clock signal LC2. The gate of the twentieth transistor T20 is electrically connected to the first node QN. The gate of the twenty-first transistor T21 is connected to the N-3 rd stage pass signal ST (N-3).

It is understood that the first pull-down maintaining unit 1051 and the second pull-down maintaining unit 1052 are symmetrically arranged for maintaining the low potential of the first node QN, the nth stage pass signal ST (N) and the nth stage scan signal G (N). This arrangement improves the uniformity of the GOA circuit, and thus improves the stability of the GOA circuit.

Note that the first pull-down holding unit 1051 and the second pull-down holding unit 1052 may operate simultaneously. Of course, the durability of the GOA circuit may be improved by controlling the first low frequency clock signal LC1 and the second low frequency clock signal LC2 such that the first pull-down holding unit 1051 and the second pull-down holding unit 1052 alternately operate.

Further, the nth stage GOA unit 100 also includes a second reset module 106'. The second Reset module 106' is connected to the Reset signal Reset and the first reference low level signal VSSQ, and is electrically connected to the first node QN. The second Reset module 106' is configured to Reset the potential of the first node QN under control of the Reset signal Reset.

In some embodiments, the second reset module 106' includes a thirty-first transistor T31. The gate of the thirty-first transistor T31 is connected to the Reset signal Reset. The source of the thirty-first transistor T31 is connected to the first reference low level signal VSSQ. The drain of the thirty-first transistor T31 is electrically connected to the first node QN.

It should be noted that the clock signal timing chart shown in fig. 3 and the partial scan signal timing chart shown in fig. 5 are also applicable to the nth stage GOA unit 100 of the present embodiment. The operation of the nth stage GOA unit 100 according to this embodiment may refer to the operation of the nth stage GOA unit 100 according to the above embodiment. The difference is that, in the present embodiment, the second reset module 106' includes only the thirty-first transistor T31 compared to the first reset module 106, so as to pull down the potential of the first node GN. Further, the potentials of the first low frequency clock signal LC1 and the second low frequency clock signal LC2 may remain inverted, so that the first pull-down maintaining unit 1051 and the second pull-down maintaining unit 1052 alternately operate.

The GOA circuit provided by the application can be applied to large, medium and small-sized panels. The transistors in the GOA circuit may be low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors. In addition, the transistors in the GOA circuit provided by the embodiment of the application are of the same type, so that the influence of the difference between the transistors of different types on the pixel driving circuit is avoided, and the process is simplified.

Correspondingly, the application further provides a display panel, which comprises the GOA circuit. Referring to fig. 9, fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the application. As shown in fig. 9, the display panel 1000 includes a display area AA and a GOA circuit 300 integrally disposed on an edge of the display area AA. The GOA circuit 300 is similar to the GOA circuit described above in terms of structure and principle, and will not be described herein. It should be noted that, the display panel 1000 provided in the present application is described by taking a one-side driving mode in which the GOA circuit 300 is disposed on the display area AA side as an example, but the present application is not limited thereto. In some embodiments, a dual-side driving or other driving modes may be adopted according to the actual requirements of the display panel 1000, which is specifically limited by the present application.

The application provides a display panel 1000. The display panel 1000 includes a GOA circuit 300.GOA circuit 300 includes multiple stages of cascaded GOA cells. The N-th GOA unit comprises a pull-up control module, a pre-boosting module, a pull-up module, a pull-down maintenance module and a bootstrap capacitor, wherein N is an integer larger than 0. According to the application, the pre-boosting module is additionally arranged in the GOA unit, the bootstrap effect of the pre-boosting module is utilized to improve the potential of the first node, and the starting degree of the transistor in the pull-up module 103 is improved, so that the effect that the driving voltage is reduced and the GOA circuit 300 can still normally work within a larger threshold voltage deviation range is achieved, and the normal display of the display panel 1000 is ensured.

The foregoing has outlined rather broadly the principles and embodiments of the present application in order that the detailed description of the application may be better understood, and in order that the present application may be better understood; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A GOA circuit comprising a multistage cascade of GOA cells, an nth stage GOA cell comprising: the device comprises a pull-up control module, a pre-boosting module, a pull-up module, a pull-down maintenance module and a bootstrap capacitor;

the pull-up control module is connected with the N-m-th level transmission signal and is electrically connected with the first node, and is used for outputting the N-m-th level transmission signal to the first node under the control of the N-m-th level transmission signal; n and m are integers greater than 0, and N > m;

2. The GOA circuit of claim 1, wherein the GOA circuit receives K clock signals that are valid in successive cycles of operation of the GOA circuit;

the clock signal is the clock signal accessed by the N-N-th GOA unit, wherein N > K is more than or equal to 4,1/2K is more than or equal to m is more than or equal to 1, K, m and N are integers.

3. The GOA circuit of claim 1, wherein the pull-down module comprises a fifth transistor and a sixth transistor;

4. The GOA circuit of claim 1, wherein the pull-down maintenance module comprises a first pull-down maintenance unit comprising a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

5. The GOA circuit of claim 4, wherein the control signal is the nth stage clock signal, the first pull-down maintenance unit further comprising a fourteenth transistor;

6. The GOA circuit of claim 4, wherein the nth stage GOA unit further comprises a first reset module;

7. The GOA circuit of claim 6, wherein the first reset module comprises a thirty-first transistor, a thirty-second transistor, and a thirty-third transistor;

8. The GOA circuit of claim 4, wherein the pull-down maintenance module further comprises a second pull-down maintenance unit, the control signal comprising a first low frequency clock signal and a second low frequency clock signal, the gate of the eleventh transistor and the source of the eleventh transistor both being tied to the first low frequency clock signal;

the grid electrode of the fifteenth transistor, the grid electrode of the sixteenth transistor, the grid electrode of the seventeenth transistor, the grid electrode of the eighteenth transistor, the drain electrode of the nineteenth transistor, the drain electrode of the twentieth transistor and the drain electrode of the twenty first transistor are all electrically connected to a third node, the source electrode of the fifteenth transistor, the source electrode of the sixteenth transistor, the source electrode of the seventeenth transistor, the source electrode of the twenty first transistor and the source electrode of the twenty first transistor are all connected to the first reference low level signal, the drain electrode of the fifteenth transistor is electrically connected to the second node, the drain electrode of the sixteenth transistor is electrically connected to the first node, the drain electrode of the seventeenth transistor is electrically connected to the N-th stage transmission signal output end, the source electrode of the eighteenth transistor is connected to the second reference low level signal, the drain electrode of the eighteenth transistor is electrically connected to the N-th stage scanning signal output end, the grid electrode of the nineteenth transistor and the nineteenth transistor are all electrically connected to the N-th node, and the drain electrode of the nineteenth transistor is electrically connected to the N-th stage transmission signal.

9. The GOA circuit of claim 8, wherein the nth stage GOA unit further comprises a second reset module;