CN106898287B

CN106898287B - Shift register, driving method thereof and grid driving circuit

Info

Publication number: CN106898287B
Application number: CN201710192071.XA
Authority: CN
Inventors: 冯思林
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2017-03-28
Filing date: 2017-03-28
Publication date: 2020-12-01
Anticipated expiration: 2037-03-28
Also published as: CN106898287A; US20180286302A1

Abstract

The invention provides a shift register, a driving method thereof and a grid driving circuit, belongs to the technical field of grid driving circuits, and can at least partially solve the problem that the conventional bidirectional scanning shift register is easy to generate output abnormity. The shift register of the present invention includes: an input unit for introducing a signal of the first signal terminal into a pull-up node under the control of the input terminal; a reset unit for introducing a signal of the second signal terminal into the pull-up node under the control of the reset terminal; an output unit for introducing a signal of the first clock terminal into an output terminal according to a level of the pull-up node; a pull-down unit for introducing a signal of a fixed level terminal to the pull-up node and the output terminal according to a level of the pull-down node, and for introducing the signal of the fixed level terminal to the pull-up node and the output terminal under control of a third signal terminal; a pull-down control unit for controlling a level of the pull-down node according to a signal of the second clock terminal and a level of the pull-up node; a storage capacitor.

Description

Shift register, driving method thereof and grid driving circuit

Technical Field

The invention belongs to the technical field of grid driving circuits, and particularly relates to a shift register, a driving method thereof and a grid driving circuit.

Background

To simplify the structure of the display panel, the gate lines may be driven using a gate driver circuit (GOA) formed on the array substrate. The grid driving circuit comprises a plurality of cascaded shift registers, each shift register drives one grid line, and when one shift register outputs a conducting signal, the work of other shift registers can be triggered, so that the driving of all the grid lines can be realized by only using a plurality of simple control signals.

In many cases, it is desirable that the display panel can perform bidirectional scanning, that is, each gate line is required to be alternately turned on from top to bottom and from bottom to top. As shown in fig. 5, in order to realize bidirectional scanning, it is necessary to provide a first signal terminal FW and a second signal terminal BW, one of the two signal terminals is continuously at a high level, the other is continuously at a low level, and when ports at the high level are different, the scanning direction is also different.

Meanwhile, in a frame, the scanning of all the gate lines can be completed only in a part of Time, the remaining Time is a Blank Time, and signals of other ports except for the first signal terminal FW and the second signal terminal BW in the Blank Time are all kept at a low level. In the idle stage, one of the first signal terminal FW and the second signal terminal BW is continuously at a high level, and a certain leakage current inevitably exists in the transistor, so that in this stage, the storage capacitor C gradually generates charge accumulation, the level of the pull-up node PU of the shift register gradually rises, and the transistor for correspondingly controlling the output is in an unsaturated state, so that when a next frame of picture (i.e., when each shift register restarts to work), the shift register (especially the last stage of shift register) is easy to generate output abnormality, which affects the display quality.

Disclosure of Invention

The invention at least partially solves the problem that the conventional bidirectional scanning shift register is easy to generate output abnormity, and provides the shift register, the driving method thereof and the grid driving circuit, which can realize bidirectional scanning and avoid output abnormity.

The technical scheme adopted for solving the technical problem of the invention is a shift register, which comprises:

the input unit is connected with the input end, the first signal end and the pull-up node and is used for introducing a signal of the first signal end into the pull-up node under the control of the input end;

the reset unit is connected with the reset terminal, the second signal terminal and the pull-up node and is used for introducing a signal of the second signal terminal into the pull-up node under the control of the reset terminal;

the output unit is connected with the output end, the first clock end and the pull-up node and is used for introducing a signal of the first clock end into the output end according to the level of the pull-up node;

the pull-down unit is connected with the third signal end, the second clock end, the fixed level end, the output end, the pull-up node and the pull-down node, is used for introducing the signal of the fixed level end into the pull-up node and the output end according to the level of the pull-down node, and is used for introducing the signal of the fixed level end into the pull-up node and the output end under the control of the third signal end;

the pull-down control unit is connected with the second clock end, the pull-up node, the pull-down node and the constant level end and is used for controlling the level of the pull-down node according to the signal of the second clock end and the level of the pull-up node;

and the first pole of the storage capacitor is connected with the pull-down node, and the second pole of the storage capacitor is connected with the pull-down node.

Preferably, the input unit includes a first transistor, wherein,

the grid electrode of the first transistor is connected with the input end, the first pole of the first transistor is connected with the first signal end, and the second pole of the first transistor is connected with the upper pull node.

It is further preferred that the reset unit includes a second transistor, wherein,

the grid electrode of the second transistor is connected with the reset end, the first pole is connected with the upper pull node, and the second pole is connected with the second signal end.

It is further preferred that the output unit comprises a third transistor, wherein,

the grid electrode of the third transistor is connected with the upper pull node, the first pole is connected with the first clock end, and the second pole is connected with the output end.

It is further preferable that the pull-down unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, wherein,

the grid electrode of the fourth transistor is connected with the second clock end, the first pole of the fourth transistor is connected with the output end, and the second pole of the fourth transistor is connected with the fixed-level end;

the grid electrode of the fifth transistor is connected with the pull-down node, the first pole of the fifth transistor is connected with the pull-up node, and the second pole of the fifth transistor is connected with the constant-level end;

the grid electrode of the sixth transistor is connected with the pull-down node, the first pole of the sixth transistor is connected with the output end, and the second pole of the sixth transistor is connected with the fixed-level end;

the grid electrode of the seventh transistor is connected with a third signal end, the first electrode of the seventh transistor is connected with a pull-up node, and the second electrode of the seventh transistor is connected with a fixed-level end;

a grid electrode of the eighth transistor is connected with a third signal end, a first pole of the eighth transistor is connected with a pull-down node, and a second pole of the eighth transistor is connected with a third signal end;

and the grid electrode of the ninth transistor is connected with the third signal end, the first pole of the ninth transistor is connected with the output end, and the second pole of the ninth transistor is connected with the fixed-level end.

It is further preferable that the pull-down control unit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, wherein,

the grid electrode of the tenth transistor is connected with the second pole of the thirteenth transistor, the first pole of the tenth transistor is connected with the second clock end, and the second pole of the tenth transistor is connected with the pull-down node;

a grid electrode of the eleventh transistor is connected with a pull-up node, a first pole of the eleventh transistor is connected with the pull-down node, and a second pole of the eleventh transistor is connected with a constant-level end;

the grid electrode of the twelfth transistor is connected with the upper pull node, the first pole of the twelfth transistor is connected with the second pole of the thirteenth transistor, and the second pole of the twelfth transistor is connected with the fixed-level end;

and the grid electrode of the thirteenth transistor is connected with the second clock terminal, and the first electrode of the thirteenth transistor is connected with the second clock terminal.

It is further preferred that all transistors are N-type transistors;

alternatively, the first and second electrodes may be,

all transistors are P-type transistors.

The technical scheme adopted for solving the technical problem of the invention is a gate drive circuit, which comprises:

a plurality of cascaded shift registers.

The technical scheme adopted for solving the technical problem of the invention is a driving method of the shift register, which comprises the following steps:

an idle stage: and providing an off signal to the constant level terminal and providing an on signal to the third signal terminal to introduce the off signal of the constant level terminal to the pull-up node and the output terminal.

Further preferably, the shift register is a shift register in which all the transistors are N-type transistors, and the driving method of the shift register includes:

in the forward direction scanning, a high level is continuously input to the first signal terminal, a low level is continuously input to the second signal terminal, and a low level is continuously input to the constant level terminal, and the driving process of the shift register specifically includes:

a charging stage: inputting a high level to an input end, inputting a low level to a first clock end, inputting a high level to a second clock end, inputting a low level to a reset end, and inputting a low level to a third signal end;

an output stage: inputting a low level to the input end, inputting a high level to the first clock end, inputting a low level to the second clock end, inputting a low level to the reset end, and inputting a low level to the third signal end;

a reset stage: inputting a low level to the input end, inputting a low level to the first clock end, inputting a high level to the second clock end, inputting a high level to the reset end, and inputting a low level to the third signal end;

a maintaining stage: inputting a low level to the input end, alternately inputting a high level to the first clock end and the second clock end, inputting a low level to the reset end, and inputting a low level to the third signal end;

an idle stage: inputting a low level to the input end, inputting a low level to the first clock end, inputting a low level to the second clock end, inputting a low level to the reset end, and inputting a high level to the third signal end;

during the reverse scan, a low level is continuously input to the first signal terminal, a high level is continuously input to the second signal terminal, and a low level is continuously input to the constant level terminal, and the driving process of the shift register specifically includes:

a charging stage: inputting a high level to a reset end, inputting a low level to a first clock end, inputting a high level to a second clock end, inputting a low level to an input end, and inputting a low level to a third signal end;

an output stage: inputting a low level to a reset end, inputting a high level to a first clock end, inputting a low level to a second clock end, inputting a low level to an input end, and inputting a low level to a third signal end;

a reset stage: inputting a low level to a reset end, inputting a low level to a first clock end, inputting a high level to a second clock end, inputting a high level to an input end, and inputting a low level to a third signal end;

a maintaining stage: inputting a low level to a reset end, alternately inputting a high level to a first clock end and a second clock end, inputting a low level to an input end, and inputting a low level to a third signal end;

an idle stage: inputting a low level to a reset end, inputting a low level to a first clock end, inputting a low level to a second clock end, inputting a low level to an input end, and inputting a high level to a third signal end;

alternatively, the first and second electrodes may be,

the shift register is a shift register in which all the transistors are P-type transistors, and the driving method of the shift register comprises the following steps:

in the forward direction scanning, a low level is continuously input to the first signal terminal, a high level is continuously input to the second signal terminal, and a high level is continuously input to the constant level terminal, and the driving process of the shift register specifically includes:

a charging stage: inputting a low level to the input end, inputting a high level to the first clock end, inputting a low level to the second clock end, inputting a high level to the reset end, and inputting a high level to the third signal end;

an output stage: inputting a high level to an input end, inputting a low level to a first clock end, inputting a high level to a second clock end, inputting a high level to a reset end, and inputting a high level to a third signal end;

a reset stage: inputting a high level to an input end, inputting a high level to a first clock end, inputting a low level to a second clock end, inputting a low level to a reset end, and inputting a high level to a third signal end;

a maintaining stage: inputting a high level to an input end, alternately inputting a low level to a first clock end and a second clock end, inputting a high level to a reset end, and inputting a high level to a third signal end;

an idle stage: inputting a high level to an input end, inputting a high level to a first clock end, inputting a high level to a second clock end, inputting a high level to a reset end, and inputting a low level to a third signal end;

during the reverse scan, a high level is continuously input to the first signal terminal, a low level is continuously input to the second signal terminal, and a high level is continuously input to the constant level terminal, and the driving process of the shift register specifically includes:

a charging stage: inputting a low level to a reset end, inputting a high level to a first clock end, inputting a low level to a second clock end, inputting a high level to an input end, and inputting a high level to a third signal end;

an output stage: inputting a high level to a reset end, inputting a low level to a first clock end, inputting a high level to a second clock end, inputting a high level to an input end, and inputting a high level to a third signal end;

a reset stage: inputting a high level to a reset end, inputting a high level to a first clock end, inputting a low level to a second clock end, inputting a low level to an input end, and inputting a high level to a third signal end;

a maintaining stage: inputting a high level to a reset end, alternately inputting a low level to a first clock end and a second clock end, inputting a high level to an input end, and inputting a high level to a third signal end;

an idle stage: and inputting a high level to the reset terminal, inputting a high level to the first clock terminal, inputting a high level to the second clock terminal, inputting a high level to the input terminal, and inputting a low level to the third signal terminal.

By adjusting the signals of the first signal terminal and the second signal terminal, the shift register of the embodiment can realize both forward scanning and reverse scanning, that is, it has a bidirectional scanning function; meanwhile, in the idle stage, as long as a conducting signal is provided for the third signal end, a turn-off signal of the fixed-level end can be introduced into the output end and the pull-up node, so that the shift register can continuously and stably output low level, the level of the pull-up node is prevented from being raised due to electric leakage, and the charge accumulation of the storage capacitor is eliminated, thereby avoiding output abnormity (especially for the last stage of shift register) when the next frame starts, and ensuring the display quality.

Drawings

FIG. 1 is a circuit diagram of a shift register according to an embodiment of the present invention;

FIG. 2 is a block diagram of a gate driving circuit according to an embodiment of the present invention;

FIG. 3 is a timing diagram illustrating a forward scan of a shift register according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating a reverse scan of a shift register according to an embodiment of the present invention;

FIG. 5 is a circuit diagram of a conventional shift register;

wherein the reference numerals are: m1, a first transistor; m2, a second transistor; m3, a third transistor; m4, a fourth transistor; m5, a fifth transistor; m6, a sixth transistor; m7, a seventh transistor; m8, an eighth transistor; m9, ninth transistor; m10, tenth transistor; m11, an eleventh transistor; m12, a twelfth transistor; m13, thirteenth transistor; C. a storage capacitor; CLK, a first clock terminal; CLKB, a second clock terminal; INPUT, INPUT terminal; OUTPUT, OUTPUT terminal; RESET and a RESET end; PD, a pull-down node; PU, a pull-up node; FW, a first signal terminal; BW, a second signal terminal; a GCL and a third signal terminal; VGL, fixed level terminal; 1. an input unit; 2. a reset unit; 3. an output unit; 4. an output unit; 5. a pull-down control unit.

Detailed Description

In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Example 1:

as shown in fig. 1 to 4, the present embodiment provides a shift register, which includes:

an INPUT unit 1, connected to the INPUT terminal INPUT, the first signal terminal FW, and the pull-up node PU, for introducing a signal of the first signal terminal FW into the pull-up node PU under the control of the INPUT terminal INPUT;

the RESET unit 2 is connected with the RESET terminal RESET, the second signal terminal BW and the pull-up node PU, and is configured to introduce a signal of the second signal terminal BW into the pull-up node PU under the control of the RESET terminal RESET;

the OUTPUT unit 3 is connected with the OUTPUT end OUTPUT, the first clock end CLK and the pull-up node PU, and is used for introducing a signal of the first clock end CLK into the OUTPUT end OUTPUT according to the level of the pull-up node PU;

the pull-down unit 4 is connected with the third signal terminal GCL, the second clock terminal CLKB, the fixed level terminal VGL, the OUTPUT terminal OUTPUT, the pull-up node PU and the pull-down node PD, and is configured to introduce a signal of the fixed level terminal VGL into the pull-up node PU and the OUTPUT terminal OUTPUT according to the level of the pull-down node PD, and introduce a signal of the fixed level terminal VGL into the pull-up node PU and the OUTPUT terminal OUTPUT under the control of the third signal terminal GCL;

a pull-down control unit 5, connected to the second clock terminal CLKB, the pull-up node PU, the pull-down node PD, and the constant level terminal VGL, for controlling the level of the pull-down node PD according to the signal of the second clock terminal CLKB and the level of the pull-up node PU;

and a first pole of the storage capacitor C is connected with the pull-up node PU, and a second pole of the storage capacitor C is connected with the pull-down node PD.

Preferably, the input unit 1 comprises a first transistor M1, wherein,

the gate of the first transistor M1 is connected to the INPUT terminal INPUT, the first pole is connected to the first signal terminal FW, and the second pole is connected to the pull-up node PU.

Preferably, the reset unit 2 includes a second transistor M2, wherein,

the gate of the second transistor M2 is connected to the RESET terminal RESET, the first pole is connected to the pull-up node PU, and the second pole is connected to the second signal terminal BW.

Preferably, the output unit 3 comprises a third transistor M3, wherein,

the gate of the third transistor M3 is connected to the pull-up node PU, the first pole is connected to the first clock terminal CLK, and the second pole is connected to the OUTPUT terminal OUTPUT.

Preferably, the pull-down unit 4 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, wherein,

the gate of the fourth transistor M4 is connected to the second clock terminal CLKB, the first pole is connected to the OUTPUT terminal OUTPUT, and the second pole is connected to the constant level terminal VGL;

the gate of the fifth transistor M5 is connected to the pull-down node PD, the first pole is connected to the pull-up node PU, and the second pole is connected to the constant voltage terminal VGL;

the gate of the sixth transistor M6 is connected to the pull-down node PD, the first pole is connected to the OUTPUT terminal OUTPUT, and the second pole is connected to the constant level terminal VGL;

the gate of the seventh transistor M7 is connected to the third signal terminal GCL, the first pole is connected to the pull-up node PU, and the second pole is connected to the constant voltage terminal VGL;

a gate of the eighth transistor M8 is connected to the third signal terminal GCL, a first pole is connected to the pull-down node PD, and a second pole is connected to the third signal terminal GCL;

the gate of the ninth transistor M9 is connected to the third signal terminal GCL, the first pole is connected to the OUTPUT terminal OUTPUT, and the second pole is connected to the constant voltage terminal VGL.

Preferably, the pull-down control unit 5 includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, wherein,

a gate of the tenth transistor M10 is connected to a second pole of the thirteenth transistor M13, the first pole is connected to the second clock terminal CLKB, and the second pole is connected to the pull-down node PD;

the gate of the eleventh transistor M11 is connected to the pull-up node PU, the first pole is connected to the pull-down node PD, and the second pole is connected to the constant voltage terminal VGL;

the gate of the twelfth transistor M12 is connected to the pull-up node PU, the first pole is connected to the second pole of the thirteenth transistor M13, and the second pole is connected to the constant voltage terminal VGL;

the gate of the thirteenth transistor M13 is connected to the second clock terminal CLKB, and the first pole is connected to the second clock terminal CLKB.

More preferably, all transistors are N-type transistors; alternatively, all transistors are P-type transistors.

That is, all the transistors (the first transistor M1 to the thirteenth transistor M13) in the above shift register are preferably of the same type.

By adjusting the signals of the first signal terminal FW and the second signal terminal BW, the shift register of the embodiment can implement both forward scanning and reverse scanning, that is, it has a bidirectional scanning function; meanwhile, in the Blank Time period, as long as a conducting signal is provided to the third signal terminal GCL, a turn-off signal of the constant level terminal VGL can be introduced into the OUTPUT terminal OUTPUT and the pull-up node PU, so that the shift register continuously and stably OUTPUTs a low level, the pull-up node PU is prevented from being raised in level due to electric leakage, and the charge accumulation of the storage capacitor C is eliminated, thereby avoiding OUTPUT abnormality (especially for the last stage of shift register) at the beginning of a next frame picture and ensuring the display quality.

The present embodiment further provides a gate driving circuit, which includes:

a plurality of cascaded shift registers.

As shown in fig. 2, a plurality of shift registers may be cascaded to form a gate driving circuit, where the OUTPUT terminal OUTPUT of each shift register is connected to a gate line for driving the gate line.

Specifically, except for the last stage of shift register, the OUTPUT terminal OUTPUT of each shift register is also connected to the INPUT terminal INPUT of the next stage of shift register, and certainly, the INPUT terminal INPUT of the first stage of shift register needs to be connected with a separate driving signal; meanwhile, besides the first-stage shift register, the OUTPUT terminal OUTPUT of each shift register is also connected to the RESET terminal RESET of the first-stage shift register, and of course, the RESET terminal RESET of the last-stage shift register is connected to a separate driving signal.

Meanwhile, for any two adjacent shift registers, their clock terminals are connected to opposite clock signal lines, that is, if the first clock terminal CLK of one shift register stage is connected to the first clock signal line and the second clock terminal CLKB is connected to the second clock signal line, the shift register of the other shift register stage must have the first clock terminal CLK connected to the second clock signal line and the second clock terminal CLKB connected to the first clock signal line.

The present embodiment further provides a driving method of the shift register, including:

an idle stage: a turn-off signal is provided to the constant level terminal VGL, and a turn-on signal is provided to the third signal terminal GCL to introduce the turn-off signal of the constant level terminal VGL to the pull-up node PU and the OUTPUT terminal OUTPUT.

In the shift register of this embodiment, in the Blank Time period (Blank Time), the third signal terminal GCL provides a turn-on signal, so that the turn-off signal of the constant level terminal VGL is introduced into the OUTPUT terminal OUTPUT and the pull-up node PU, so that the shift register can continuously and stably OUTPUT a low level, and prevent the pull-up node PU from increasing in level due to leakage, eliminate charge accumulation of the storage capacitor C, thereby avoiding OUTPUT abnormality (especially for the last stage of shift register) at the start of a next frame picture, and ensuring display quality.

The following description will specifically describe the operation process of the shift register, in which all transistors are N-type transistors, and since the shift register can implement bidirectional scanning, the following description will respectively describe the processes of forward scanning and reverse scanning.

(a) As shown in fig. 3, during the forward direction scan (i.e., scan from the low-level shift register to the high-level shift register), a high level is continuously input to the first signal terminal FW, a low level is continuously input to the second signal terminal BW, and a low level is continuously input to the constant level terminal VGL, and the driving process of the shift register specifically includes:

s11, charging stage: a high level is INPUT to the INPUT terminal INPUT, a low level is INPUT to the first clock terminal CLK, a high level is INPUT to the second clock terminal CLKB, a low level is INPUT to the RESET terminal RESET, and a low level is INPUT to the third signal terminal GCL.

In this stage, the INPUT terminal INPUT is at a high level (a conducting signal OUTPUT from the shift register of the previous stage), the first transistor M1 is turned on, the high level of the first signal terminal FW is introduced into the pull-up node PU, and the third transistor M3 is turned on, the low level of the first clock terminal CLK is introduced into the OUTPUT terminal OUTPUT, so that the shift register OUTPUTs a low level, and the storage capacitor C is charged.

Meanwhile, since the pull-up node PU is at a high level, the eleventh transistor M11 and the twelfth transistor M12 are turned on, so that the thirteenth transistor M13 and the tenth transistor M10 are turned off (although the second clock terminal CLKB is at a high level), and the pull-down node PD is at a low level.

S12, output stage: a low level is INPUT to the INPUT terminal INPUT, a high level is INPUT to the first clock terminal CLK, a low level is INPUT to the second clock terminal CLKB, a low level is INPUT to the RESET terminal RESET, and a low level is INPUT to the third signal terminal GCL.

In this stage, the INPUT terminal INPUT is changed to a low level, so the first transistor M1 is turned off, the pull-up node PU cannot discharge and keeps a high level, the third transistor M3 keeps on, and the high level of the first clock terminal CLK is introduced to the OUTPUT terminal OUTPUT, so that the shift register OUTPUTs a high level on signal.

At the same time, the level of the pull-up node PU rises further (but still high) due to the bootstrap effect of the storage capacitor C.

S13, resetting: a low level is INPUT to the INPUT terminal INPUT, a low level is INPUT to the first clock terminal CLK, a high level is INPUT to the second clock terminal CLKB, a high level is INPUT to the RESET terminal RESET, and a low level is INPUT to the third signal terminal GCL.

In this stage, the RESET terminal RESET becomes a high level (a conduction signal output from the next stage of shift register), so that the second transistor M2 is turned on, a low level of the second signal terminal BW is introduced into the pull-up node PU, and the pull-up node PU becomes a low level; since the second clock terminal CLKB is also at the high level, the fourth transistor M4 is turned on, the low level of the constant level terminal VGL is introduced into the OUTPUT terminal OUTPUT, the shift register OUTPUTs the low level, and the storage capacitor C is discharged.

Meanwhile, since the pull-up node PU becomes low level, the eleventh transistor M11 and the twelfth transistor M12 are turned off, so the high level of the second clock terminal CLKB can turn on the tenth transistor M10 and the thirteenth transistor M13, the high level of the second clock terminal CLKB enters the pull-down node PD through the thirteenth transistor M13, the pull-down node PD is high level, and the low level of the constant level terminal VGL is respectively introduced into the pull-up node PU and the OUTPUT terminal OUTPUT through the fifth transistor M5 and the sixth transistor M6, thereby further ensuring the storage capacitor C to be completely discharged.

S14, keeping stage: a low level is INPUT to the INPUT terminal INPUT, a high level is alternately INPUT to the first clock terminal CLK and the second clock terminal CLKB, a low level is INPUT to the RESET terminal RESET, and a low level is INPUT to the third signal terminal GCL.

In this stage, the shift register of the current stage has completed scanning or is waiting for scanning, and the shift registers of other stages are scanning, so that the clock signal is still asserted, and the first clock terminal CLK and the second clock terminal CLKB are alternately high. When the second clock terminal CLKB is at a high level, the pull-down node PD is at a high level, and a low level of the constant level terminal VGL is introduced into the OUTPUT terminal OUTPUT and the pull-up node PU; since the time interval of the high level of the second clock terminal CLKB is short, the OUTPUT terminal OUTPUT approximately keeps outputting the low level.

S15, Blank phase (Blank Time): a low level is INPUT to the INPUT terminal INPUT, a low level is INPUT to the first clock terminal CLK, a low level is INPUT to the second clock terminal CLKB, a low level is INPUT to the RESET terminal RESET, and a high level is INPUT to the third signal terminal GCL.

In this stage, the scanning of all the shift registers is completed, or the input of the current frame of picture is completed, so that each shift register does not work any more, so that the display panel keeps displaying the current frame of picture, and the shift registers at each stage start scanning again until the next frame of picture starts.

Specifically, in this stage, the third signal terminal GCL is kept at the high level, so that the ninth transistor M9 and the seventh transistor M7 are both turned on, and the low level of the constant voltage terminal VGL is continuously introduced into the pull-up node PU and the INPUT terminal INPUT. Therefore, the shift register can continuously and stably output low level, prevent the level of the pull-up node PU from rising due to electric leakage, eliminate the charge accumulation of the storage capacitor C, avoid output abnormity (particularly for the last stage of shift register) when the next frame picture starts, and ensure the display quality.

(b) As shown in fig. 4, during the reverse scan (i.e., scanning from the high-level shift register to the low-level shift register), a low level is continuously input to the first signal terminal FW, a high level is continuously input to the second signal terminal BW, and a low level is continuously input to the constant level terminal VGL, and the driving process of the shift register specifically includes:

s21, charging stage: a high level is INPUT to the RESET terminal RESET, a low level is INPUT to the first clock terminal CLK, a high level is INPUT to the second clock terminal CLKB, a low level is INPUT to the INPUT terminal INPUT, and a low level is INPUT to the third signal terminal GCL.

In this stage, the RESET terminal RESET is at a high level (a conducting signal OUTPUT from the next stage shift register, and is a reverse scan, so that the next stage shift register OUTPUTs a conducting signal first), the second transistor M2 is turned on, the high level of the second signal terminal BW is introduced into the pull-up node PU, and the third transistor M3 is turned on, the low level of the first clock terminal CLK is introduced into the OUTPUT terminal OUTPUT, so that the shift register OUTPUTs a low level, and the storage capacitor C is charged.

S22, output stage: a low level is INPUT to the RESET terminal RESET, a high level is INPUT to the first clock terminal CLK, a low level is INPUT to the second clock terminal CLKB, a low level is INPUT to the INPUT terminal INPUT, and a low level is INPUT to the third signal terminal GCL.

In this stage, the RESET terminal RESET becomes a low level, so the second transistor M2 is turned off, the pull-up node PU cannot discharge and keeps a high level, the third transistor M3 keeps on, and the high level of the first clock terminal CLK is introduced to the OUTPUT terminal OUTPUT, so that the shift register OUTPUTs a high level on signal.

S23, resetting: a low level is INPUT to the RESET terminal RESET, a low level is INPUT to the first clock terminal CLK, a high level is INPUT to the second clock terminal CLKB, a high level is INPUT to the INPUT terminal INPUT, and a low level is INPUT to the third signal terminal GCL.

In this stage, the INPUT terminal INPUT becomes a high level (a turn-on signal from the shift register of the previous stage), so that the first transistor M1 is turned on, a low level of the first signal terminal FW is introduced into the pull-up node PU, and the pull-up node PU becomes a low level; since the second clock terminal CLKB is also at the high level, the fourth transistor M4 is turned on, the low level of the constant level terminal VGL is introduced into the OUTPUT terminal OUTPUT, the shift register OUTPUTs the low level, and the storage capacitor C is discharged.

S24, keeping stage: a low level is INPUT to the RESET terminal RESET, a high level is alternately INPUT to the first clock terminal CLK and the second clock terminal CLKB, a low level is INPUT to the INPUT terminal INPUT, and a low level is INPUT to the third signal terminal GCL.

In this stage, when the second clock terminal CLKB is at a high level, the pull-down node PD can be at a high level, and a low level of the fixed level terminal VGL is introduced into the OUTPUT terminal OUTPUT and the pull-up node PU; since the time interval of the high level of the second clock terminal CLKB is short, the OUTPUT terminal OUTPUT approximately keeps outputting the low level.

S25, Blank phase (Blank Time): a low level is INPUT to the RESET terminal RESET, a low level is INPUT to the first clock terminal CLK, a low level is INPUT to the second clock terminal CLKB, a low level is INPUT to the INPUT terminal INPUT, and a high level is INPUT to the third signal terminal GCL.

In this stage, the third signal terminal GCL is kept at a high level, so that the ninth transistor M9 and the seventh transistor M7 are both turned on, and a low level of the constant level terminal VGL is continuously introduced into the pull-up node PU and the INPUT terminal INPUT. Therefore, the shift register can continuously and stably output low level, prevent the level of the pull-up node PU from rising due to electric leakage, eliminate the charge accumulation of the storage capacitor C, avoid output abnormity (particularly for the last stage of shift register) when the next frame picture starts, and ensure the display quality.

The shift register with N-type transistors as an example is described above, and if all the transistors are P-type transistors, the driving method of the shift register is as follows:

(a) in the forward direction scanning, a low level is continuously input to the first signal terminal FW, a high level is continuously input to the second signal terminal BW, and a high level is continuously input to the constant level terminal vlow L, and the driving process of the shift register specifically includes:

a charging stage: a low level is INPUT to the INPUT terminal INPUT, a high level is INPUT to the first clock terminal CLK, a low level is INPUT to the second clock terminal CLKB, a high level is INPUT to the RESET terminal RESET, and a high level is INPUT to the third signal terminal low CL.

An output stage: a high level is INPUT to the INPUT terminal INPUT, a low level is INPUT to the first clock terminal CLK, a high level is INPUT to the second clock terminal CLKB, a high level is INPUT to the RESET terminal RESET, and a high level is INPUT to the third signal terminal low CL.

A reset stage: a high level is INPUT to the INPUT terminal INPUT, a high level is INPUT to the first clock terminal CLK, a low level is INPUT to the second clock terminal CLKB, a low level is INPUT to the RESET terminal RESET, and a high level is INPUT to the third signal terminal low CL.

A maintaining stage: a high level is INPUT to the INPUT terminal INPUT, a low level is alternately INPUT to the first clock terminal CLK and the second clock terminal CLKB, a high level is INPUT to the RESET terminal RESET, and a high level is INPUT to the third signal terminal low CL.

An idle stage: a high level is INPUT to the INPUT terminal INPUT, a high level is INPUT to the first clock terminal CLK, a high level is INPUT to the second clock terminal CLKB, a high level is INPUT to the RESET terminal RESET, and a low level is INPUT to the third signal terminal low CL.

(b) In the reverse scan, a high level is continuously input to the first signal terminal FW, a low level is continuously input to the second signal terminal BW, and a high level is continuously input to the constant level terminal vlow L, and the driving process of the shift register specifically includes:

a charging stage: a low level is INPUT to the RESET terminal RESET, a high level is INPUT to the first clock terminal CLK, a low level is INPUT to the second clock terminal CLKB, a high level is INPUT to the INPUT terminal INPUT, and a high level is INPUT to the third signal terminal low CL.

An output stage: a high level is INPUT to the RESET terminal RESET, a low level is INPUT to the first clock terminal CLK, a high level is INPUT to the second clock terminal CLKB, a high level is INPUT to the INPUT terminal INPUT, and a high level is INPUT to the third signal terminal low CL.

A reset stage: a high level is INPUT to the RESET terminal RESET, a high level is INPUT to the first clock terminal CLK, a low level is INPUT to the second clock terminal CLKB, a low level is INPUT to the INPUT terminal INPUT, and a high level is INPUT to the third signal terminal low CL.

A maintaining stage: a high level is INPUT to the RESET terminal RESET, a low level is alternately INPUT to the first clock terminal CLK and the second clock terminal CLKB, a high level is INPUT to the INPUT terminal INPUT, and a high level is INPUT to the third signal terminal low CL.

An idle stage: a high level is INPUT to the RESET terminal RESET, a high level is INPUT to the first clock terminal CLK, a high level is INPUT to the second clock terminal CLKB, a high level is INPUT to the INPUT terminal INPUT, and a low level is INPUT to the third signal terminal low CL.

It should be understood that in the above driving method, the levels of all the driving signals are opposite to those of the transistors in the N-type, so that the operating states of all the transistors are substantially the same in any stage thereof, and the operation process of the shift register is also the same, so that the detailed description thereof will not be provided herein.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A shift register, comprising:

the first pole of the storage capacitor is connected with the upper pull node, and the second pole of the storage capacitor is connected with the output end;

the input unit includes a first transistor, wherein,

the grid electrode of the first transistor is connected with the input end, the first pole of the first transistor is connected with the first signal end, and the second pole of the first transistor is connected with the upper pull node;

the reset unit includes a second transistor, wherein,

the grid electrode of the second transistor is connected with the reset end, the first pole is connected with the upper pull node, and the second pole is connected with the second signal end;

the output unit includes a third transistor, wherein,

the grid electrode of the third transistor is connected with a pull-up node, the first pole of the third transistor is connected with the first clock end, and the second pole of the third transistor is connected with the output end;

the pull-down unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, wherein,

the grid electrode of the ninth transistor is connected with a third signal end, the first electrode of the ninth transistor is connected with the output end, and the second electrode of the ninth transistor is connected with the fixed-level end;

the fixed level end is used for obtaining a turn-off signal in the idle stage, and the third signal end is used for obtaining a turn-on signal so as to introduce the turn-off signal of the fixed level end into the pull-up node and the output end.

2. The shift register of claim 1, wherein the pull-down control unit includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, wherein,

3. The shift register of claim 2,

all transistors are N-type transistors;

alternatively, the first and second electrodes may be,

all transistors are P-type transistors.

4. A gate drive circuit, comprising:

a plurality of cascaded shift registers, the shift registers of any one of claims 1 to 3.

5. A method of driving a shift register according to any one of claims 1 to 3, the method comprising:

6. The method of driving a shift register according to claim 5,

the shift register is the shift register in which all transistors are N-type transistors according to claim 3, and the driving method of the shift register includes:

alternatively, the first and second electrodes may be,

the shift register is the shift register in which all transistors are P-type transistors according to claim 3, and the driving method of the shift register includes: