CN107248390B - Shifting register unit and driving method thereof, grid driving circuit and display device - Google Patents

Shifting register unit and driving method thereof, grid driving circuit and display device Download PDF

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Publication number
CN107248390B
CN107248390B CN201710623527.3A CN201710623527A CN107248390B CN 107248390 B CN107248390 B CN 107248390B CN 201710623527 A CN201710623527 A CN 201710623527A CN 107248390 B CN107248390 B CN 107248390B
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China
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signal
transistor
node
shift register
potential
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CN201710623527.3A
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Chinese (zh)
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CN107248390A (en
Inventor
冯雪欢
李永谦
李蒙
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to CN201710623527.3A priority Critical patent/CN107248390B/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using semiconductor elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit

Abstract

The invention discloses a shift register unit, a driving method thereof, a grid driving circuit and a display device, and belongs to the technical field of display. The shift register unit includes: the device comprises a shifting module, an initialization module and an output control module; the shift module is capable of outputting a drive signal to a first control node; the initialization module is capable of outputting an initialization signal to the second control node; the output control module is used for outputting signals on the control nodes of which the electric potentials are effective electric potentials in the first control node and the second control node to the output end. Therefore, the shift register unit provided by the invention not only can normally scan and drive the display panel, but also can output an initialization signal to the display panel under the control of the initialization module, and the initialization signal can initialize the switch transistor in the pixel unit, so that the switch transistor is discharged, and the influence of residual charges on the charging effect is avoided.

Description

Shifting register unit and driving method thereof, grid driving circuit and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a shift register unit, a driving method thereof, a gate driving circuit, and a display device.

Background

In a display device, when displaying an image, it is necessary to scan a pixel unit with a shift register (i.e., a gate driver circuit).

The shift register in the related art includes a plurality of cascaded shift register units, each shift register unit corresponds to a row of pixel units, and when the shift register unit outputs a driving signal, the corresponding row of pixel units can be lighted. The plurality of cascaded shift register units can realize the progressive scanning driving of each row of pixel units in the display device so as to display images.

However, the shift register unit in the related art has a single operation mode and low flexibility in driving.

Disclosure of Invention

In order to solve the problems of single working mode and low flexibility in driving of the shift register unit in the related art, the invention provides the shift register unit, a driving method thereof, a grid driving circuit and a display device. The technical scheme is as follows:

in a first aspect, a shift register unit is provided, which includes:

the device comprises a shifting module, an initialization module and an output control module;

the shift module is connected with an input signal end and a first control node, and is used for outputting a driving signal to the first control node under the control of the input signal end, wherein the driving signal is used for driving a pixel unit in a display panel;

the initialization module is connected with an initialization signal end, an enable signal end and a second control node, and is used for outputting an initialization signal from the initialization signal end to the second control node under the control of the enable signal end, wherein the initialization signal is used for initializing pixel units in the display panel;

the output control module is respectively connected with the first control node, the second control node and the output end, and is used for outputting a signal from a target control node to the output end, wherein the target control node is a control node of which the electric potential is an effective electric potential in the first control node and the second control node.

Optionally, the initialization module includes: a data trigger;

the clock signal end of the data trigger is connected with the enable signal end, the input end of the data trigger is connected with the initialization signal end, the output end of the data trigger is connected with the second control node, and the data trigger is used for outputting the initialization signal from the initialization signal end to the second control node when the enable signal output by the enable signal end is at a rising edge.

Optionally, the output control module includes: an OR gate;

and a first input end of the OR gate is connected with the first control node, a second input end of the OR gate is connected with the second control node, and an output end of the OR gate is an output end of the shift register unit.

Optionally, the shifting module includes: the input submodule, the output submodule, the anti-creeping submodule and the pull-down submodule are connected;

the input submodule is respectively connected with an input signal end, a first clock signal end, an anti-creeping node and a pull-up node and is used for controlling the potential of the pull-up node under the control of an input signal from the input signal end, a first clock signal from the first clock signal end and the anti-creeping node;

the output submodule is respectively connected with the pull-up node, a second clock signal end and the first control node and is used for outputting a driving signal to the first control node under the control of the pull-up node and a second clock signal from the second clock signal end;

the anti-leakage sub-module is respectively connected with the second clock signal end and the anti-leakage node and is used for controlling the potential of the anti-leakage node under the control of the second clock signal;

the pull-down submodule is respectively connected with a reset signal end, the input signal end, a power signal end, the anti-creeping node, the pull-up node and the first control node and is used for carrying out noise reduction on the pull-up node and the first control node under the control of a reset signal from the reset signal end, a power signal from the power signal end, the input signal and the anti-creeping node.

Optionally, the input sub-module includes: a first transistor and a second transistor; the output sub-module includes: a third transistor and a capacitor; the anticreep sub-module includes: a fourth transistor; the pull-down sub-module includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

the grid electrode of the first transistor is connected with the first clock signal end, the first pole of the first transistor is connected with the input signal end, and the second pole of the first transistor is connected with the anti-leakage node;

the grid electrode of the second transistor is connected with the input signal end, the first pole of the second transistor is connected with the anti-leakage node, and the second pole of the second transistor is connected with the pull-up node;

a gate of the third transistor is connected to the pull-up node, a first pole of the third transistor is connected to the second clock signal terminal, and a second pole of the third transistor is connected to the first control node;

one end of the capacitor is connected with the pull-up node, and the other end of the capacitor is connected with the first control node;

the grid electrode and the first electrode of the fourth transistor are connected with the second clock signal end, and the second electrode of the fourth transistor is connected with the anti-leakage node;

a gate of the fifth transistor is connected to the input signal terminal, a first pole of the fifth transistor is connected to the power signal terminal, and a second pole of the fifth transistor is connected to a gate of the sixth transistor;

a first pole of the sixth transistor is connected with the anti-leakage node, and a second pole of the sixth transistor is connected with the pull-up node;

a gate of the seventh transistor is connected to the input signal terminal, a first pole of the seventh transistor is connected to the power signal terminal, and a second pole of the seventh transistor is connected to a pull-down node;

a gate and a first pole of the eighth transistor are connected to the reset signal terminal, and a second pole of the eighth transistor is connected to the pull-down node;

a gate of the ninth transistor is connected to the pull-down node, a first pole of the ninth transistor is connected to the reset signal terminal, and a second pole of the ninth transistor is connected to a gate of the sixth transistor;

a gate of the tenth transistor is connected to the pull-down node, a first pole of the tenth transistor is connected to the power signal terminal, and a second pole of the tenth transistor is connected to the first control node.

In a second aspect, there is provided a driving method of a shift register unit, the shift register unit including: the device comprises a shifting module, an initialization module and an output control module; the method comprises the following steps:

in the initialization stage, an enable signal output by an enable signal end jumps from a second potential to a first potential, an initialization signal output by the initialization signal end is at the first potential, the initialization module outputs the initialization signal to a second control node, and the output control module outputs the initialization signal to an output end;

in the driving stage, the initialization signal is at a second potential, the enable signal jumps from the second potential to a first potential, an input signal output by an input signal end is the first potential, the initialization module outputs the initialization signal to the second control node, the shift module outputs a driving signal at the first potential to the first control node, and the output control module outputs the driving signal to the output end;

wherein the first potential is an effective potential.

Optionally, the shifting module includes: the input submodule, the output submodule, the anti-creeping submodule and the pull-down submodule are connected; the driving phase comprises:

in the charging stage, the input signal is a first potential, a first clock signal output by a first clock signal end is a first potential, and the input submodule outputs the input signal to a pull-up node under the control of the input signal and the first clock signal;

in the output stage, a second clock signal output by a second clock signal end is a first potential, the pull-up node is the first potential, the output submodule outputs the second clock signal to the first control node under the control of the pull-up node, and the anti-leakage submodule outputs the second clock signal to the anti-leakage node;

in the reset stage, a reset signal output by a reset signal end is a first potential, the input signal is a second potential, the first clock signal is the first potential, the pull-down submodule outputs the input signal to the pull-up node and outputs a power supply signal from a power supply signal end to the first control node under the control of the reset signal and the first clock signal, and the power supply signal is the second potential.

In a third aspect, a gate driving circuit is provided, which includes: at least two cascaded shift register cells according to the first aspect;

the first control node in each shift register unit is connected with the input signal end of the next-stage shift register unit;

each shift register unit is connected with an enabling signal end, or all the shift register units are connected with the same enabling signal end; or, the gate driving circuit comprises at least two shift register groups, each shift register group comprises at least one shift register unit, and each shift register group is connected with an enable signal terminal.

Optionally, the initialization signal end of each shift register unit is connected to the second control node of the previous shift register unit;

or all the shift register units are connected with the same initialization signal end;

or, the gate driving circuit includes at least two shift register groups, each shift register group includes at least one shift register unit, each shift register group is connected to an initialization signal terminal, and the initialization signal terminal of each shift register group is connected to the initialization signal terminal of the next shift register group through the delay module.

In a fourth aspect, there is provided a display device including: a gate drive circuit as claimed in the third aspect.

The technical scheme provided by the invention has the beneficial effects that:

the invention provides a shift register unit and a driving method thereof, a gate driving circuit and a display device, wherein the shift register unit also comprises an initialization module and an output control module, the initialization module can output an initialization signal to the output end of the shift register unit through the output control module under the control of an enable signal end and an initialization signal end, and the initialization signal can initialize a switch transistor in a pixel unit, so that the switch transistor is discharged, and the influence of residual charges on the charging effect is avoided. Therefore, the shift register unit provided by the embodiment of the invention not only has the function of scanning driving, but also has the function of initialization, and has the advantages of richer working modes and higher driving flexibility.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another shift register unit according to an embodiment of the present invention;

FIG. 4 is a flowchart of a driving method of a shift register unit according to an embodiment of the present invention;

FIG. 5 is a flow chart of a driving method for driving a phase according to an embodiment of the present invention;

FIG. 6 is a timing diagram of a shift register unit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention;

fig. 9 is a timing diagram of signal terminals in a gate driving circuit according to an embodiment of the invention;

fig. 10 is a timing diagram of signal terminals in another gate driving circuit according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics, and the transistors used in embodiments of the present invention are mainly switching transistors depending on the role in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present invention, the source is referred to as a first stage, and the drain is referred to as a second stage. The form of the figure provides that the middle end of the transistor is a grid, the signal input end is a source, and the signal output end is a drain. In addition, the switching transistor used in the embodiment of the present invention may include any one of a P-type switching transistor and an N-type switching transistor, in which the P-type switching transistor is turned on when the gate is at a low potential and turned off when the gate is at a high potential, and the N-type switching transistor is turned on when the gate is at a high potential and turned off when the gate is at a low potential. In addition, the plurality of signals in the embodiments of the present invention correspond to the first potential and the second potential. The first potential and the second potential represent only 2 state quantities of the potential of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as can be seen from fig. 1, the display device may generally include a host 00, a display panel 01, a timing controller 02, a gate driving circuit 03, and a source driving circuit 04. The timing controller 02 is connected to the host 00, the gate driving circuit 03, and the source driving circuit 04, respectively, and is configured to control operating states of the gate driving circuit 03 and the source driving circuit 04. The gate driving circuit 03 is respectively connected to each row of pixel units in the display panel 01, and is configured to scan a plurality of rows of pixel units in the display panel 01 line by line. The source driving circuit 04 is respectively connected to each row of pixel units of the display panel 01, and is configured to output data signals to the plurality of rows of pixel units to charge the plurality of rows of pixel units.

For example, in fig. 1, the display panel 01 includes n rows and m columns of pixel units, and the gate driving circuit 03 can output n gate driving signals of G1 to Gn to the n rows of pixel units respectively; the source driving circuit 04 may output m paths of data signals of D1 to Dm to the m columns of pixel units, respectively.

Fig. 2 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention, where the shift register unit may be applied to the gate driving circuit 03 shown in fig. 1, and as shown in fig. 2, the shift register unit may include: a shift module 10, an initialization module 20 and an output control module 30.

The shift module 10 is connected to an input signal terminal IN and a first control node S1, and is used for outputting a driving signal to the first control node S1 under the control of the input signal terminal IN, wherein the driving signal is used for driving a pixel unit IN a display panel.

The initialization module 20 is connected to an initialization signal terminal INIT, an enable signal terminal EN, and a second control node S2, and is configured to output an initialization signal from the initialization signal terminal INIT to the second control node S2 under the control of the enable signal terminal EN, where the initialization signal is used to initialize a pixel unit in the display panel.

The output control module 30 is respectively connected to the first control node S1, the second control node S2 and the output terminal OUT, and is configured to output a signal from a target control node to the output terminal OUT, wherein the target control node is one of the first control node S1 and the second control node S2, and the potential of the target control node is active potential. That is, the output control module 30 can control the potential of the output terminal OUT to be the effective potential when the potential of any control node is the effective potential.

In summary, the embodiments of the present invention provide a shift register unit, which further includes an initialization module and an output control module, where the initialization module can output an initialization signal to an output end of the shift register unit through the output control module under the control of an enable signal end and an initialization signal end, and the initialization signal can initialize a switching transistor in a pixel unit, so that the switching transistor is discharged, and the influence of residual charges on a charging effect is avoided. Therefore, the shift register unit provided by the embodiment of the invention not only has the function of scanning driving, but also has the function of initialization, and has the advantages of richer working modes and higher driving flexibility.

Fig. 3 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention, and referring to fig. 3, the initialization module 20 may specifically include: a data flip-flop 201.

The clock signal terminal CK of the data flip-flop 201 is connected to the enable signal terminal EN, the input terminal D of the data flip-flop 201 is connected to the initialization signal terminal INIT, and the output terminal Q of the data flip-flop 201 is connected to the second control node S2. The data flip-flop 201 is configured to output the initialization signal from the initialization signal terminal INIT to the second control node S2 when the enable signal output by the enable signal terminal EN is at a rising edge. While the potential of the enable signal output from the enable signal terminal EN remains unchanged, the data flip-flop 201 may control the potential of the output terminal (i.e., the second control node S2) thereof to remain at the previous stage.

In practical applications, the initialization module 20 may be composed of other electronic components besides the data flip-flop, as long as it is ensured that the initialization signal can be output to the second control node S2 when the enable signal is at the rising edge.

Alternatively, as shown in fig. 3, the output control module 30 may include: or gate 301.

The first input terminal of the or gate 301 is connected to the first control node S1, the second input terminal of the or gate 301 is connected to the second control node S2, and the output terminal of the or gate 301 is the output terminal OUT of the shift register unit. The or gate 301 may control the potential of the output terminal OUT to be an active potential when the potential of any one of the control nodes has an active potential, and control the potential of the output terminal OUT to be an inactive potential when the potentials of the two control nodes are both inactive potentials.

Further, as shown in fig. 3, in the shift register unit provided in the embodiment of the present invention, the shift module 10 may specifically include: an input sub-module 101, an output sub-module 102, an anti-creeping sub-module 103 and a pull-down sub-module 104.

The input sub-module 101 is respectively connected to an input signal terminal IN, a first clock signal terminal CLKB, a leakage-preventing node P1 and a pull-up node PU, and is configured to control a potential of the pull-up node PU under the control of an input signal from the input signal terminal IN, a first clock signal from the first clock signal terminal CLKB and the leakage-preventing node P1.

The output sub-module 102 is respectively connected to the pull-up node PU, a second clock signal terminal CLK and the first control node S1, and is configured to output a driving signal to the first control node S1 under the control of the pull-up node PU and a second clock signal from the second clock signal terminal CLK. Specifically, the output sub-module 102 may output the second clock signal to the first control node S1 when the voltage level of the pull-up node PU is the first voltage level, where the second clock signal is a driving signal for driving the pixel unit.

The anti-leakage submodule 103 is respectively connected to the second clock signal terminal CLK and the anti-leakage node P1, and is configured to control a potential of the anti-leakage node P1 under the control of the second clock signal. Specifically, the anti-leakage sub-module 103 can control the potential of the anti-leakage node P1 to be the first potential when the second clock signal is the first potential, so as to ensure that the potentials of the anti-leakage node P1 and the pull-up node PU are the first potential in the output phase, thereby avoiding the influence of the leakage of the transistors connected with the two nodes on the potential of the pull-up node PU, and ensuring the stability of the potential of the pull-up node PU.

The pull-down submodule 104 is respectively connected to the reset signal terminal STD, the input signal terminal IN, the power signal terminal VGL, the anti-leakage node P1, the pull-up node PU and the first control node S1, and is configured to perform noise reduction on the pull-up node PU and the first control node S1 under the control of the reset signal from the reset signal terminal STD, the power signal from the power signal terminal VGL, the input signal, the power signal and the anti-leakage node P1.

Specifically, referring to fig. 3, the input sub-module 101 may include: a first transistor M1 and a second transistor M2; the output sub-module 102 may include: a third transistor M3 and a capacitor C; the anti-creeping module 103 may include: a fourth transistor M4; the pull-down sub-module 104 may include: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.

The gate of the first transistor M1 is connected to the first clock signal terminal CLKB, the first pole of the first transistor M1 is connected to the input signal terminal IN, and the second pole of the first transistor M1 is connected to the leakage-proof node P1.

The gate of the second transistor M2 is connected to the input signal terminal IN, the first pole of the second transistor M2 is connected to the anti-leakage node P1, and the second pole of the second transistor M2 is connected to the pull-up node PU.

When the second clock signal output from the second clock signal terminal CLKB and the input signal output from the input signal terminal IN are both at the first potential, the first transistor M1 and the second transistor M2 are turned on, and the input signal terminal IN can output the input signal to the pull-up node PU, thereby charging the pull-up node PU.

The gate of the third transistor M3 is connected to the pull-up node PU, the first pole of the third transistor M3 is connected to the second clock signal terminal CLK, and the second pole of the third transistor M3 is connected to the first control node S1.

One end of the capacitor C is connected to the pull-up node PU, and the other end of the capacitor C is connected to the first control node S1.

When the voltage level of the pull-up node PU is the first voltage level, the third transistor M3 is turned on, and the second clock signal terminal CLK can output the second clock signal to the first control node S1.

The gate and the first pole of the fourth transistor M4 are connected to the second clock signal terminal CLK, and the second pole of the fourth transistor M4 is connected to the leakage-preventing node P1. When the second clock signal is at the first potential, the fourth transistor M4 is turned on and outputs the second clock signal to the anti-leakage node P1 such that the potential of the anti-leakage node P1 is also at the first potential. Therefore, in the output stage, the potentials of the first pole and the second pole of the second transistor M2 and the sixth transistor M6 are both the first potential, so that the leakage currents of the second transistor M2 and the sixth transistor M6 can be effectively reduced, and the influence of the leakage currents on the potential of the pull-up node PU is avoided.

The gate of the fifth transistor M5 is connected to the input signal terminal IN, the first pole of the fifth transistor M5 is connected to the power signal terminal VGL, and the second pole of the fifth transistor M5 is connected to the gate of the sixth transistor M6.

The first pole of the sixth transistor M6 is connected to the leakage-proof node P1, and the second pole of the sixth transistor M6 is connected to the pull-up node PU.

The gate of the seventh transistor M7 is connected to the input signal terminal IN, the first pole of the seventh transistor M7 is connected to the power signal terminal VGL, and the second pole of the seventh transistor M7 is connected to the pull-down node PD.

The gate and the first pole of the eighth transistor M8 are connected to the reset signal terminal STD, and the second pole of the eighth transistor M8 is connected to the pull-down node PD.

The gate of the ninth transistor M9 is connected to the pull-down node PD, the first pole of the ninth transistor M9 is connected to the reset signal terminal STD, and the second pole of the ninth transistor M9 is connected to the gate of the sixth transistor M6.

The gate of the tenth transistor M10 is connected to the pull-down node PD, the first pole of the tenth transistor M10 is connected to the power signal terminal VGL, and the second pole of the tenth transistor M10 is connected to the first control node S1.

In summary, the embodiments of the present invention provide a shift register unit, which further includes an initialization module and an output control module, where the initialization module can output an initialization signal to an output end of the shift register unit through the output control module under the control of an enable signal end and an initialization signal end, and the initialization signal can initialize a switching transistor in a pixel unit, so that the switching transistor is discharged, and the influence of residual charges on a charging effect is avoided. Therefore, the shift register unit provided by the embodiment of the invention can realize double-pulse output, has the functions of scanning driving and initialization, and has the advantages of rich working modes and high driving flexibility.

Fig. 4 is a flowchart of a driving method of a shift register unit according to an embodiment of the present invention, for driving the shift register unit shown in fig. 2 or fig. 3, where as shown in fig. 2, the shift register unit may include: a shift module 10, an initialization module 20 and an output control module 30. Referring to fig. 4, the driving method may specifically include:

in step 201, in the initialization phase, the enable signal output by the enable signal terminal EN jumps from the second potential to the first potential, the initialization signal output by the initialization signal terminal INIT is at the first potential, the initialization module 20 outputs the initialization signal to the second control node S2, and the output control module 30 outputs the initialization signal to the output terminal OUT.

Step 202, IN the driving phase, the initialization signal is at the second potential, the enable signal jumps from the second potential to the first potential, the input signal output by the input signal terminal IN is at the first potential, the initialization module 20 outputs the initialization signal to the second control node S2, the shift module 10 outputs the driving signal at the first potential to the first control node S1, and the output control module 30 outputs the driving signal to the output terminal OUT.

Wherein the first potential is an effective potential. For example, when the transistors in the shift register unit are all N-type transistors, the first potential (i.e., the effective potential) can be a high potential.

Optionally, as shown in fig. 3, the shift module 10 may specifically include: an input sub-module 101, an output sub-module 102, an anti-creeping sub-module 103 and a pull-down sub-module 104; correspondingly, as shown in fig. 5, the driving phase shown in step 202 may specifically include:

step 2021, in the charging stage, the input signal is at the first voltage level, the first clock signal output by the first clock signal terminal CLKB is at the first voltage level, and the input sub-module 101 outputs the input signal to the pull-up node PU under the control of the input signal and the first clock signal.

In step 2022, in the output stage, the second clock signal outputted from the second clock signal terminal CLK is at the first voltage level, the pull-up node PU is at the first voltage level, the output sub-module 102 outputs the second clock signal to the first control node S1 under the control of the pull-up node PU, and the anti-leakage sub-module 103 outputs the second clock signal to the anti-leakage node P1.

Step 2023, during the reset phase, the reset signal output by the reset signal terminal STD is at the first potential, the input signal is at the second potential, the first clock signal is at the first potential, the pull-down sub-module 104 outputs the input signal to the pull-up node PU under the control of the reset signal and the first clock signal, and outputs the power signal from the power signal terminal VGL to the first control node S1, where the power signal is at the second potential.

Fig. 6 is a driving timing diagram of a shift register unit according to an embodiment of the present invention, and details a driving principle of the shift register unit according to the embodiment of the present invention will be described with reference to the shift register unit shown in fig. 3 as an example.

Referring to fig. 6, in the initialization phase t1, the enable signal output from the enable signal terminal EN transitions from the second potential to the first potential, the initialization signal output from the initialization signal terminal INIT is at the first potential, and the data flip-flop 201 outputs the initialization signal at the first potential to the second control node S2 under the driving of the enable signal. Since the input signal outputted from the input signal terminal IN is at the second potential, the shift module 10 has not yet started to operate, and the potential of the first control node S1 is at the second potential. Further, referring to fig. 3, the or gate 301 may output the initialization signal to the output terminal OUT under the driving of the two control nodes, so that the potential of the output terminal OUT is pulled up to the first potential. The initialization signal can drive the switching transistors in a row of pixel units in the display panel to discharge, so that the influence of residual charges on the display effect is avoided, and the initialization of the row of pixel units is realized.

In addition, as can be seen from fig. 6, in the initialization period t1, the enable signal output from the enable signal terminal EN also jumps from the first potential to the second potential after maintaining the first level for a period of time, so as to trigger the data flip-flop 201 to reset the potential of the second control node S2 in the next period.

Further, in the charging phase t2 of the driving phase, the enable signal jumps from the second potential to the first potential, the initialization signal is the second potential, and the data flip-flop 201 outputs the initialization signal of the second potential to the second control node S2; meanwhile, since the input signal output from the input signal terminal IN is at the first potential and the first clock signal output from the first clock signal terminal CLKB is at the first potential (not shown IN fig. 6), the first transistor M1 and the second transistor M2 are turned on, and the input signal terminal IN can output the input signal to the pull-up node PU, thereby charging the pull-up node PU. The third transistor M3 is turned on, and the second clock signal terminal CLK outputs the second clock signal to the first control node S1, and the second clock signal is at the second potential. Since the potentials of the first control node S1 and the second control node S2 are both the second potential, the or gate 301 controls the potential of the output terminal OUT to be the second potential as shown in fig. 6.

In addition, it should be noted that, in the charging phase t2, the fifth transistor M5 and the seventh transistor M7 are turned on under the driving of the input signal, the power signal terminal VGL outputs the power signal at the second potential to the gate of the sixth transistor M6 and the pull-down node PD, respectively, so that the sixth transistor M6, the ninth transistor M9 and the tenth transistor M10 are turned off, thereby avoiding the influence on the potential of the pull-up node PU.

With continued reference to fig. 6, in the output phase t3, the enable signal is at the second potential, and thus the data flip-flop 201 may control the potential of the second node S2 to maintain the second potential of the previous phase. Meanwhile, since the second clock signal output from the second clock signal terminal CLK is at the first potential and the potential of the pull-up node PU is further pulled high by the bootstrap action of the capacitor C, the third transistor M3 can be fully turned on, and the second clock signal terminal CLK outputs the second clock signal at the first potential to the first control node S1. At this time, since the first control node S1 is at the first potential and the second control node S2 is at the second point, as shown in fig. 6, the or gate 301 can control the potential of the output terminal OUT to be at the first potential, that is, output the second clock signal to the output terminal OUT, wherein the second clock signal is used for driving the pixel unit in the display panel.

In the output stage t3, the input signal and the first clock signal are both at the second potential, and the first transistor M1, the second transistor M2, and the fifth transistor M5 and the seventh transistor M7 are all turned off. The fourth transistor M4 is turned on under the driving of the second clock signal terminal CLK to pull up the potential of the leakage-proof node P1 to the first potential, and since the potentials of the second pole of the first transistor M1 are both the first potential and the potentials of the second pole of the first pole of the second transistor M2 are both the first potential, the leakage current of the first transistor M1 and the second transistor M2 can be prevented, thereby ensuring the stability of the potential of the pull-up node PU.

In the reset phase t4, the enable signal is at the second potential, so the data flip-flop 201 can control the potential of the second node S2 to maintain the second potential of the previous phase. Meanwhile, the reset signal output from the reset signal terminal STD and the first clock signal output from the first clock signal terminal CLKB are at the first potential, and the input signal is at the second potential, at this time, the first transistor M1 is turned on, and the input signal at the second potential is output to the anti-leakage node P1; the eighth transistor M8 is turned on, and the reset signal terminal STD pulls down the node PD to output a reset signal at the first potential; under the driving of the pull-down node PD, the ninth transistor M9 and the tenth transistor M10 are turned on, and the power signal terminal VGL outputs a power signal at the second potential to the first control node S1 to reset the first control node S1; meanwhile, the reset signal terminal STD may also output a reset signal to the gate of the sixth transistor M6, so that the sixth transistor M6 is turned on, the anti-leakage node P1 is connected to the pull-up node PU, and since the potential of the anti-leakage node P1 is the second potential, the potential of the pull-up node PU is also pulled low, thereby resetting the pull-up node PU. In the reset phase t4, since the potentials of the first control node S1 and the second control node S2 are both the second potential, the or gate 301 controls the potential of the output terminal OUT to be the second potential as shown in fig. 6.

It should be noted that the charging phase t2, the output phase t3 and the reset phase t4 constitute the driving phase of the shift register unit. The driving phase may be executed immediately after the initialization phase is ended, or may be executed after a certain time interval, which is not limited in the embodiment of the present invention.

It should be noted that, in the embodiment of the present invention, the clock signals outputted by the first clock signal terminal CLKB and the second clock signal terminal CLK have the same frequency and complementary potentials, that is, when the first clock signal is at the first potential, the second clock signal is at the second potential, and when the first clock signal is at the second potential, the second clock signal is at the first potential. The power signal output by the power signal terminal VGL is a dc signal, and the potential thereof may be an inactive potential. For example, when the transistors in the shift register unit are N-type transistors, the potential of the power supply signal is low, and when the transistors in the shift register unit are P-type transistors, the potential of the power supply signal is high.

In summary, in the initialization stage, the initialization module may output the initialization signal to the output terminal of the shift register unit through the output control module under the control of the enable signal terminal and the initialization signal terminal, and the initialization signal may initialize the switching transistor in the pixel unit, so that the switching transistor is discharged, and the influence of the residual charge on the charging effect is avoided. Therefore, the shift register unit provided by the embodiment of the invention can realize double-pulse output, has the functions of scanning driving and initialization, and has the advantages of rich working modes and high driving flexibility.

In the above embodiments, the transistors are N-type transistors, and the first potential is higher than the second potential. Of course, the transistors may also be P-type transistors, and when the transistors are P-type transistors, the first potential may be low relative to the second potential, and the potential of the signal terminals may change in a reverse manner to the potential shown in fig. 6.

Fig. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention, and referring to fig. 7, the gate driving circuit may include at least two cascaded shift register units 00, where each shift register unit 00 may be a shift register unit as shown in fig. 2 or fig. 3.

As can be seen from fig. 7, the first control node S1 IN each shift register unit may be connected to the input signal terminal IN of the next stage shift register unit. For example, IN FIG. 7, the first control node S1-1 IN the first stage of shift register cells is connected to the input signal terminal IN-2 of the second stage of shift register cells.

In the embodiment of the present invention, the initialization modules in each shift register unit may be respectively connected to an enable signal terminal EN, for example, in fig. 7, the initialization modules 20 of n shift register units are respectively connected to the enable signal terminals EN-1 to EN-n in a one-to-one correspondence. Alternatively, the initialization modules in all the shift register units may be connected to the same enable signal terminal EN. Or, the shift register units in the gate driving circuit may be divided into at least two shift register groups, each shift register group includes at least one shift register unit, and each shift register group is connected to the same enable signal terminal EN.

Further, the initialization signal terminal INIT of each shift register unit may be connected to the second control node S2 of the previous stage shift register unit, for example, in fig. 7, the initialization signal terminal INIT-2 of the second stage shift register unit is connected to the second control node S2-1 of the first stage shift register unit.

Alternatively, the initialization modules of all the shift register units may be connected to the same initialization signal terminal INIT.

As shown in fig. 8, the gate driving circuit may be divided into at least two shift register groups, each shift register group includes at least one shift register unit, each shift register group is connected to an initialization signal terminal INIT, and the initialization signal terminal INIT of each shift register group is connected to the initialization signal terminal INIT of the next shift register group through the delay module 40.

For example, in the gate driving circuit shown in fig. 8, the first to tenth stage shift register units are a first group of shift register groups, and the eleventh to twentieth stage shift register units are a second group of shift register groups. The initialization module 20 of each shift register unit in the first shift register group may be connected to an initialization signal terminal INIT-1, and the initialization signal terminal INIT-1 is connected to the initialization module 20 of each shift register unit in the second shift register group through a delay module 40; further, the initialization signal terminal INIT-1 may be connected to an initialization module in the third set of shift registers of the delay module 40. Wherein each delay module 40 may be composed of two inverters and one capacitor.

Further, it should be noted that the reset signal terminal STD in each shift register unit may be connected to the first control node S1 of the next stage shift register unit.

Fig. 9 is a timing diagram of signal terminals in a gate driving circuit according to an embodiment of the present invention, and when the gate driving circuit adopts the connection manner shown in fig. 7, as shown in fig. 9, the n-level shift register unit can output an initialization signal at the same time in the initialization stage t1, so that the full screen of the display panel can be discharged and initialized. Thereafter, the n-stage shift register unit may sequentially perform driving stages, i.e., sequentially output driving signals, from the first stage.

Fig. 10 is a timing diagram of signal terminals in another gate driving circuit according to an embodiment of the present invention, and when the gate driving circuit adopts the connection manner shown in fig. 8, as shown in fig. 10, the first group of shift register units (i.e., the first to tenth shift register units) in the gate driving circuit can output the initialization signal at the same time in the initialization stage t1, so that partial areas of the display panel can be discharged and initialized. Thereafter, the first to tenth stage shift register units may sequentially output driving signals. Further, the second group of shift register units (i.e., the eleventh to twentieth stage shift register units) in the gate driving circuit may simultaneously output the initialization signal in the initialization stage t11, so that another area of the display panel may be discharged and initialized; thereafter, the eleventh to twentieth stage shift register units may sequentially output the driving signals.

It should be noted that, in the embodiment of the present invention, the enable signal terminal and the initialization signal terminal connected to each shift register unit in the gate driving circuit, and the time sequence of the signals output by the two signal terminals may be flexibly adjusted according to the actual application requirements, so as to initialize the full screen or a partial area of the display panel.

In summary, the gate driving circuit provided in the embodiments of the present invention can implement full-screen discharge and initialization on the display panel or discharge and initialization on any area on the display panel by controlling the levels of the signals output by the enable signal terminal and the initialization signal terminal of each stage of the shift register unit, thereby effectively improving the driving flexibility and improving the display effect of the display panel.

Embodiments of the present invention provide a display device, which may include a gate driving circuit as shown in fig. 7 or 8. The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the shift register unit and each module described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A shift register cell, comprising:
the device comprises a shifting module, an initialization module and an output control module;
the shift module is connected with an input signal end and a first control node, and is used for outputting a driving signal to the first control node under the control of the input signal end, wherein the driving signal is used for driving a pixel unit in a display panel;
the initialization module is connected with an initialization signal end, an enable signal end and a second control node, and is used for outputting an initialization signal from the initialization signal end to the second control node under the control of the enable signal end, wherein the initialization signal is used for initializing a pixel unit in the full screen of the display panel or a pixel unit in a partial area, and the enable signal end, the initialization signal end, the time sequence of the enable signal and the time sequence of the initialization signal can be flexibly adjusted according to actual application requirements;
the output control module is respectively connected with the first control node, the second control node and the output end, and is used for outputting a signal from a target control node to the output end, wherein the target control node is a control node of which the electric potential is an effective electric potential in the first control node and the second control node.
2. The shift register cell of claim 1, wherein the initialization module comprises: a data trigger;
the clock signal end of the data trigger is connected with the enable signal end, the input end of the data trigger is connected with the initialization signal end, the output end of the data trigger is connected with the second control node, and the data trigger is used for outputting the initialization signal from the initialization signal end to the second control node when the enable signal output by the enable signal end is at a rising edge.
3. The shift register cell of claim 1, wherein the output control module comprises: an OR gate;
and a first input end of the OR gate is connected with the first control node, a second input end of the OR gate is connected with the second control node, and an output end of the OR gate is an output end of the shift register unit.
4. The shift register cell of any one of claims 1 to 3, wherein the shift module comprises: the input submodule, the output submodule, the anti-creeping submodule and the pull-down submodule are connected;
the input submodule is respectively connected with an input signal end, a first clock signal end, an anti-creeping node and a pull-up node and is used for controlling the potential of the pull-up node under the control of an input signal from the input signal end, a first clock signal from the first clock signal end and the anti-creeping node;
the output submodule is respectively connected with the pull-up node, a second clock signal end and the first control node and is used for outputting a driving signal to the first control node under the control of the pull-up node and a second clock signal from the second clock signal end;
the anti-leakage sub-module is respectively connected with the second clock signal end and the anti-leakage node and is used for controlling the potential of the anti-leakage node under the control of the second clock signal;
the pull-down submodule is respectively connected with a reset signal end, the input signal end, a power signal end, the anti-creeping node, the pull-up node and the first control node and is used for carrying out noise reduction on the pull-up node and the first control node under the control of a reset signal from the reset signal end, a power signal from the power signal end, the input signal and the anti-creeping node.
5. The shift register cell of claim 4, wherein the input submodule comprises: a first transistor and a second transistor; the output sub-module includes: a third transistor and a capacitor; the anticreep sub-module includes: a fourth transistor; the pull-down sub-module includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;
the grid electrode of the first transistor is connected with the first clock signal end, the first pole of the first transistor is connected with the input signal end, and the second pole of the first transistor is connected with the anti-leakage node;
the grid electrode of the second transistor is connected with the input signal end, the first pole of the second transistor is connected with the anti-leakage node, and the second pole of the second transistor is connected with the pull-up node;
a gate of the third transistor is connected to the pull-up node, a first pole of the third transistor is connected to the second clock signal terminal, and a second pole of the third transistor is connected to the first control node;
one end of the capacitor is connected with the pull-up node, and the other end of the capacitor is connected with the first control node;
the grid electrode and the first electrode of the fourth transistor are connected with the second clock signal end, and the second electrode of the fourth transistor is connected with the anti-leakage node;
a gate of the fifth transistor is connected to the input signal terminal, a first pole of the fifth transistor is connected to the power signal terminal, and a second pole of the fifth transistor is connected to a gate of the sixth transistor;
a first pole of the sixth transistor is connected with the anti-leakage node, and a second pole of the sixth transistor is connected with the pull-up node;
a gate of the seventh transistor is connected to the input signal terminal, a first pole of the seventh transistor is connected to the power signal terminal, and a second pole of the seventh transistor is connected to a pull-down node;
a gate and a first pole of the eighth transistor are connected to the reset signal terminal, and a second pole of the eighth transistor is connected to the pull-down node;
a gate of the ninth transistor is connected to the pull-down node, a first pole of the ninth transistor is connected to the reset signal terminal, and a second pole of the ninth transistor is connected to a gate of the sixth transistor;
a gate of the tenth transistor is connected to the pull-down node, a first pole of the tenth transistor is connected to the power signal terminal, and a second pole of the tenth transistor is connected to the first control node.
6. A driving method of a shift register unit, which is applied to the shift register unit according to any one of claims 1 to 5; the method comprises the following steps:
in the initialization stage, an enable signal output by an enable signal end jumps from a second potential to a first potential, an initialization signal output by the initialization signal end is at the first potential, the initialization module outputs the initialization signal to a second control node, and the output control module outputs the initialization signal to an output end;
in the driving stage, the initialization signal is at a second potential, the enable signal jumps from the second potential to a first potential, an input signal output by an input signal end is the first potential, the initialization module outputs the initialization signal to the second control node, the shift module outputs a driving signal at the first potential to the first control node, and the output control module outputs the driving signal to the output end;
wherein the first potential is an effective potential.
7. The method of driving a shift register cell according to claim 6, wherein the shift module comprises: the input submodule, the output submodule, the anti-creeping submodule and the pull-down submodule are connected; the driving phase comprises:
in the charging stage, the input signal is a first potential, a first clock signal output by a first clock signal end is a first potential, and the input submodule outputs the input signal to a pull-up node under the control of the input signal and the first clock signal;
in the output stage, a second clock signal output by a second clock signal end is a first potential, the pull-up node is the first potential, the output submodule outputs the second clock signal to the first control node under the control of the pull-up node, and the anti-leakage submodule outputs the second clock signal to an anti-leakage node;
in the reset stage, a reset signal output by a reset signal end is a first potential, the input signal is a second potential, the first clock signal is the first potential, the pull-down submodule outputs the input signal to the pull-up node and outputs a power supply signal from a power supply signal end to the first control node under the control of the reset signal and the first clock signal, and the power supply signal is the second potential.
8. A gate drive circuit, comprising: at least two cascaded shift register cells according to any of claims 1 to 5;
the first control node in each shift register unit is connected with the input signal end of the next-stage shift register unit;
each shift register unit is connected with an enabling signal end, or all the shift register units are connected with the same enabling signal end; or, the gate driving circuit comprises at least two shift register groups, each shift register group comprises at least one shift register unit, and each shift register group is connected with an enable signal terminal.
9. A gate drive circuit as claimed in claim 8,
the initialization signal end of each shift register unit is connected with the second control node of the previous shift register unit;
or all the shift register units are connected with the same initialization signal end;
or, the gate driving circuit includes at least two shift register groups, each shift register group includes at least one shift register unit, each shift register group is connected to an initialization signal terminal, and the initialization signal terminal of each shift register group is connected to the initialization signal terminal of the next shift register group through the delay module.
10. A display device, characterized in that the display device comprises: a gate drive circuit as claimed in claim 8 or 9.
CN201710623527.3A 2017-07-27 2017-07-27 Shifting register unit and driving method thereof, grid driving circuit and display device CN107248390B (en)

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CN109935184A (en) * 2018-02-14 2019-06-25 京东方科技集团股份有限公司 Shift register cell, gate driving circuit, display device and driving method
CN108538233A (en) * 2018-04-20 2018-09-14 京东方科技集团股份有限公司 A kind of shift register, its driving method and gate driving circuit, display device
CN108538257A (en) * 2018-07-13 2018-09-14 京东方科技集团股份有限公司 Drive element of the grid and its driving method, gate driving circuit and display base plate
CN108630167A (en) * 2018-07-26 2018-10-09 武汉华星光电技术有限公司 A kind of GOA circuits, display panel and display device

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