TWI695362B - Light-emitting control circuit - Google Patents
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- TWI695362B TWI695362B TW108101403A TW108101403A TWI695362B TW I695362 B TWI695362 B TW I695362B TW 108101403 A TW108101403 A TW 108101403A TW 108101403 A TW108101403 A TW 108101403A TW I695362 B TWI695362 B TW I695362B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
Description
本發明係有關於一種控制電路,且特別是有關於一種發光控制電路。 The invention relates to a control circuit, and in particular to a light-emitting control circuit.
一般顯示器的畫素陣列中具有的多個畫素單元包含光電二極體,並藉由發光控制電壓控制驅動路徑上的電晶體,進一步驅動光電二極體。然而,用以提供發光控制電壓的發光控制電路容易因設計不佳,造成發光控制電壓的低態與高態不穩定,無法達到足夠低或是足夠高的電壓準位。 A plurality of pixel units in a pixel array of a general display include photodiodes, and the transistors in the driving path are controlled by the light emission control voltage to further drive the photodiodes. However, the light-emitting control circuit used to provide the light-emitting control voltage is likely to be unstable due to poor design, and the low-state and high-state of the light-emitting control voltage may not be stable enough to achieve a sufficiently low or sufficiently high voltage level.
由此可見,上述現有的方式,顯然仍存在不便與缺陷,而有待改進。為了解決上述問題,相關領域莫不費盡心思來謀求解決之道,但長久以來仍未發展出適當的解決方案。 It can be seen that the above existing methods obviously still have inconveniences and shortcomings and need to be improved. In order to solve the above-mentioned problems, the related fields must spare no effort to find a solution, but a suitable solution has not been developed for a long time.
發明內容旨在提供本揭示內容的簡化摘要,以使閱讀者對本揭示內容具備基本的理解。此發明內容並非本揭示內容的完整概述,且其用意並非在指出本發明實施例的重要/關鍵元件或界定本發明的範圍。 The summary of the present invention aims to provide a simplified summary of the disclosure so that the reader can have a basic understanding of the disclosure. This summary of the invention is not a complete overview of the disclosure, and it is not intended to point out important/critical elements of embodiments of the invention or to define the scope of the invention.
本發明內容之一目的是在提供一種發光控制電路,藉以改善先前技術的問題。 An object of the present invention is to provide a lighting control circuit to improve the problems of the prior art.
為達上述目的,本發明內容之一技術態樣係關於一種發光控制電路,包含:第一電晶體、電容、控制單元、第一放電單元、第二放電單元以及電壓提供單元。第一電晶體包含第一端、輸入控制端及第二端,其中第一端耦接於電壓源,第二端耦接於發光控制端,並用以根據輸入控制端所接收之控制電壓於發光控制端輸出發光控制電壓。電容耦接於輸入控制端以及第二端間。控制單元耦接於電壓源以及輸入控制端間,用以根據發光時脈訊號於輸入控制端輸出控制電壓。第一放電單元耦接於輸入控制端以及放電端間,並包含相串聯於第一連接節點之第一放電電晶體以及第二放電電晶體。第二放電單元耦接於第一電晶體之第二端以及放電端間,其中放電端用以接收發光時脈訊號,第一放電單元以及第二放電單元用以根據放電控制訊號以及發光時脈訊號運作,以於導通時分別對輸入控制端以及第一電晶體之第二端進行放電,並於關閉時停止放電。電壓提供單元耦接於第一連接節點,用以在發光時脈訊號使第一放電單元以及第二放電單元停止放電時,提供放電抑制電壓至第一連接節點,進一步抑制第一放電單元的放電。 To achieve the above object, one technical aspect of the present invention relates to a light emission control circuit, including: a first transistor, a capacitor, a control unit, a first discharge unit, a second discharge unit, and a voltage supply unit. The first transistor includes a first terminal, an input control terminal, and a second terminal, wherein the first terminal is coupled to the voltage source, the second terminal is coupled to the light-emitting control terminal, and is used to emit light according to the control voltage received by the input control terminal The control terminal outputs the lighting control voltage. The capacitor is coupled between the input control terminal and the second terminal. The control unit is coupled between the voltage source and the input control terminal, and is used to output a control voltage at the input control terminal according to the light-emitting clock signal. The first discharge unit is coupled between the input control terminal and the discharge terminal, and includes a first discharge transistor and a second discharge transistor connected in series to the first connection node. The second discharge unit is coupled between the second end of the first transistor and the discharge end, wherein the discharge end is used to receive the light-emission clock signal, and the first discharge unit and the second discharge unit are used according to the discharge control signal and the light-emission clock The signal operates to discharge the input control terminal and the second terminal of the first transistor when turned on, and to stop discharging when turned off. The voltage supply unit is coupled to the first connection node to provide a discharge suppression voltage to the first connection node when the light-emitting clock signal stops the first discharge unit and the second discharge unit from discharging, further suppressing the discharge of the first discharge unit .
為達上述目的,本發明內容之另一技術態樣係關於一種發光控制電路,包含:第一電晶體、電容、第二電晶體、第一放電電晶體以及第二放電電晶體。第一電晶體包含第一端、輸入控制端及第二端,其中第一端耦接於電壓源,第二端耦接於發光控制端,並用以根據輸入控制端所接收之控制電壓 於發光控制端輸出發光控制電壓。電容耦接於輸入控制端以及第二端間。第二電晶體包含第三端、控制端及第四端,其中第三端耦接於電壓源,第四端耦接於輸入控制端,並用以於控制端接收發光時脈訊號,以根據發光時脈訊號於輸入控制端輸出控制電壓。第一放電電晶體包含第五端、第一放電控制端及第六端,其中第五端耦接於輸入控制端,第六端耦接於放電端。第二放電電晶體包含第七端、第二放電控制端及第八端,其中第七端耦接於第一電晶體之第二端,第八端耦接於放電端。其中放電端用以接收發光時脈訊號,第一放電電晶體以及第二放電電晶體用以根據第一放電控制端以及第二放電控制端接收放電控制訊號,以根據放電控制訊號以及發光時脈訊號運作,以於導通時分別對輸入控制端以及第一電晶體之第二端進行放電,並於關閉時停止放電。 To achieve the above object, another technical aspect of the present disclosure relates to a light emission control circuit, including: a first transistor, a capacitor, a second transistor, a first discharge transistor, and a second discharge transistor. The first transistor includes a first terminal, an input control terminal, and a second terminal, wherein the first terminal is coupled to the voltage source, and the second terminal is coupled to the light-emitting control terminal, and is used to control the voltage received by the input control terminal The light-emission control voltage is output on the light-emission control terminal. The capacitor is coupled between the input control terminal and the second terminal. The second transistor includes a third terminal, a control terminal and a fourth terminal, wherein the third terminal is coupled to the voltage source, the fourth terminal is coupled to the input control terminal, and is used to receive the light-emitting clock signal at the control terminal to The clock signal outputs the control voltage at the input control terminal. The first discharge transistor includes a fifth terminal, a first discharge control terminal, and a sixth terminal, wherein the fifth terminal is coupled to the input control terminal, and the sixth terminal is coupled to the discharge terminal. The second discharge transistor includes a seventh end, a second discharge control end, and an eighth end, wherein the seventh end is coupled to the second end of the first transistor, and the eighth end is coupled to the discharge end. The discharge terminal is used to receive the light-emitting clock signal, and the first discharge transistor and the second discharge transistor are used to receive the discharge control signal according to the first discharge control terminal and the second discharge control terminal according to the discharge control signal and the light-emitting clock The signal operates to discharge the input control terminal and the second terminal of the first transistor when turned on, and to stop discharging when turned off.
因此,根據本發明之技術內容,本發明實施例藉由提供一種發光控制電路,藉以改善發光控制電壓在高態及低態時的穩定度,使發光控制電壓能在高態時達到夠高的準位,並在低態時達到夠低的準位。 Therefore, according to the technical content of the present invention, the embodiments of the present invention provide a light-emission control circuit to improve the stability of the light-emission control voltage in the high state and the low state, so that the light-emission control voltage can reach a sufficiently high level in the high state Level, and reach a sufficiently low level in the low state.
在參閱下文實施方式後,本發明所屬技術領域中具有通常知識者當可輕易瞭解本發明之基本精神及其他發明目的,以及本發明所採用之技術手段與實施態樣。 After referring to the embodiments below, those with ordinary knowledge in the technical field to which the present invention belongs can easily understand the basic spirit of the present invention and other inventive objectives, as well as the technical means and implementation aspects adopted by the present invention.
100‧‧‧發光控制電路 100‧‧‧Lighting control circuit
110‧‧‧控制單元 110‧‧‧Control unit
120‧‧‧第一放電單元 120‧‧‧ First discharge unit
130‧‧‧第二放電單元 130‧‧‧Second discharge unit
140‧‧‧電壓提供單元 140‧‧‧ Voltage supply unit
180‧‧‧畫素單元 180‧‧‧Pixel unit
190‧‧‧位移暫存器 190‧‧‧shift register
400‧‧‧發光控制電路 400‧‧‧Lighting control circuit
430‧‧‧第二放電單元 430‧‧‧Second discharge unit
500‧‧‧發光控制電路 500‧‧‧Lighting control circuit
540‧‧‧電壓提供單元 540‧‧‧ Voltage supply unit
600‧‧‧發光控制電路 600‧‧‧Lighting control circuit
C‧‧‧電容 C‧‧‧Capacitance
D‧‧‧第一端 D‧‧‧The first end
ECK‧‧‧發光時脈訊號 ECK‧‧‧luminous clock signal
EM‧‧‧發光控制電壓 EM‧‧‧Lighting control voltage
G‧‧‧輸入控制端 G‧‧‧Input control terminal
H、H+‧‧‧高態 H, H+‧‧‧High state
L‧‧‧低態 L‧‧‧low state
N1‧‧‧第一連接節點 N1‧‧‧ First connection node
N2‧‧‧第二連接節點 N2‧‧‧Second connection node
P1‧‧‧第一時間區間 P1‧‧‧ First time interval
P2‧‧‧第二時間區間 P2‧‧‧Second time interval
P3‧‧‧第三時間區間 P3‧‧‧ Third time interval
P4‧‧‧第四時間區間 P4‧‧‧ Fourth time interval
P5‧‧‧第五時間區間 P5‧‧‧ fifth time interval
Q‧‧‧放電控制訊號 Q‧‧‧Discharge control signal
S‧‧‧第二端 S‧‧‧The second end
T1‧‧‧第一電晶體 T1‧‧‧ First transistor
T2‧‧‧第二電晶體 T2‧‧‧second transistor
T3‧‧‧第三電晶體 T3‧‧‧third transistor
TD1‧‧‧第一放電電晶體 TD1‧‧‧The first discharge transistor
TD2‧‧‧第二放電電晶體 TD2‧‧‧Second discharge transistor
TD3‧‧‧第三放電電晶體 TD3‧‧‧The third discharge transistor
TD4‧‧‧第四放電電晶體 TD4‧‧‧The fourth discharge transistor
TDI1‧‧‧第一放電電晶體 TDI1‧‧‧First discharge transistor
TDI2‧‧‧第二放電電晶體 TDI2‧‧‧Second discharge transistor
VC‧‧‧控制電壓 VC‧‧‧Control voltage
VGH‧‧‧電壓源 VGH‧‧‧Voltage source
VI‧‧‧放電抑制電壓 VI‧‧‧Discharge suppression voltage
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下: In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the drawings are described as follows:
第1圖係依照本發明一實施例繪示一種發光控制電路的示意圖。 FIG. 1 is a schematic diagram of a lighting control circuit according to an embodiment of the invention.
第2圖係依照本發明實施例繪示一種控制波形示意圖。 FIG. 2 is a schematic diagram of a control waveform according to an embodiment of the present invention.
第3A-3E圖係依照本發明第1圖所示之實施例繪示發光控制電路的操作示意圖。 FIGS. 3A-3E are schematic diagrams illustrating the operation of the lighting control circuit according to the embodiment shown in FIG. 1 of the present invention.
第4圖係依照本發明一實施例繪示一種發光控制電路的示意圖。 FIG. 4 is a schematic diagram of a lighting control circuit according to an embodiment of the invention.
第5圖係依照本發明一實施例繪示一種發光控制電路的示意圖。 FIG. 5 is a schematic diagram of a lighting control circuit according to an embodiment of the invention.
第6圖係依照本發明一實施例繪示一種發光控制電路的示意圖。 FIG. 6 is a schematic diagram of a lighting control circuit according to an embodiment of the invention.
根據慣常的作業方式,圖中各種特徵與元件並未依比例繪製,其繪製方式是為了以最佳的方式呈現與本發明相關的具體特徵與元件。此外,在不同圖式間,以相同或相似的元件符號來指稱相似的元件/部件。 According to the usual working methods, various features and elements in the drawings are not drawn to scale. The drawing method is to present the specific features and elements related to the present invention in an optimal manner. In addition, between different drawings, the same or similar element symbols are used to refer to similar elements/components.
為了使本揭示內容的敘述更加詳盡與完備,下文針對了本發明的實施態樣與具體實施例提出了說明性的描述;但這並非實施或運用本發明具體實施例的唯一形式。實施方式中涵蓋了多個具體實施例的特徵以及用以建構與操作這些具體實施例的方法步驟與其順序。然而,亦可利用其他具體實施例來達成相同或均等的功能與步驟順序。 In order to make the description of this disclosure more detailed and complete, the following provides an illustrative description of the implementation form and specific embodiments of the present invention; however, this is not the only form for implementing or using specific embodiments of the present invention. The embodiments cover the features of multiple specific embodiments, as well as the method steps and their sequence for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equal functions and sequence of steps.
除非本說明書另有定義,此處所用的科學與技術 詞彙之含義與本發明所屬技術領域中具有通常知識者所理解與慣用的意義相同。此外,在不和上下文衝突的情形下,本說明書所用的單數名詞涵蓋該名詞的複數型;而所用的複數名詞時亦涵蓋該名詞的單數型。 Unless otherwise defined in this specification, the science and technology used here The meaning of the vocabulary is the same as the meaning understood and used by those with ordinary knowledge in the technical field to which the present invention belongs. In addition, without conflicting with the context, the singular noun used in this specification covers the plural form of the noun; and the plural noun used also covers the singular form of the noun.
另外,關於本文中所使用之「耦接」,可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,亦可指二或多個元件相互操作或動作。 In addition, as used herein, "coupling" may refer to two or more elements making direct physical or electrical contact with each other, or indirectly making physical or electrical contact with each other, or may refer to two or more elements interoperating Or action.
第1圖係依照本發明一實施例繪示一種發光控制電路100的示意圖。如圖所示,發光控制電路100包含第一電晶體T1、電容C、控制單元110、第一放電單元120、第二放電單元130以及電壓提供單元140。第一電晶體T1包含第一端D、輸入控制端G及第二端S。
FIG. 1 is a schematic diagram of a light
於連接關係上,第一電晶體T1的第一端D耦接於電壓源VGH,第二端S耦接於用以輸出發光控制電壓EM的發光控制端,輸入控制端G則用以接收控制電壓VC。電容C耦接於輸入控制端G以及第二端S間,以提供將輸入控制端G的電壓耦合至第二端S的功效。 In terms of connection, the first terminal D of the first transistor T1 is coupled to the voltage source VGH, the second terminal S is coupled to the light-emitting control terminal for outputting the light-emitting control voltage EM, and the input control terminal G is used for receiving control Voltage VC. The capacitor C is coupled between the input control terminal G and the second terminal S to provide the effect of coupling the voltage of the input control terminal G to the second terminal S.
控制單元110耦接於電壓源VGH以及輸入控制端G間,並可接收發光時脈訊號ECK。於本實施例中,控制單元110包含第二電晶體T2,此第二電晶體T2包含第一端、控制端及第二端,第二電晶體T2之第一端耦接於電壓源VGH,第二電晶體T2之控制端用以接收發光時脈訊號ECK,第二電晶體T2之第二端耦接於輸入控制端G。
The
第一放電單元120耦接於輸入控制端G以及用以接收發光時脈訊號ECK的放電端間,並包含相串聯於第一連接節點N1之第一放電電晶體TD1以及第二放電電晶體TD2。
The
第一放電電晶體TD1包含第一端、控制端及第二端,第一放電電晶體TD1之第一端耦接於輸入控制端G,第一放電電晶體TD1之控制端用以接收放電控制訊號Q,第一放電電晶體TD1之第二端耦接於第一連接節點N1。 The first discharge transistor TD1 includes a first end, a control end, and a second end. The first end of the first discharge transistor TD1 is coupled to the input control terminal G, and the control end of the first discharge transistor TD1 is used to receive discharge control In the signal Q, the second end of the first discharge transistor TD1 is coupled to the first connection node N1.
第二放電電晶體TD2包含第一端、控制端及第二端,第二放電電晶體TD2之第一端耦接於第一連接節點N1,第二放電電晶體TD2之控制端用以接收放電控制訊號Q,第二放電電晶體TD2之第二端耦接於放電端。 The second discharge transistor TD2 includes a first end, a control end and a second end. The first end of the second discharge transistor TD2 is coupled to the first connection node N1, and the control end of the second discharge transistor TD2 is used to receive the discharge In the control signal Q, the second terminal of the second discharge transistor TD2 is coupled to the discharge terminal.
第二放電單元130耦接於第一電晶體T1之第二端S以及放電端間。於本實施例中,第二放電單元130包含第三放電電晶體TD3。第三放電電晶體TD3包含第一端、控制端及第二端,第三放電電晶體TD3之第一端耦接於第二端S,第三放電電晶體TD3之控制端用以接收放電控制訊號Q,第三放電電晶體TD3之第二端耦接於放電端。
The
電壓提供單元140耦接於第一連接節點N1。電壓提供單元140用以提供放電抑制電壓VI至第一連接節點N1,進一步抑制第一放電單元120的放電。於本實施例中,電壓提供單元140包含第三電晶體T3。第三電晶體T3包含第一端、控制端及第二端,第三電晶體T3之第一端耦接於電壓源VGH,第三電晶體T3之控制端耦接於發光控制端以接收發光控制電壓EM,第三電晶體T3之第二端耦接於第一連接節點N1。
The
於一實施例中,發光控制電路100可應用於顯示面板(未繪示)中。發光控制端可耦接於顯示面板的畫素陣列中的一列畫素單元180,以輸出發光控制電壓EM控制該列畫素單元180之光電二極體的發光,放電控制訊號Q則是由對應驅動該列畫素單元180的位移暫存器190產生。
In one embodiment, the light
為使本發明實施例之發光控制電路100的操作方式易於理解,請一併參閱第2圖以及第3A-3E圖。第2圖係依照本發明實施例繪示一種控制波形示意圖。第3A-3E圖係依照本發明第1圖所示之實施例繪示發光控制電路100的操作示意圖。
In order to make the operation mode of the light
如第2圖所示,在對應上述的該列畫素單元180的一掃描時間中,包含第一時間區間P1、第二時間區間P2、第三時間區間P3、第四時間區間P4以及第五時間區間P5。以下將以第2圖搭配第3A-3E圖,詳細說明各個時間區間中,各訊號與元件的操作及狀態。
As shown in FIG. 2, a scan time corresponding to the column of
如第3A圖所示,在第一時間區間P1中,發光時脈訊號ECK為低態L且放電控制訊號Q為具有第一準位的高態H。 As shown in FIG. 3A, in the first time interval P1, the light-emission clock signal ECK is in the low state L and the discharge control signal Q is in the high state H with the first level.
此時,控制單元110包含的第二電晶體T2將由於低態L的發光時脈訊號ECK而關閉(於第3A圖中以記號X表示關閉狀態)。第一放電單元120的第一放電電晶體TD1以及第二放電電晶體TD2將由於放電控制訊號Q的高態H以及發光時脈訊號ECK的低態L導通,以對輸入控制端G進行放電,使輸入控制端G接收到低態L的控制電壓VC。
At this time, the second transistor T2 included in the
第一電晶體T1將因為輸入控制端G接收到低態L的控制電壓VC而關閉(於第3A圖中以記號X表示關閉狀態)。此時,第二放電單元130的第三放電電晶體TD3將由於放電控制訊號Q的高態H導通,以對第二端S進行放電,俾使發光控制電壓EM輸出為低態L。
The first transistor T1 will be turned off because the input control terminal G receives the control voltage VC of the low state L (the symbol X indicates the off state in FIG. 3A). At this time, the third discharge transistor TD3 of the
電壓提供單元140包含的第三電晶體T3的控制端將由於低態L的發光控制電壓EM而關閉(於第3A圖中以記號X表示關閉狀態),因此將不提供任何電壓至第一連接節點N1。第一連接節點N1將由於第二放電電晶體TD2的放電而被拉至低態L。
The control terminal of the third transistor T3 included in the
如第3B圖所示,在第二時間區間P2中,發光時脈訊號ECK為高態H且放電控制訊號Q為具有大於第一準位的第二準位的高態H+。 As shown in FIG. 3B, in the second time interval P2, the light-emission clock signal ECK is in a high state H and the discharge control signal Q is in a high state H+ having a second level greater than the first level.
此時,控制單元110包含的第二電晶體T2將由於高態H的發光時脈訊號ECK而導通。於一實施例中,電壓源VGH的電壓為高態H,因此導通的控制單元110將根據電壓源VGH的電壓對輸入控制端G進行充電,控制電壓VC將因而為高態H。第一放電單元120的第一放電電晶體TD1以及第二放電電晶體TD2雖然接收到高態H+的放電控制訊號Q,然而由於發光時脈訊號ECK為高態H,且輸入控制端G也為高態H,將使第一放電電晶體TD1的第一端(耦接於輸入控制端G)以及第二放電電晶體TD2的第二端(接收發光時脈訊號ECK)的電壓大致相同而停止放電。
At this time, the second transistor T2 included in the
第一電晶體T1將因為輸入控制端G接收到高態H
的控制電壓VC而導通,並根據電壓源VGH的電壓對第二端S耦接的發光控制端充電,而使發光控制電壓EM成為高態H。類似於第一放電單元120,第二放電單元130的第三放電電晶體TD3將由於放電控制訊號Q的高態H+導通,然而由於發光時脈訊號ECK為高態H,且第二端S也為高態H,將使第三放電電晶體TD3的第一端(耦接於第二端S)及第二端(接收發光時脈訊號ECK)的電壓大致相同而停止放電。
The first transistor T1 will receive a high state H because the input control terminal G
The control voltage VC is turned on, and the light emitting control terminal coupled to the second terminal S is charged according to the voltage of the voltage source VGH, so that the light emitting control voltage EM becomes a high state H. Similar to the
進一步地,電壓提供單元140包含的第三電晶體T3的控制端將由於高態H的發光控制電壓EM而導通,因此將對第一連接節點N1進行充電,根據電壓源VGH的電壓提供放電抑制電壓VI至第一連接節點N1。由於電壓源VGH的電壓是高態H的準位,因此放電抑制電壓VI亦將使第一連接節點N1提升為高態H。第一放電單元120的第一放電電晶體TD1以及第二放電電晶體TD2各自的第一端及第二端的電壓將因此大致相同,達到進一步抑制放電的功效。
Further, the control terminal of the third transistor T3 included in the
如第3C圖所示,在第三時間區間P3中,發光時脈訊號ECK為低態L且放電控制訊號Q為具有第一準位的高態H。 As shown in FIG. 3C, in the third time interval P3, the light-emission clock signal ECK is in the low state L and the discharge control signal Q is in the high state H with the first level.
此時,控制單元110包含的第二電晶體T2將由於低態L的發光時脈訊號ECK而關閉(於第3C圖中以記號X表示關閉狀態)。第一放電單元120的第一放電電晶體TD1以及第二放電電晶體TD2將由於放電控制訊號Q的高態H以及發光時脈訊號ECK的低態L導通,以對輸入控制端G進行放電,使輸入控制端G接收到低態L的控制電壓VC。
At this time, the second transistor T2 included in the
第一電晶體T1將因為輸入控制端G接收到低態L的控制電壓VC而關閉(於第3C圖中以記號X表示關閉狀態)。此時,第二放電單元130的第三放電電晶體TD3將由於放電控制訊號Q的高態H導通,以對第二端S進行放電,俾使發光控制電壓EM輸出低態L。
The first transistor T1 will be turned off because the input control terminal G receives the control voltage VC of the low state L (indicated by the symbol X in FIG. 3C to indicate the off state). At this time, the third discharge transistor TD3 of the
電壓提供單元140包含的第三電晶體T3的控制端將由於低態L的發光控制電壓EM而關閉(於第3C圖中以記號X表示關閉狀態),因此將不提供任何電壓至第一連接節點N1。第一連接節點N1將由於第二放電電晶體TD2的放電而被拉至低態L。
The control terminal of the third transistor T3 included in the
如第3D圖所示,在第四時間區間P4中,發光時脈訊號ECK為低態L且放電控制訊號Q為低態L。 As shown in FIG. 3D, in the fourth time interval P4, the light-emission clock signal ECK is in the low state L and the discharge control signal Q is in the low state L.
此時,控制單元110包含的第二電晶體T2將由於低態L的發光時脈訊號ECK而關閉(於第3D圖中以記號X表示關閉狀態)。第一放電單元120的第一放電電晶體TD1以及第二放電電晶體TD2將由於放電控制訊號Q的低態L以及發光時脈訊號ECK的低態L關閉(於第3D圖中以記號X表示關閉狀態),以停止對輸入控制端G進行放電。然而由於第三時間區間P3中輸入控制端G即已經是低態L,因此輸入控制端G所接收到的控制電壓VC仍為低態L。
At this time, the second transistor T2 included in the
第一電晶體T1將因為輸入控制端G接收到低態L的控制電壓VC而關閉(於第3D圖中以記號X表示關閉狀態)。然而由於第三時間區間P3中第二端S即已經是低態L,因此將於發光控制端繼續輸出低態L的發光控制電壓EM。此時,第
二放電單元130的第三放電電晶體TD3將由於放電控制訊號Q的低態L關閉(於第3D圖中以記號X表示關閉狀態),以停止對第二端S進行放電。
The first transistor T1 will be turned off because the input control terminal G receives the control voltage VC of the low state L (the symbol X indicates the off state in the 3D diagram). However, since the second terminal S is already in the low state L in the third time interval P3, the light emission control voltage EM of the low state L will continue to be output at the light emission control terminal. At this time, the first
The third discharge transistor TD3 of the
電壓提供單元140包含的第三電晶體T3的控制端將由於低態L的發光控制電壓EM而關閉(於第3D圖中以記號X表示關閉狀態),因此將不提供任何電壓至第一連接節點N1。
The control terminal of the third transistor T3 included in the
如第3E圖所示,在第五時間區間P5中,發光時脈訊號ECK為高態H且放電控制訊號Q為低態L。 As shown in FIG. 3E, in the fifth time interval P5, the light-emission clock signal ECK is in a high state H and the discharge control signal Q is in a low state L.
此時,控制單元110包含的第二電晶體T2將由於高態H的發光時脈訊號ECK而導通,以根據電壓源VGH的電壓對輸入控制端G進行充電。雖然發光時脈訊號ECK為高態H,然而第一放電單元120的第一放電電晶體TD1以及第二放電電晶體TD2將由於放電控制訊號Q的低態L關閉(於第3E圖中以記號X表示關閉狀態),以停止對輸入控制端G進行放電。因此,在一實施例中,控制電壓VC將因持續充電而為具有大於第一準位的第二準位的高態H+。
At this time, the second transistor T2 included in the
第一電晶體T1將因為輸入控制端G接收到高態H+的控制電壓VC而導通,並根據電壓源VGH的電壓對第二端S耦接的發光控制端充電,而使發光控制電壓EM成為高態H。此時,第二放電單元130的第三放電電晶體TD3將由於放電控制訊號Q的低態L關閉(於第3E圖中以記號X表示關閉狀態),以停止對第二端S進行放電。此時,控制電壓VC以及發光控制電壓EM均為高態,且第一放電單元120以及第二放電單元130均已停止放電。因此,即便在第五時間區間P5後控制單元110
接收到低態L的發光時脈訊號ECK而關閉,控制電壓VC以及發光控制電壓EM亦能持續維持在高態的準位。
The first transistor T1 will be turned on because the input control terminal G receives the control voltage VC of the high state H+, and charges the light emitting control terminal coupled to the second terminal S according to the voltage of the voltage source VGH, so that the light emitting control voltage EM becomes High state H. At this time, the third discharge transistor TD3 of the
電壓提供單元140包含的第三電晶體T3的控制端將由於高態H的發光控制電壓EM而導通,因此將根據電壓源VGH的電壓對第一連接節點N1進行充電,提供放電抑制電壓VI至第一連接節點N1。
The control terminal of the third transistor T3 included in the
因此,發光控制電路100在經過上述第一時間區間P1至第五時間區間P5的操作後,發光控制電壓EM將可輸出如第2圖所示的波形,以對相應的畫素單元的光電二極體的發光進行驅動與控制。須注意的是,第2圖所繪示的波形僅為一範例,於其他實施例中,亦可能採用其他的波形來進行驅動。
Therefore, after the operations of the first time interval P1 to the fifth time interval P5 are performed, the light
在部分技術中,第一電晶體T1的輸入控制端是以二極體的連接方式與第一端耦接,以直接由電壓源VGH控制輸入控制端,維持常開的狀態。當想要輸出低態的控制電壓VC時,可能由於第一放電單元120的放電能力不足,導致第一電晶體T1的輸入控制端無法順利關閉,進一步使發光控制電壓EM無法達到夠低的準位。
In some technologies, the input control terminal of the first transistor T1 is coupled to the first terminal in a diode connection manner, so that the input control terminal is directly controlled by the voltage source VGH to maintain the normally open state. When it is desired to output the low-state control voltage VC, the input control terminal of the first transistor T1 may not be closed smoothly due to insufficient discharge capacity of the
因此,本發明的發光控制電路100可藉由控制單元110的設置,在欲維持控制電壓VC於低態時透過發光時脈訊號ECK使控制單元110關閉,確保控制電壓VC的低態不會受到電壓源VGH的影響。這樣的配置將可進一步確保第一電晶體T1的關閉,而使發光控制電壓EM的準位可維持在夠低的狀態。
Therefore, the light-emitting
另一方面,在欲維持控制電壓VC於高態時,電壓
提供單元140可在發光時脈訊號ECK使第一放電單元120停止放電時,提供放電抑制電壓VI至第一連接節點N1,進一步抑制第一放電單元120的放電,確保控制電壓VC的高態不會受到第一放電單元120的影響,進一步使發光控制電壓EM的準位可維持在夠高的狀態。
On the other hand, when the control voltage VC is to be maintained at a high state, the voltage
The providing
在上述實施例中,第二放電單元130僅包含一個放電電晶體。然而在其他實施例中,第二放電單元130亦可比照第一放電單元120的形式設置兩個串聯的放電電晶體,並在放電電晶體間的連接點提供抑制放電的機制。
In the above embodiment, the
第4圖係依照本發明一實施例繪示一種發光控制電路400的示意圖。發光控制電路400與第1圖所示的發光控制電路100大同小異,包含第一電晶體T1、電容C、控制單元110、第一放電單元120以及電壓提供單元140,因此不再就相同的元件進行贅述。與先前的實施例相較下,本實施例的發光控制電路400包含第二放電單元430,且第二放電單元430包含相串聯於第二連接節點N2之第三放電電晶體TD3以及第四放電電晶體TD4。
FIG. 4 is a schematic diagram of a light
第三放電電晶體TD3包含第一端、控制端及第二端,第三放電電晶體TD3之第一端耦接於第二端S,第三放電電晶體TD3之控制端用以接收放電控制訊號Q,第三放電電晶體TD3之第二端耦接於第二連接節點N2。 The third discharge transistor TD3 includes a first end, a control end, and a second end. The first end of the third discharge transistor TD3 is coupled to the second end S, and the control end of the third discharge transistor TD3 is used to receive discharge control In the signal Q, the second end of the third discharge transistor TD3 is coupled to the second connection node N2.
第四放電電晶體TD4包含第一端、控制端及第二端,第四放電電晶體TD4之第一端耦接於第二連接節點N2,第四放電電晶體TD4之控制端用以接收放電控制訊號Q,第四 放電電晶體TD4之第二端耦接於放電端。 The fourth discharge transistor TD4 includes a first end, a control end, and a second end. The first end of the fourth discharge transistor TD4 is coupled to the second connection node N2, and the control end of the fourth discharge transistor TD4 is used to receive the discharge Control signal Q, fourth The second terminal of the discharge transistor TD4 is coupled to the discharge terminal.
進一步地,在本實施例中,電壓提供單元140包含的第三電晶體T3之第二端耦接於第一連接節點N1以及第二連接節點N2。
Further, in this embodiment, the second end of the third transistor T3 included in the
因此,上述電壓提供單元140提供放電抑制電壓VI至第一連接節點N1以抑制第一放電單元120的放電的機制,亦可應用於第二放電單元430中。更詳細的說,電壓提供單元140可提供放電抑制電壓VI至第二連接節點N2,確保發光控制電壓EM的高態不會受到第二放電單元430的影響,進一步使發光控制電壓EM的準位可維持在夠高的狀態。
Therefore, the above-mentioned
第5圖係依照本發明一實施例繪示一種發光控制電路500的示意圖。發光控制電路500與第1圖所示的發光控制電路100大同小異,包含第一電晶體T1、電容C、控制單元110、第一放電單元120以及第二放電單元130,因此不再就相同的元件進行贅述。與先前的實施例相較下,本實施例的發光控制電路500包含電壓提供單元540。
FIG. 5 is a schematic diagram of a light
電壓提供單元540耦接於第一連接節點N1。電壓提供單元540用以提供放電抑制電壓VI至第一連接節點N1,進一步抑制第一放電單元120的放電。於本實施例中,電壓提供單元540包含第三電晶體T3。第三電晶體T3包含第一端、控制端及第二端。第三電晶體T3包含第一端、控制端及第二端,第三電晶體T3之第一端耦接於發光控制端充電,以接收發光控制電壓EM,第三電晶體T3之控制端接收發光時脈訊號ECK,第三電晶體T3之第二端耦接於第一連接節點N1。
The
當發光控制電路500操作於例如第2圖所示的第二時間區間P2時,電壓提供單元540包含的第三電晶體T3的控制端將由於高態H的發光時脈訊號ECK而導通,因此將根據發光控制電壓EM的高態H對第一連接節點N1進行充電,亦可提供放電抑制電壓VI至第一連接節點N1,而達到抑制放電的功效。
When the light-
於又一實施例中,電壓提供單元540包含的第三電晶體T3之第一端亦可耦接於電壓源VGH,其亦可根據高態H的發光時脈訊號ECK而導通,而改由根據電壓源VGH對第一連接節點N1進行充電,提供放電抑制電壓VI至第一連接節點N1,而達到抑制放電的功效。
In yet another embodiment, the first end of the third transistor T3 included in the
需注意的是,上述是以電壓提供單元140為例,提供不同的電壓提供單元140的實現方式。於其他實施例中,控制單元110、第一放電單元120以及第二放電單元130的結構亦不限於第1圖所示的結構。於其他實施例中,此些單元亦可能藉由其他的結構達到相同的功效。
It should be noted that the foregoing uses the
第6圖係依照本發明一實施例繪示一種發光控制電路600的示意圖。發光控制電路600與第1圖所示的發光控制電路100大同小異,包含第一電晶體T1、電容C及控制單元110,因此不再就相同的元件進行贅述。與先前的實施例相較下,本實施例的發光控制電路600包含第一放電電晶體TDI1以及第二放電電晶體TDI2。
FIG. 6 is a schematic diagram of a light
第一放電電晶體TDI1包含第一端、控制端及第二端,第一放電電晶體TDI1之第一端耦接於第一電晶體T1的輸 入控制端G,第一放電電晶體TDI1之控制端用以接收放電控制訊號Q,第一放電電晶體TDI1之第二端耦接於放電端。 The first discharge transistor TDI1 includes a first end, a control end, and a second end. The first end of the first discharge transistor TDI1 is coupled to the input of the first transistor T1 Into the control terminal G, the control terminal of the first discharge transistor TDI1 is used to receive the discharge control signal Q, and the second terminal of the first discharge transistor TDI1 is coupled to the discharge terminal.
第二放電電晶體TDI2包含第一端、控制端及第二端,第二放電電晶體TDI2之第一端耦接於第一電晶體T1的第二端S,第二放電電晶體TDI2之控制端用以接收放電控制訊號Q,第二放電電晶體TDI2之第二端耦接於放電端。 The second discharge transistor TDI2 includes a first end, a control end, and a second end. The first end of the second discharge transistor TDI2 is coupled to the second end S of the first transistor T1, and the control of the second discharge transistor TDI2 The terminal is used to receive the discharge control signal Q, and the second terminal of the second discharge transistor TDI2 is coupled to the discharge terminal.
因此,相較於第1圖的發光控制電路100,發光控制電路600並未包含電壓提供單元,因此也僅在第一電晶體T1的輸入控制端G與第二端S到放電端間各設置一個電晶體進行放電。因此,在本實施例中,這樣的配置方式將僅有藉由控制單元110維持控制電壓VC在低態時的穩定度,進而使發光控制電壓EM得以維持在夠低的準位的機制。
Therefore, compared to the light
由上述本發明實施方式可知,應用本發明具有下列優點。本發明實施例藉由提供一種發光控制電路100,藉以改善發光控制電壓EM在高態及低態時的穩定度,使發光控制電壓EM能在高態時達到夠高的準位,並在低態時達到夠低的準位。
It can be known from the above embodiments of the present invention that the application of the present invention has the following advantages. The embodiment of the present invention improves the stability of the light emission control voltage EM in the high state and the low state by providing a light
雖然上文實施方式中揭露了本發明的具體實施例,然其並非用以限定本發明,本發明所屬技術領域中具有通常知識者,在不悖離本發明之原理與精神的情形下,當可對其進行各種更動與修飾,因此本發明之保護範圍當以附隨申請專利範圍所界定者為準。 Although the above embodiments disclose specific examples of the present invention, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs, without departing from the principle and spirit of the present invention, should Various changes and modifications can be made to it, so the scope of protection of the present invention shall be defined by the scope of the accompanying patent application.
100‧‧‧發光控制電路 100‧‧‧Lighting control circuit
110‧‧‧控制單元 110‧‧‧Control unit
120‧‧‧第一放電單元 120‧‧‧ First discharge unit
130‧‧‧第二放電單元 130‧‧‧Second discharge unit
140‧‧‧電壓提供單元 140‧‧‧ Voltage supply unit
180‧‧‧畫素單元 180‧‧‧Pixel unit
190‧‧‧位移暫存器 190‧‧‧shift register
C‧‧‧電容 C‧‧‧Capacitance
D‧‧‧第一端 D‧‧‧The first end
ECK‧‧‧發光時脈訊號 ECK‧‧‧luminous clock signal
EM‧‧‧發光控制電壓 EM‧‧‧Lighting control voltage
G‧‧‧輸入控制端 G‧‧‧Input control terminal
N1‧‧‧第一連接節點 N1‧‧‧ First connection node
Q‧‧‧放電控制訊號 Q‧‧‧Discharge control signal
S‧‧‧第二端 S‧‧‧The second end
T1‧‧‧第一電晶體 T1‧‧‧ First transistor
T2‧‧‧第二電晶體 T2‧‧‧second transistor
T3‧‧‧第三電晶體 T3‧‧‧third transistor
TD1‧‧‧第一放電電晶體 TD1‧‧‧The first discharge transistor
TD2‧‧‧第二放電電晶體 TD2‧‧‧Second discharge transistor
TD3‧‧‧第三放電電晶體 TD3‧‧‧The third discharge transistor
VC‧‧‧控制電壓 VC‧‧‧Control voltage
VGH‧‧‧電壓源 VGH‧‧‧Voltage source
VI‧‧‧放電抑制電壓 VI‧‧‧Discharge suppression voltage
Claims (11)
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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CN108831385A (en) * | 2018-06-25 | 2018-11-16 | 上海天马有机发光显示技术有限公司 | Scan drive circuit, display device and driving method |
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CN108831385A (en) * | 2018-06-25 | 2018-11-16 | 上海天马有机发光显示技术有限公司 | Scan drive circuit, display device and driving method |
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