CN111833820A - Grid scanning driving circuit, driving method and display panel - Google Patents
Grid scanning driving circuit, driving method and display panel Download PDFInfo
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- CN111833820A CN111833820A CN201910320334.XA CN201910320334A CN111833820A CN 111833820 A CN111833820 A CN 111833820A CN 201910320334 A CN201910320334 A CN 201910320334A CN 111833820 A CN111833820 A CN 111833820A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
Abstract
According to the gate scanning driving circuit, the driving method and the display panel, the first output voltage stabilizing transistor is arranged in the gate scanning driving circuit and can be used for controlling the connection or disconnection of the seventh transistor which outputs high level to the signal output line, so that when the eighth transistor is connected and outputs low level to the signal output line, the seventh transistor is kept disconnected, the signal output line can stably output low level, and the stability of output signals is improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a gate scan driving circuit, a driving method, and a display panel.
Background
An Organic Light Emitting Diode (OLED) Display panel has many advantages, such as self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of approximately 180 °, a wide temperature range, and capability of implementing flexible Display and large-area full-color Display, and is considered as a Display panel with the most potential development in the industry. The gate scan driving circuit can maintain stable and effective operation, and is a key point of consideration for improving the performance of the display panel.
In a conventional gate scan driving circuit, a transistor continuously operates for a long time or under different environments (voltage, current, temperature change, and the like), so that characteristics of the transistor change. Most commonly, the leakage current is increased due to the shift of the threshold voltage or the deterioration of the characteristics of the transistor connected to the signal output line, which may cause the output voltage of the gate scan driving circuit to be unstable and may easily cause the output signal to be invalid due to the increased leakage current or the shift of the threshold voltage in the positive direction when the gate scan driving circuit outputs a low voltage for controlling the light emitting device to emit light.
Disclosure of Invention
In view of the above-mentioned problems, the present disclosure provides a gate scan driving circuit, a driving method, and a display panel.
In one aspect, the present disclosure provides a gate scan driving circuit, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a seventh transistor, an eighth transistor, and a first output voltage-stabilizing transistor;
one end of the first transistor is connected with a low potential, and the other end of the first transistor is respectively connected with one end of the third transistor, the control end of the fourth transistor and the control end of the seventh transistor; the control end of the first transistor is connected with a forward clock signal;
one end of the second transistor is connected with the initial input signal, and the other end of the second transistor is respectively connected with the control end of the third transistor, one end of the fifth transistor and the control end of the eighth transistor; the control end of the second transistor is connected with a forward clock signal;
the other end of the third transistor is connected with a forward clock signal; one end of the fourth transistor is connected with a high potential, and the other end of the fourth transistor is connected with the other end of the fifth transistor; the control end of the fifth transistor is connected with a reverse clock signal; one end of the seventh transistor is connected with a high potential, and the other end of the seventh transistor is connected with an output signal line; one end of the eighth transistor is connected with the reverse clock signal, and the other end of the eighth transistor is connected with the output signal line;
one end of the first output voltage-stabilizing transistor is connected with the control end of the seventh transistor, the other end of the first output voltage-stabilizing transistor is connected with a high potential, and the control end of the first output voltage-stabilizing transistor is connected with an output signal wire; wherein when the output signal line outputs a low level, the first output regulator transistor is turned on to keep the seventh transistor turned off;
the forward clock signal and the reverse clock signal are mutually reverse phase signals.
In an optional other example, the gate scan driving circuit further includes: a second output regulator transistor;
one end of the second output voltage stabilizing transistor is connected with the control end of the eighth transistor, the other end of the second output voltage stabilizing transistor is connected with a low potential, and the control end of the second output voltage stabilizing transistor is connected with the output signal wire; wherein when the output signal line outputs a low level, the second output regulator transistor is turned on to keep the eighth transistor turned on.
In other examples of the alternatives, the forward clock signal, the reverse clock signal, and the initial input signal are all generated by an external timing controller.
In other examples of the alternatives, the gate scan driving circuit further includes a sixth transistor;
one end of the sixth transistor is connected with one end of the second transistor, the other end of the sixth transistor is connected with the control end of the eighth transistor, and the control end of the sixth transistor is connected with a low potential.
In other optional examples, the gate scan driving circuit further includes: a first capacitor;
and one end of the first capacitor is connected with the control end of the seventh transistor, and the other end of the first capacitor is connected with the output signal line.
In an optional other example, the gate scan driving circuit further includes: a second capacitor;
and one end of the second capacitor is connected with the control end of the eighth transistor, and the other end of the second capacitor is connected with the output signal line.
In other optional examples, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are each at least one of a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, and an amorphous silicon thin film transistor.
In another aspect, the present disclosure provides a driving method of a gate scan driving circuit, the driving method being applied to the gate scan driving circuit as described in any one of the above, the driving method comprising:
in the first stage, the forward clock signal is at low level, the reverse clock signal is at high level, and the initial input signal is at low level; the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor and the eighth transistor are turned on, the fifth transistor and the first output voltage stabilizing transistor are turned off, and the output signal line outputs high level;
in the second stage, the forward clock signal is at a high level, the reverse clock signal is at a low level, and the initial input signal is at a high level; the third transistor, the fifth transistor, the eighth transistor and the first output voltage-stabilizing transistor are switched on, the first transistor, the second transistor, the fourth transistor and the seventh transistor are switched off, and the output signal line outputs low level;
in the third stage, the forward clock signal is at low level, the reverse clock signal is at high level, and the initial input signal is at high level; the first transistor, the second transistor, the third transistor, the fourth transistor and the seventh transistor are turned on, the fifth transistor, the sixth transistor, the eighth transistor and the first output voltage stabilizing transistor are turned off, and the output signal line outputs high level;
in the fourth stage, the forward clock signal is at high level, the reverse clock signal is at low level, and the initial input signal is at high level; the fourth transistor, the fifth transistor and the seventh transistor are turned on, the first transistor, the second transistor, the third transistor, the eighth transistor and the first output voltage stabilizing transistor are turned off, and the output signal line outputs high level.
When the gate scan driving circuit further includes a second output regulator transistor, the driving method further includes:
in the second stage, the second output regulator transistor is turned on.
In a final aspect, the present disclosure provides a display panel, including the gate scan driving circuit as described in any one of the preceding claims.
According to the gate scanning driving circuit, the driving method and the display panel, the first output voltage stabilizing transistor is arranged in the gate scanning driving circuit and can be used for controlling the connection or disconnection of the seventh transistor which outputs high level to the signal output line, so that when the eighth transistor is connected and outputs low level to the signal output line, the seventh transistor is kept disconnected, the signal output line can stably output low level, and the stability of output signals is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate examples consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic structural diagram of a conventional gate scan driving circuit;
fig. 2 is a schematic structural diagram of a gate scan driving circuit provided in an example of the present disclosure;
fig. 3 is a schematic diagram of a driving timing sequence of a gate scan driving circuit according to an example of the present disclosure;
fig. 4 is a schematic structural diagram of another gate scan driving circuit provided in the examples of the present disclosure;
fig. 5 is a schematic structural diagram of another gate scan driving circuit provided in the examples of the present disclosure;
fig. 6 is a schematic structural diagram of another gate scan driving circuit provided in an example of the present disclosure;
FIG. 7 is a simulation diagram of the driving timing diagram shown in FIG. 3.
Explicit examples of the present disclosure have been shown by the above figures and will be described in more detail later. These drawings and written description are not intended to limit the scope of the disclosed concepts in any manner, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific examples.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The examples described in the following exemplary examples are not intended to represent all examples consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
Examples of the present disclosure may be described below with reference to the accompanying drawings. Accordingly, those of ordinary skill in the art will recognize that various changes, equivalents, and/or substitutions can be made to the examples described herein without departing from the scope and spirit of the present disclosure. In the description of the drawings, like components may be denoted by like reference numerals.
In the present disclosure, the expressions "having", "may have", "include" and "contain", or "may include" and "may contain" may be used herein to indicate the presence of corresponding features (e.g., elements such as values, functions, operations, or components), but do not exclude the presence of additional features.
In the present disclosure, the expression "a or B", "at least one of a and/or B", or "one or more of a and/or B", etc., as used herein, may include all combinations of one or more of the associated listed items. For example, the terms "a or B", "at least one of a and B", "at least one of a or B" may refer to all of the following: (1) comprises at least one A, (2) comprises at least one B, (3) comprises at least one A and at least one B.
The terminology used in the present disclosure is for the purpose of describing examples of the present disclosure, and is not intended to limit the scope of the present disclosure. Unless otherwise indicated, terms in the singular may include the plural. Unless otherwise defined herein, all terms (including technical or scientific terms) used herein may have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, which are defined or used commonly in dictionaries, should also be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the context of each example of the present disclosure. In some cases, even if a term is a term defined in the present disclosure, the term should not be construed as excluding examples of the present disclosure.
An Organic Light Emitting Diode (OLED) Display panel has many advantages, such as self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of approximately 180 °, a wide temperature range, and capability of implementing flexible Display and large-area full-color Display, and is considered as a Display panel with the most potential development in the industry. The gate scan driving circuit can maintain stable and effective operation, and is a key point of consideration for improving the performance of the display panel.
Fig. 1 is a schematic structural diagram of a conventional gate scan driving circuit, and as shown in fig. 1, the gate scan driving circuit includes transistors T1, T2, T3, T4, T5, T6, T7, and T8, and capacitors C1 and C2.
The control end of the transistor T1 is connected to the forward clock signal CK, one end of the transistor is connected to the low level VL, and the other end of the transistor is connected to one end of the capacitor C1, the control end of the transistor T5 and one end of the transistor T3 respectively;
one end of the transistor T2 is connected to one end of the transistor T6, one end of the transistor T5, and a control end of the transistor T3, respectively, and the other end is connected to the initial input signal GSTV, and the control end thereof is connected to the forward clock signal CK;
the other end of the transistor T3 is connected to the forward clock signal CK;
the control end of the transistor T4 is connected to a low level, and the other end of the transistor T4 is connected with one end of the capacitor C1 and the control end of the transistor T8;
one end of the transistor T5 is connected to the high level VH, and the other end is connected to the other end of the transistor T6;
the control end of the transistor T6 is connected with a reverse clock signal CB;
one end of the transistor T7 is connected to the high level VH, and the other end is connected to a signal output line;
one end of the transistor T8 is connected with a reverse clock signal CB, and the other end is connected with a signal output line;
the other end of the capacitor C1 is connected to the other end of the transistor T8, and the other end of the capacitor C2 is connected to one end of the transistor T7.
Each of the transistors is a P-type transistor, i.e., the transistor is turned on when the control terminal is at a low level.
In a stage where the conventional gate scan control circuit outputs a low level, the initial input signal GSTV is at a high level, the forward clock signal CK is at a high level, and the reverse clock signal CB is at a low level.
At this time, the transistors T3, T4, T6, and T8 are turned on, the transistors T1, T2, T5, and T7 are turned off, and the output level of the output signal line coincides with the other end of T8, that is, the level of the inverted clock signal, due to the turning on of T8 and the turning off of T7. In other words, at this time, the output signal line outputs a low level.
However, as described above, the transistor characteristics change when the transistor is continuously operated for a long time or under different environments (voltage, current, temperature change, and the like). The most common is that the transistor T7 connected to the signal output line has a large leakage current due to a shift in threshold voltage or a deterioration in characteristics, and the leakage current becomes large or the threshold voltage shifts in the positive direction.
When the threshold voltage of the transistor T7 shifts to the positive direction, it may turn on to form a path at the stage when the gate scan control circuit outputs a low level. At this time, the output level of the output signal line will no longer coincide with the low level of the output of the inverted clock signal, but may be between the high level and the low level. That is, in this case, the voltage output by the gate scan driving circuit is unstable, and the output signal is liable to be invalid.
In view of the above problems, the present disclosure provides a gate scan driving circuit, a driving method, and a display panel, so that a transistor for providing a high level to a signal output line, that is, a seventh transistor in the present disclosure, is maintained in an off state when the gate scan driving circuit outputs a low level by providing a first output voltage stabilization transistor, thereby ensuring that the signal output line can output a stable low level.
For convenience of description, without specific explanation, the transistors referred to in each example provided in the present disclosure will be P-type field effect transistors, i.e., PMOS transistors, and thus, in each example provided in the present disclosure, when the control terminal of each transistor is inputted with a low level, the transistor will be turned on, and vice versa.
It should be noted that each transistor in the gate scan driving circuit based on the present disclosure may also adopt a field effect transistor opposite to the transistor, and the level of each signal input to the gate scan driving circuit should be adjusted accordingly, which has a similar principle, and the present disclosure will not be repeated in the case that each transistor adopts an N-type field effect transistor.
Fig. 2 is a schematic structural diagram of a gate scan driving circuit according to an example of the present disclosure, and as shown in fig. 2, the gate scan driving circuit includes:
a gate scan driving circuit body and a first output stabilization transistor P1;
wherein, the gate scanning drive circuit body includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, an eighth transistor T8, and a first output regulator transistor P1;
one end of the first transistor T1 is connected to the low potential VL, and the other end of the first transistor T1 is respectively connected to one end of the third transistor T3, the control end of the fourth transistor T4, and the control end of the seventh transistor T7; the control end of the first transistor T1 is connected with a positive clock signal CK;
one end of the second transistor T2 is connected to the initial input signal STV, and the other end is connected to the control end of the third transistor T3, one end of the fifth transistor T5, and the control end of the eighth transistor T8, respectively; the control end of the second transistor T2 is connected with a positive clock signal CK;
the other end of the third transistor T3 is connected to the forward clock signal CK; one end of the fourth transistor T4 is connected to the high potential VH, and the other end is connected to the other end of the fifth transistor T5; the control terminal of the fifth transistor T5 is connected to the inverted clock signal CKB; one end of the seventh transistor T7 is connected to the high potential VH, and the other end is connected to the output signal line OUT; one end of the eighth transistor T8 is connected to the inverted clock signal CKB, and the other end is connected to the output signal line OUT;
one end of the first output regulator transistor P1 is connected to the control end of the seventh transistor T7, the other end is connected to the high potential VH, and the control end of the first output regulator transistor P1 is connected to the output signal line OUT; wherein, when the output signal line OUT outputs a low level, the first output regulator transistor P1 is turned on to keep the seventh transistor T7 turned off;
the forward clock signal CK and the reverse clock signal CKB are inverse signals.
The gate scan driving circuit is controlled to be in different stages by level variation of each signal, and the stages include, but are not limited to, a first stage, a second stage, a third stage, and a fourth stage. It should be noted that the gate scan driving circuit can provide a scan driving signal to the pixel unit connected thereto. Generally, when the gate scan driving circuit outputs a low level signal and does not apply another control signal to the pixel unit, the pixel unit will be in a light emitting state, whereas when the gate scan driving circuit outputs a high level signal and does not apply another control signal to the pixel unit, the pixel unit will be in a non-light emitting state. Accordingly, in the present disclosure, when the gate scan driving circuit is in the second phase, it may provide the pixel unit with a low-level scan driving signal to enter the light emitting phase.
Fig. 3 is a schematic diagram of a driving timing sequence of a gate scan driving circuit according to an example of the present disclosure, and fig. 7 is a schematic diagram of a simulation of the driving timing sequence shown in fig. 3, as shown in fig. 3 and fig. 7, when the gate scan driving circuit according to an example of the present disclosure is in a second stage, states of signals therein are as follows: the initial input signal STV is high, the forward clock signal CK is high, and the reverse clock signal CKB is low.
Specifically, in the example of the present disclosure, when the gate scan driving circuit is in the second phase, the forward clock signal CK is at a high level, the reverse clock signal CKB is at a low level, and the initial input signal STV is at a high level. At this time, the third transistor T3 is still turned on, the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned off by the forward clock signal CK, the fifth transistor T5 and the eighth transistor T8 are turned on by the reverse clock signal CKB, and the output signal line OUT outputs a low level to turn on the first output regulator transistor P1.
Therefore, in the disclosed example, the turned-on first output regulator transistor P1 keeps the level of the node a consistent with the high level VH, so that the control terminal of the seventh transistor T7 is in a stable high state, and the seventh transistor T7 is stable in a turned-off state, i.e., the gate scan driving circuit outputs a stable low level in the second stage, thereby avoiding the problem of invalid output signals.
In addition, the forward clock signal CK, the reverse clock signal CKB, and the initial input signal STV in the disclosed example are all generated by an external timing controller.
In addition, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 in the disclosed example are each at least one of a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, and an amorphous silicon thin film transistor.
On the basis of the above example, in order to further improve the gate scan driving circuit provided by the present disclosure, fig. 4 is a schematic structural diagram of another gate scan driving circuit provided by the example of the present disclosure.
As shown in fig. 4, the gate scan driving circuit includes a gate scan driving circuit body, a first output stabilization transistor P1 and a second output stabilization transistor P2.
The specific structure of the gate scan driving circuit body and the first output stabilizing transistor P1 is similar to the previous examples, and is not repeated here. Unlike the previous example, the gate scan driving circuit of this example further includes a second output stabilization transistor P2, one end of the second output stabilization transistor P2 is connected to the control terminal of the eighth transistor T8, the other end is connected to the low potential VL, and the control terminal of the second output stabilization transistor P2 is connected to the output signal line OUT.
In the gate scan driving circuit provided in this example, in conjunction with the timing diagram shown in fig. 3, when it is in the second phase, the forward clock signal CK is at a high level, the reverse clock signal CKB is at a low level, and the initial input signal STV is at a high level.
At this time, similar to the previous example, the third transistor T3 is still turned on, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off by the forward clock signal CK, the fifth transistor T5 and the eighth transistor T8 are turned on by the reverse clock signal CKB, and the output signal line OUT outputs a low level to turn on the first output regulator transistor P1.
Unlike the previous example, since the output signal line OUT outputs a low level, the second output regulator transistor P2 having its control terminal connected to the output signal line will also be turned on, and the level of the node B will be kept coincident with the low level VL. At this time, since the control terminal of the eighth transistor P2 has the same level as the node B, the eighth transistor P2 thereof is turned on continuously, and the output signal line OUT outputs a low level.
That is, in the gate scan driving circuit shown in fig. 4, in the case where it is in the second stage where the output signal line OUT outputs a low level, the first output regulator transistor P1 and the second output regulator transistor P2 are both turned on, and accordingly, the level of the node a is pulled high to make the seventh transistor T7 continuously turned off, and the level of the node B is pulled low to a low level to make the eighth transistor T8 continuously turned on, so that the output signal line OUT stably outputs a low level to avoid the output signal from being invalid.
In order to further improve the signal stability, on the basis of the example shown in fig. 2 or fig. 4, the gate scan driving circuit further includes: and a sixth transistor T6.
Fig. 5 is a schematic structural diagram of another gate scan driving circuit provided in the example of the present disclosure, and it should be noted that fig. 5 is obtained on the basis of the structure shown in fig. 4. In other examples, the sixth transistor T6 may be added to the circuit structure shown in fig. 2, which is not described in detail in this example.
In this example, the other end of the second transistor T2 is no longer directly connected to the control terminal of the eighth transistor T8, but is connected through the sixth transistor T6. That is, as shown in fig. 5, in this example, one end of the sixth transistor T6 is connected to the other end of the second transistor T2, the other end of the sixth transistor T6 is connected to the control end of the eighth transistor T8, and the control end of the sixth transistor T6 is connected to the low potential VL.
It should be noted that, unlike the previous example, the gate scan driving circuit provided in this example is further provided with a sixth transistor T6, and generally, the control terminal thereof is connected to the low potential VL and is turned on. In other words, the sixth transistor T6 can be regarded as a unidirectional conducting tube, so that the signal flows into the control terminal of the eighth transistor T8 only from one terminal of the second transistor T2 without signal backflow, and the signal stability in the whole gate scan driving circuit is further improved.
On the basis of any of the examples shown in fig. 2, 4 and 5, in order to further stabilize the on or off operation state of the seventh transistor T7 and/or the eighth transistor T8, the gate scan driving circuit further includes: a first capacitance C1, and/or a second capacitance C2.
To facilitate the description of the scheme provided in this example, fig. 6 is a schematic structural diagram of another gate scan driving circuit provided in this example of the disclosure, which is constructed on the basis of fig. 4.
It should be noted that, the gate scan driving circuit shown in fig. 6 is described by taking an example of simultaneously including the first capacitor C1 and the second capacitor C2, and in other optional examples, only the first capacitor C1 may be included, or only the second capacitor C2 may be included.
The gate scan driving circuit shown in fig. 6 includes a gate scan driving circuit body, a first output stabilization transistor P1 and a second output stabilization transistor P2, a first capacitor C1 and a second capacitor C2.
The specific structure and the corresponding principle of the gate scan driving circuit body, the first output stabilization transistor P1 and the second output stabilization transistor P2 are similar to those of the example shown in fig. 4, and are not repeated herein.
Unlike the previous example, the gate scan driving circuit of this example further includes a first capacitor C1 and a second capacitor C2.
One end of the first capacitor C1 is connected to the control end of the seventh transistor T7, and the other end is connected to the output signal line OUT; one end of the second capacitor C2 is connected to the control terminal of the eighth transistor T8, and the other end is connected to the output signal line OUT.
In the first stage, the first capacitor C1 stores energy when the voltage at the node a is at a low level, that is, stores energy when CK is at a low level, so that the stored energy is released to the control terminal of the seventh transistor T7 in the second stage, and further the T7 is kept in the off state in the second stage, in combination with the timing diagram of fig. 3 and the simulation diagram of fig. 7. Similarly, the second capacitor C2 can be used to maintain the absolute voltage value of the node B, wherein, in conjunction with the timing chart of fig. 3, the voltage of the node B is charged to a low level VL in the first phase, and the voltage of the node B is charged to a low level 3 times as low as the signal output line OUT in the second phase, so that the T8 further maintains the on state in the second phase.
Therefore, by the arrangement of the first capacitor C1 and the second capacitor C2, the gate scan driving circuit can better maintain a stable signal output state.
The present disclosure also provides a driving method based on any one of the foregoing gate scanning driving circuits, including the following steps:
and S101, controlling the gate scanning driving circuit to be in a first stage.
Specifically, in the first stage, the forward clock signal CK is at a low level, the reverse clock signal CKB is at a high level, and the initial input signal STV is at a low level, in conjunction with the timing diagram shown in fig. 3 and the simulation diagram shown in fig. 7.
In the above signal state, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned on, the fifth transistor T5 and the first output regulator transistor P1 are turned off, and the output signal line OUT outputs a high level.
In this state, the gate scan driver circuit outputs a high level to the pixel cell through the output signal line OUT, and the pixel cell does not emit light.
And step S102, controlling the grid scanning driving circuit to be in a second stage.
Specifically, in conjunction with the timing diagram shown in fig. 3, in the second stage, the forward clock signal CK is at a high level, the reverse clock signal CKB is at a low level, and the initial input signal STV is at a high level.
In the above signal state, the third transistor T3, the fifth transistor T5, the eighth transistor T8, and the first output regulator transistor P1 are turned on, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off, and the output signal line OUT outputs a low level.
In this state, the gate scan driving circuit outputs a low level to the pixel unit through the output signal line OUT, and the pixel unit emits light.
Further, the turned-on first output regulator transistor P1 keeps the level of the node a consistent with the high level VH, so that the control terminal of the seventh transistor T7 is in a stable high state, and the seventh transistor T7 is in a stable off state, i.e., the gate scan driving circuit outputs a stable low level in the second stage, thereby avoiding the problem of invalid output signals.
And step S103, controlling the gate scanning driving circuit to be in a third stage.
Specifically, in the third stage, the forward clock signal CK is at a low level, the reverse clock signal CKB is at a high level, and the initial input signal STV is at a high level, in conjunction with the timing diagram shown in fig. 3 and the simulation diagram shown in fig. 7.
In the above signal states, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned on, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the first output regulator transistor P1 are turned off, and the output signal line OUT outputs a high level.
In this state, the gate scan driver circuit outputs a high level to the pixel unit through the output signal line OUT, and the pixel unit does not emit light.
And step S103, controlling the gate scanning driving circuit to be in a fourth stage.
Specifically, in conjunction with the timing diagram shown in fig. 3, in the fourth stage, the forward clock signal CK is at a high level, the reverse clock signal CKB is at a low level, and the initial input signal STV is at a high level.
In this signal state, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned on, the first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8, and the first output regulator transistor P1 are turned off, and the output signal line OUT outputs a high level.
In this state, the gate scan driver circuit outputs a high level to the pixel unit through the output signal line OUT, and the pixel unit does not emit light.
In particular, when the gate scan driving circuit further includes the second output regulator transistor P2, the driving method further includes:
in the second stage, the second output regulator transistor P2 is turned on.
It should be noted that the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, the eighth transistor, the first output regulator transistor, and the second output regulator transistor are all P-type field effect transistors.
In other optional examples, the transistors may also be N-type field effect transistors, and signals input to the N-type field effect transistors need to be adjusted accordingly, which is not described herein again.
In a final aspect, the present disclosure provides a display panel comprising the gate scan driving circuit as described in any one of the preceding claims.
Although illustrative examples of the present disclosure are described herein, the present disclosure is not limited to the various preferred examples described herein, but includes any and all examples, modifications, omissions, combinations (e.g., of aspects across various examples), alterations, and/or substitutions having equivalent elements as would be appreciated by one of ordinary skill in the art in light of the present disclosure. The limitations in the claims are to be interpreted broadly based on the terms used in the claims and not limited to examples described in the specification or during the prosecution of the application, which examples are to be construed as non-exclusive. For example, in the present disclosure, the term "preferably" is non-exclusive and means "preferably, but not limited to". In the present disclosure and during the course of this application, means-plus-function or step-plus-function limitations will apply only to the following cases, for a particular claim limitation, in which all of the following conditions exist: a) the "means for.. or" step for.. is expressly stated; b) the corresponding functions are clearly stated; and c) no structure, material, or acts for supporting the structure are recited. In the present disclosure and during the course of the present application, the term "present disclosure" or "invention" may be used to denote one or more aspects of the present disclosure. The terms present disclosure or invention should not be improperly interpreted as a limitation, should not be improperly interpreted as applying all aspects or examples (i.e., it should be understood that the present disclosure has multiple aspects and examples), and should not be improperly interpreted as limiting the scope of the application or claims. In the present disclosure and during the course of the present application, the term "example" may be used to describe any aspect, feature, process or step, any combination thereof and/or any portion thereof, etc. In some examples, various examples may include overlapping features. In the present disclosure and during the course of the present application, the following shorthand terms may be utilized: an "e.g." indicating "for example" and an "NB" indicating "attention".
Finally, it should be noted that: the above examples are only intended to illustrate the technical solutions of the present disclosure, not to limit them; while the present disclosure has been described in detail with reference to the foregoing examples, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing examples can still be modified, or some or all of the technical features can be equivalently replaced; such modifications and substitutions do not depart from the scope of the exemplary embodiments of the present disclosure.
Claims (10)
1. A gate scan driving circuit, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a seventh transistor, an eighth transistor, and a first output voltage-stabilizing transistor;
one end of the first transistor is connected with a low potential, and the other end of the first transistor is respectively connected with one end of the third transistor, the control end of the fourth transistor and the control end of the seventh transistor; the control end of the first transistor is connected with a forward clock signal;
one end of the second transistor is connected with the initial input signal, and the other end of the second transistor is respectively connected with the control end of the third transistor, one end of the fifth transistor and the control end of the eighth transistor; the control end of the second transistor is connected with a forward clock signal;
the other end of the third transistor is connected with a forward clock signal; one end of the fourth transistor is connected with a high potential, and the other end of the fourth transistor is connected with the other end of the fifth transistor; the control end of the fifth transistor is connected with a reverse clock signal; one end of the seventh transistor is connected with a high potential, and the other end of the seventh transistor is connected with an output signal line; one end of the eighth transistor is connected with the reverse clock signal, and the other end of the eighth transistor is connected with the output signal line;
one end of the first output voltage-stabilizing transistor is connected with the control end of the seventh transistor, the other end of the first output voltage-stabilizing transistor is connected with a high potential, and the control end of the first output voltage-stabilizing transistor is connected with an output signal wire; wherein when the output signal line outputs a low level, the first output regulator transistor is turned on to keep the seventh transistor turned off;
the forward clock signal and the reverse clock signal are mutually reverse phase signals.
2. The gate scan driving circuit according to claim 1, further comprising: a second output regulator transistor;
one end of the second output voltage stabilizing transistor is connected with the control end of the eighth transistor, the other end of the second output voltage stabilizing transistor is connected with a low potential, and the control end of the second output voltage stabilizing transistor is connected with the output signal wire; wherein when the output signal line outputs a low level, the second output regulator transistor is turned on to keep the eighth transistor turned on.
3. The gate scan driving circuit of claim 1, wherein the forward clock signal, the reverse clock signal and the initial input signal are all generated by an external timing controller.
4. The gate scan driving circuit according to claim 1, further comprising: a sixth transistor;
one end of the sixth transistor is connected with one end of the second transistor, the other end of the sixth transistor is connected with the control end of the eighth transistor, and the control end of the sixth transistor is connected with a low potential.
5. The gate scan driving circuit according to any one of claims 1 to 4, further comprising: a first capacitor;
and one end of the first capacitor is connected with the control end of the seventh transistor, and the other end of the first capacitor is connected with the output signal line.
6. The gate scan driving circuit according to any one of claims 1 to 4, further comprising: a second capacitor;
and one end of the second capacitor is connected with the control end of the eighth transistor, and the other end of the second capacitor is connected with the output signal line.
7. The gate scan driving circuit according to any one of claims 1 to 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are each at least one of a low temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, and an amorphous silicon thin film transistor.
8. A driving method of a gate scan driving circuit, the driving method being applied to the gate scan driving circuit according to any one of claims 1 to 7, the driving method comprising:
in the first stage, the forward clock signal is at low level, the reverse clock signal is at high level, and the initial input signal is at low level; the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor and the eighth transistor are turned on, the fifth transistor and the first output voltage stabilizing transistor are turned off, and the output signal line outputs high level;
in the second stage, the forward clock signal is at a high level, the reverse clock signal is at a low level, and the initial input signal is at a high level; the third transistor, the fifth transistor, the eighth transistor and the first output voltage-stabilizing transistor are switched on, the first transistor, the second transistor, the fourth transistor and the seventh transistor are switched off, and the output signal line outputs low level;
in the third stage, the forward clock signal is at low level, the reverse clock signal is at high level, and the initial input signal is at high level; the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor and the eighth transistor are switched on, the fifth transistor and the first output voltage-stabilizing transistor are switched off, and the output signal line outputs high level;
in the fourth stage, the forward clock signal is at high level, the reverse clock signal is at low level, and the initial input signal is at high level; the fourth transistor, the fifth transistor and the seventh transistor are turned on, the first transistor, the second transistor, the third transistor, the eighth transistor and the first output voltage stabilizing transistor are turned off, and the output signal line outputs high level.
9. The driving method according to claim 8, wherein when the gate scan driving circuit further includes a second output regulator transistor, the driving method further includes:
in the second stage, the second output regulator transistor is turned on.
10. A display panel comprising the gate scan driver circuit according to any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910320334.XA CN111833820A (en) | 2019-04-19 | 2019-04-19 | Grid scanning driving circuit, driving method and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910320334.XA CN111833820A (en) | 2019-04-19 | 2019-04-19 | Grid scanning driving circuit, driving method and display panel |
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| CN111833820A true CN111833820A (en) | 2020-10-27 |
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Effective date of registration: 20201209 Address after: No.146 Tianying Road, high tech Zone, Chengdu, Sichuan Province Applicant after: Chengdu CHENXIAN photoelectric Co.,Ltd. Address before: 065500 new industrial demonstration area of Guan County, Langfang, Hebei Applicant before: Yungu (Gu'an) Technology Co.,Ltd. |
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Application publication date: 20201027 |