CN100397468C - shift register circuit - Google Patents

shift register circuit Download PDF

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CN100397468C
CN100397468C CNB2005100976772A CN200510097677A CN100397468C CN 100397468 C CN100397468 C CN 100397468C CN B2005100976772 A CNB2005100976772 A CN B2005100976772A CN 200510097677 A CN200510097677 A CN 200510097677A CN 100397468 C CN100397468 C CN 100397468C
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source
drain electrode
transistorized
transistor
grid
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CN1731501A (en
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林威呈
魏俊卿
吴仰恩
马政良
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Optoelectronic Science Co ltd
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AU Optronics Corp
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Abstract

A shift register circuit is provided with a plurality of shift registers connected in series, and comprises a first transistor, wherein the grid electrode and a first source/drain electrode of the first transistor are connected with an output signal of a preceding stage shift register. And a second transistor, the gate of which is connected to the second source/drain of the first transistor, the first source/drain of which is connected to the first clock signal and the second source/drain of which is connected to the output terminal. When the second transistor is turned on and the first clock signal is at a high voltage level, the output terminal has a first voltage level. And the pull-down module is connected with the output end, the output signal of the preceding stage and the secondary shift register, the second voltage level and the third voltage level. When the output signal of the previous stage shift register is the first voltage level, the output terminal is the third voltage level.

Description

移位寄存电路 shift register circuit

技术领域 technical field

本发明有关液晶显示器的驱动电路，特别是液晶显示器的驱动电路中的移位寄存器的驱动电路。The invention relates to a driving circuit of a liquid crystal display, in particular to a driving circuit of a shift register in the driving circuit of a liquid crystal display.

背景技术 Background technique

在有源式液晶驱动技术中，是以非晶硅薄膜晶体管作为在有源式液晶驱动技术中，是以非晶硅薄膜晶体管作为每一个像素的开关组件。对于一个像素而言，当栅极线电压为高电压电平时，非晶硅薄膜晶体管导通，将源极电位拉至与漏极电位相同，得到数据线上的电压。当栅极线电压降为低电压电平时，非晶硅薄膜晶体管则关断，使其源极电位维持在应有的电平。然而，由于晶体管源极与栅极间存在着寄生电容Cgs，当栅极电压由高电压降为低电压电平时，则源极电位会受到影响而产生一定的压降，此压降称为引入压降(feedthrough voltage)ΔVgd，会造成液晶面板无法产生正确的灰度显示，是影响面板显示特性的一个重要因素。In the active liquid crystal driving technology, the amorphous silicon thin film transistor is used as the switch component of each pixel. For a pixel, when the gate line voltage is at a high voltage level, the amorphous silicon thin film transistor is turned on, and the source potential is pulled to be the same as the drain potential to obtain the voltage on the data line. When the voltage of the gate line drops to a low voltage level, the amorphous silicon thin film transistor is turned off, so that the source potential of the transistor is maintained at an appropriate level. However, due to the parasitic capacitance C gs between the source and the gate of the transistor, when the gate voltage drops from a high voltage to a low voltage level, the source potential will be affected and a certain voltage drop will be generated. This voltage drop is called The introduction of a feedthrough voltage ΔV gd will cause the liquid crystal panel to fail to produce correct gray scale display, which is an important factor affecting the display characteristics of the panel.

请参考图1，图1为公知移位寄存器的漏极、栅极以及源极的电压电平示意图。在时间t1中，漏极电压为高电压电平VDD，当栅极电位为高电压电平时，源极电压会先被拉到高电压电平VDD，然后因为寄生电容Cgs的影响而电位下降ΔVgd。在时间t2时，漏极电压为低电压电平VSS，当栅极电位为高电压电平时，源极电压会先被拉到低电压电平VSS，然后因为寄生电容Cgd的影响而电位再下降ΔVgd。由图1可知公知寄存电路会因为寄生电容的影响，使得薄膜晶体管无法表示出预定的电压，造成液晶面板无法产生正确的灰度显示。Please refer to FIG. 1 , which is a schematic diagram of voltage levels of a drain, a gate, and a source of a conventional shift register. In time t1, the drain voltage is at the high voltage level V DD , when the gate potential is at the high voltage level, the source voltage will be pulled to the high voltage level V DD first, and then due to the influence of the parasitic capacitance C gs The potential drops by ΔV gd . At time t2, the drain voltage is a low voltage level V SS , when the gate potential is a high voltage level, the source voltage will be pulled to a low voltage level V SS first, and then due to the influence of the parasitic capacitance C gd The potential then drops by ΔV gd . It can be seen from FIG. 1 that in the known register circuit, due to the influence of parasitic capacitance, the thin film transistor cannot display a predetermined voltage, and the liquid crystal panel cannot produce correct gray scale display.

发明内容 Contents of the invention

本发明的目的为提供一种可减少或消除引入压降的移位寄存电路。The purpose of the present invention is to provide a shift register circuit which can reduce or eliminate the voltage drop introduced.

本发明的另一目的为提供一种具有三阶驱动电压的移位寄存电路，以减少或消除引入压降。Another object of the present invention is to provide a shift register circuit with three-level driving voltage to reduce or eliminate the induced voltage drop.

本发明提供一种移位寄存电路，具有多个串接级的移位寄存器，包括一第一晶体管、一第二晶体管以及一下拉模块。第一晶体管的栅极与其第一源/漏极连接一前级移位寄存器的输出信号。第二晶体管的栅极连接第一晶体管的第二源/漏极，第二晶体管的第一源/漏极连接一第一时钟信号，第二晶体管的第二源/漏极连接一输出端。当第二晶体管导通且该第一时钟信号为一高电压电平时，输出端具有一第一电压电平。下拉模块连接该输出端、一次级移位寄存器的输出信号、一第二电压电平与一第三电压电平。当该次级移位寄存器的输出信号为该第二或第三电压电平时，连接该输出端与该第二电压电平；当该次级移位寄存器的输出信号为该第一电压电平时，连接该输出端与该第三电压电平。The invention provides a shift register circuit, which has a plurality of serially connected shift registers, including a first transistor, a second transistor and a pull-down module. The gate of the first transistor and its first source/drain are connected to an output signal of a previous shift register. The gate of the second transistor is connected to the second source/drain of the first transistor, the first source/drain of the second transistor is connected to a first clock signal, and the second source/drain of the second transistor is connected to an output terminal. When the second transistor is turned on and the first clock signal is at a high voltage level, the output terminal has a first voltage level. The pull-down module is connected to the output terminal, an output signal of a secondary shift register, a second voltage level and a third voltage level. When the output signal of the secondary shift register is the second or third voltage level, connect the output terminal to the second voltage level; when the output signal of the secondary shift register is the first voltage level , connecting the output terminal with the third voltage level.

本发明更提供一种移位寄存电路，形成于一玻璃基板上，具有三阶驱动电压，包括多个串接级的移位寄存器，其中每一移位寄存器包括多个晶体管。第一晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第一晶体管的栅极与该第一晶体管的第一源/漏极连接一前级移位寄存器的输出信号。第二晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第二晶体管的栅极连接该第一晶体管的第二源/漏极，该第二晶体管的第一源/漏极连接一第一时钟信号，该第二晶体管的第二源/漏极连接一输出端，当该第二晶体管导通且该第一时钟信号为一高电压电平时，该输出端具有一第一电压电平。第三晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第三晶体管的栅极连接该输出端，该第三晶体管的第二源/漏极连接该第二电压电平。第四晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第四晶体管的栅极连接该次级移位寄存器的输出信号，该第四晶体管的第一源/漏极连接该第三晶体管第一源/漏极，该第四晶体管的第二源/漏极连接该第二电压电平。第五晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第五晶体管的第一源/漏极连接该输出端，该第五晶体管的第二源/漏极连接该第三电压电平，该第五晶体管的栅极连接该第四晶体管的栅极。一第六晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第六晶体管的栅极连接该第四晶体管的栅极，该第六晶体管的第二源/漏极连接该第二电压电平，该第六晶体管的第一源/漏极连接该第二晶体管的栅极。第七晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第七晶体管的第一源/漏极连接该输出端，该第七晶体管的第二源/漏极连接该第二电压电平，该第七晶体管的栅极连接该第四晶体管的第一源/漏极。第八晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第八晶体管的第二源/漏极连接该第二电压电平，该第八晶体管的栅极连接该第七晶体管的栅极，该第八晶体管的第一源/漏极连接该第二晶体管的栅极。第九晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第九晶体管的栅极与该第九晶体管的第一源/漏极连接该第二时钟信号，该第九晶体管的第二源/漏极连接该第八晶体管的栅极。第十晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第十晶体管的第二源/漏极连接该第二电压电平，该第十晶体管的栅极连接该第一时钟信号，该第十晶体管的第一源/漏极连接该第八晶体管的栅极。第十一晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第十一晶体管的第二源/漏极连接该第二电压电平，该第十一晶体管的栅极连接该前级移位寄存器的输出信号，该第十一晶体管的第一源/漏极连接该第八晶体管的栅极与该第三晶体管的第一源/漏极。第十二晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第十二晶体管的第二源/漏极连接该第二电压电平，该第十二晶体管的栅极连接该输出端。第十三晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第十三晶体管的第一源/漏极连接该输出端，该第十三晶体管的第二源/漏极连接该第二电压电平，该第十三晶体管的栅极连接该第十二晶体管的第一源/漏极。第十四晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第十四晶体管的第二源/漏极连接该第二电压电平，该第十四晶体管的栅极连接该第十三晶体管的栅极，该第十四晶体管的第一源/漏极连接该第二晶体管的栅极。第十五晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第十五晶体管的栅极与该第十五晶体管的第一源/漏极连接该第一时钟信号，该第十五晶体管的第二源/漏极连接该第十三晶体管的栅极。第十六晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第十六晶体管的第二源/漏极连接该第二电压电平，该第十六晶体管的栅极连接该第二时钟信号，该第十六晶体管的第一源/漏极连接该第十三晶体管的栅极。The present invention further provides a shift register circuit, which is formed on a glass substrate, has three-level driving voltage, and includes a plurality of serially connected shift registers, wherein each shift register includes a plurality of transistors. The first transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the first transistor is connected to the first source/drain of the first transistor by a previous stage shift The output signal of the bit register. The second transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the second transistor is connected to the second source/drain of the first transistor, and the second transistor The first source/drain of the second transistor is connected to a first clock signal, the second source/drain of the second transistor is connected to an output terminal, when the second transistor is turned on and the first clock signal is at a high voltage level, The output terminal has a first voltage level. The third transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the third transistor is connected to the output terminal, and the second source/drain of the third transistor is connected to the second voltage level. The fourth transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the fourth transistor is connected to the output signal of the secondary shift register, and the first of the fourth transistor A source/drain is connected to the first source/drain of the third transistor, and a second source/drain of the fourth transistor is connected to the second voltage level. The fifth transistor has a gate, a first source/drain and a second source/drain, wherein the first source/drain of the fifth transistor is connected to the output terminal, and the second source of the fifth transistor The /drain is connected to the third voltage level, and the gate of the fifth transistor is connected to the gate of the fourth transistor. A sixth transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the sixth transistor is connected to the gate of the fourth transistor, and the second of the sixth transistor The source/drain is connected to the second voltage level, and the first source/drain of the sixth transistor is connected to the gate of the second transistor. The seventh transistor has a gate, a first source/drain and a second source/drain, wherein the first source/drain of the seventh transistor is connected to the output terminal, and the second source of the seventh transistor The /drain is connected to the second voltage level, and the gate of the seventh transistor is connected to the first source/drain of the fourth transistor. The eighth transistor has a gate, a first source/drain and a second source/drain, wherein the second source/drain of the eighth transistor is connected to the second voltage level, and the eighth transistor The gate is connected to the gate of the seventh transistor, and the first source/drain of the eighth transistor is connected to the gate of the second transistor. The ninth transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the ninth transistor and the first source/drain of the ninth transistor are connected to the second clock signal, the second source/drain of the ninth transistor is connected to the gate of the eighth transistor. The tenth transistor has a gate, a first source/drain and a second source/drain, wherein the second source/drain of the tenth transistor is connected to the second voltage level, and the tenth transistor The gate is connected to the first clock signal, and the first source/drain of the tenth transistor is connected to the gate of the eighth transistor. The eleventh transistor has a gate, a first source/drain and a second source/drain, wherein the second source/drain of the eleventh transistor is connected to the second voltage level, and the tenth A gate of a transistor is connected to an output signal of the preceding shift register, and a first source/drain of the eleventh transistor is connected to a gate of the eighth transistor and a first source/drain of the third transistor. The twelfth transistor has a gate, a first source/drain and a second source/drain, wherein the second source/drain of the twelfth transistor is connected to the second voltage level, and the tenth The gates of the two transistors are connected to the output terminal. The thirteenth transistor has a gate, a first source/drain and a second source/drain, wherein the first source/drain of the thirteenth transistor is connected to the output terminal, and the thirteenth transistor’s The second source/drain is connected to the second voltage level, and the gate of the thirteenth transistor is connected to the first source/drain of the twelfth transistor. The fourteenth transistor has a gate, a first source/drain and a second source/drain, wherein the second source/drain of the fourteenth transistor is connected to the second voltage level, and the tenth The gate of the fourth transistor is connected to the gate of the thirteenth transistor, and the first source/drain of the fourteenth transistor is connected to the gate of the second transistor. The fifteenth transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the fifteenth transistor is connected to the first source/drain of the fifteenth transistor. For the first clock signal, the second source/drain of the fifteenth transistor is connected to the gate of the thirteenth transistor. The sixteenth transistor has a gate, a first source/drain and a second source/drain, wherein the second source/drain of the sixteenth transistor is connected to the second voltage level, and the tenth The gate of the sixth transistor is connected to the second clock signal, and the first source/drain of the sixteenth transistor is connected to the gate of the thirteenth transistor.

为让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，详细说明如下：In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are listed below, together with the accompanying drawings, and detailed descriptions are as follows:

附图说明 Description of drawings

图1为公知移位寄存器的漏极、栅极以及源极的电压电平示意图。FIG. 1 is a schematic diagram of voltage levels of a drain, a gate, and a source of a conventional shift register.

图2为显示面板中一像素示意图。FIG. 2 is a schematic diagram of a pixel in a display panel.

图3为一三阶驱动的栅极电压示意图。FIG. 3 is a schematic diagram of the gate voltage of a third-level drive.

图4为根据本发明的第一实施例的一移位寄存器的示意图。FIG. 4 is a schematic diagram of a shift register according to the first embodiment of the present invention.

图5为根据本发明的第二实施例的一移位寄存器的示意图。FIG. 5 is a schematic diagram of a shift register according to a second embodiment of the present invention.

图6A为图5中第二电压电平下拉模块50的第一实施例的示意图。FIG. 6A is a schematic diagram of a first embodiment of the second voltage level pull-down module 50 in FIG. 5 .

图6B为图5中第二电压电平下拉模块50的第二实施例的示意图。FIG. 6B is a schematic diagram of a second embodiment of the second voltage level pull-down module 50 in FIG. 5 .

图7为图6A中第一下拉模块61的一实施例的电路图。FIG. 7 is a circuit diagram of an embodiment of the first pull-down module 61 in FIG. 6A .

图8为图6A中第二下拉模块62的一实施例的电路图。FIG. 8 is a circuit diagram of an embodiment of the second pull-down module 62 in FIG. 6A .

图9为图5中第三电压电平下拉模块51的一实施例的电路图。FIG. 9 is a circuit diagram of an embodiment of the third voltage level pull-down module 51 in FIG. 5 .

图10为根据本发明的一实施例的移位寄存器电路图。FIG. 10 is a circuit diagram of a shift register according to an embodiment of the present invention.

图11为图10的移位寄存器电路的时序图。FIG. 11 is a timing diagram of the shift register circuit of FIG. 10 .

符号说明Symbol Description

21-薄膜晶体管21- Thin film transistor

22-像素22-pixel

23-栅极23-Gate

24-栅极线24-gate line

25-数据线25-data line

T41、T42、T51、T52、T71、T72、T73、T74、T81、T82、T83、T84、T85、T91、T92、T93、T1-T16-晶体管T41, T42, T51, T52, T71, T72, T73, T74, T81, T82, T83, T84, T85, T91, T92, T93, T1-T16 - Transistors

40-下拉模块40-Drop-down module

50-第二电压电平下拉模块50-second voltage level pull-down module

51-第三电压电平下拉模块51-Third voltage level pull-down module

61-第一下拉模块61 - First drop-down module

62-第二下拉模块62-Second drop-down module

63-第一开关装置63 - First switching device

64-第二开关装置64 - Second switching device

具体实施方式 Detailed ways

图2为显示面板中一像素示意图。薄膜晶体管21连接栅极线24、数据线25以及像素22。像素22与栅极线24与23的间分别产生耦合电容Cgs与Cst。FIG. 2 is a schematic diagram of a pixel in a display panel. The thin film transistor 21 is connected to the gate line 24 , the data line 25 and the pixel 22 . Coupling capacitances C gs and C st are generated between the pixel 22 and the gate lines 24 and 23 respectively.

图3为一三阶驱动的栅极电压示意图。当第N条栅极线的电压由高电压电平V2降到低电压电平时，因Cgs电容耦合的关系使得像素22的电位因而产生引入压降；而此时第(N-1)条栅极线的电压由低电压电平V3上升至V1，因Cst电容耦合的关系，像素22电压因而有些微的上升。因此像素，如图1中的像素22，可减少因为电容耦合所形成的引入压降大小，进而减少其所造成的问题。FIG. 3 is a schematic diagram of the gate voltage of a third-level drive. When the voltage of the Nth gate line drops from the high voltage level V2 to the low voltage level, the potential of the pixel 22 will generate a voltage drop due to the relationship of C gs capacitive coupling; and at this time (N-1) The voltage of the first gate line rises from the low voltage level V 3 to V 1 , and the voltage of the pixel 22 rises slightly due to the capacitive coupling of C st . Therefore, the pixel, such as the pixel 22 in FIG. 1 , can reduce the voltage drop caused by the capacitive coupling, thereby reducing the problems caused by it.

图4为根据本发明的第一实施例的一移位寄存器的示意图。晶体管T41的栅极与第一源/漏极连接一前级移位寄存器的输出信号(N-1)与一下拉模块。晶体管T42的栅极连接晶体管T41的第二源/漏极，晶体管T42的第一源漏极连接一时钟信号CLK，第二源漏极连接下拉模块40与移位寄存器的输出信号N。下拉模块40还连接一次级移位寄存器的输出信号(N+1)、第二电压电平VSS以及第三电压电平VSS’。当晶体管T42导通且时钟信号CLK为高电压电平时，移位寄存器的输出信号N具有一第一电压电平。当次级移位寄存器的输出信号(N+1)为第二或第三电压电平时，连接该移位寄存器的输出信号N至第二电压电平VSS。当该次级移位寄存器的输出信号(N+1)为第一电压电平时，连接移位寄存器的输出信号N至第三电压电平VSS’。利用上述的驱动方式，以达到本发明的移位寄存器的三阶驱动。FIG. 4 is a schematic diagram of a shift register according to the first embodiment of the present invention. The gate and the first source/drain of the transistor T41 are connected to an output signal (N−1) of a previous shift register and a pull-down module. The gate of the transistor T42 is connected to the second source/drain of the transistor T41 , the first source and drain of the transistor T42 are connected to a clock signal CLK, and the second source and drain are connected to the pull-down module 40 and the output signal N of the shift register. The pull-down module 40 is also connected to the output signal (N+1) of the secondary shift register, the second voltage level V SS and the third voltage level V SS ′. When the transistor T42 is turned on and the clock signal CLK is at a high voltage level, the output signal N of the shift register has a first voltage level. When the output signal (N+1) of the secondary shift register is at the second or third voltage level, the output signal N of the shift register is connected to the second voltage level V SS . When the output signal (N+1) of the secondary shift register is at the first voltage level, the output signal N of the shift register is connected to the third voltage level V SS ′. The above-mentioned driving method is used to achieve the third-level driving of the shift register of the present invention.

在本发明的实施例中，该下拉模块40可能由多任务器、晶体管或逻辑门所组成的电路。In an embodiment of the present invention, the pull-down module 40 may be a circuit composed of multiplexers, transistors or logic gates.

图5为根据本发明的第二实施例的一移位寄存器的示意图。晶体管T51的栅极与第一源/漏极连接一前级移位寄存器的输出信号(N-1)与一第二电压电平下拉模块50。晶体管T52的栅极连接晶体管T51的第二源漏极，晶体管T52的第一源漏极连接一时钟信号CLK，第二源漏极连接移位寄存器的输出信号N。第二电压电平下拉模块50连接移位寄存器的输出信号N、次级移位寄存器的输出信号(N+1)与一第二电压电平VSS。第三电压电平下拉模块51连接移位寄存器的输出信号N、次级移位寄存器的输出信号(N+1)与一第三电压电平VSS’。当晶体管T52导通且时钟信号CLK为高电压电平时，移位寄存器的输出信号N具有一第一电压电平。当前级移位寄存器的输出信号(N-1)为第二或第三电压电平时，第二电压电平下拉模块50连接该移位寄存器的输出信号N至第二电压电平VSS。当该次级移位寄存器的输出信号(N+1)为第一电压电平时，第三电压电平下拉模块51连接移位寄存器的输出信号N至第三电压电平VSS’。利用上述的驱动方式，以达到本发明的移位寄存器的三阶驱动。FIG. 5 is a schematic diagram of a shift register according to a second embodiment of the present invention. The gate and the first source/drain of the transistor T51 are connected to an output signal (N−1) of a previous stage shift register and a second voltage level pull-down module 50 . The gate of the transistor T52 is connected to the second source and drain of the transistor T51 , the first source and drain of the transistor T52 are connected to a clock signal CLK, and the second source and drain are connected to the output signal N of the shift register. The second voltage level pull-down module 50 is connected to the output signal N of the shift register, the output signal (N+1) of the secondary shift register and a second voltage level V SS . The third voltage level pull-down module 51 is connected to the output signal N of the shift register, the output signal (N+1) of the secondary shift register and a third voltage level V SS ′. When the transistor T52 is turned on and the clock signal CLK is at a high voltage level, the output signal N of the shift register has a first voltage level. When the output signal (N−1) of the previous stage shift register is at the second or third voltage level, the second voltage level pull-down module 50 connects the output signal N of the shift register to the second voltage level V SS . When the output signal (N+1) of the secondary shift register is at the first voltage level, the third voltage level pull-down module 51 connects the output signal N of the shift register to the third voltage level V SS ′. The above-mentioned driving method is used to achieve the third-level driving of the shift register of the present invention.

在本发明的实施例中，第二电压电平下拉模块50与第三电压电平下拉模块51可能由多任务器、晶体管或逻辑门所组成的电路。In an embodiment of the present invention, the second voltage level pull-down module 50 and the third voltage level pull-down module 51 may be circuits composed of multiplexers, transistors or logic gates.

图6A为图5中第二电压电平下拉模块50的第一实施例的示意图。在图6A中，第二电压电平下拉模块50包括一第一下拉模块61与一第二下拉模块62。第一下拉模块61连接时钟信号CLK、移位寄存器的输出信号N与第二电压电平VSS。第二下拉模块62连接时钟信号XCLK、移位寄存器的输出信号N、前级移位寄存器输出信号(N-1)以及第二电压电平VSS。当该第一时钟信号为该高电压电平时，连接移位寄存器的输出信号N至该第二电压电平VSS。当该前级移位寄存器的输出信号(N-1)为该第二电压电平VSS且该第二时钟信号为该高电压电平时，连接移位寄存器的输出信号N至该第二电压电平VSS。FIG. 6A is a schematic diagram of a first embodiment of the second voltage level pull-down module 50 in FIG. 5 . In FIG. 6A , the second voltage level pull-down module 50 includes a first pull-down module 61 and a second pull-down module 62 . The first pull-down module 61 is connected to the clock signal CLK, the output signal N of the shift register and the second voltage level V SS . The second pull-down module 62 is connected to the clock signal XCLK, the output signal N of the shift register, the output signal (N−1) of the previous shift register, and the second voltage level V SS . When the first clock signal is at the high voltage level, the output signal N of the shift register is connected to the second voltage level V SS . When the output signal (N-1) of the previous stage shift register is the second voltage level V SS and the second clock signal is the high voltage level, connect the output signal N of the shift register to the second voltage Level V SS .

图6B为图5中第二电压电平下拉模块50的第二实施例的示意图。在图6B中，第二电压电平下拉模块50包括一第一下拉模块61、一第二下拉模块62、一第一开关装置63与一第二开关装置64。第一下拉模块61连接时钟信号CLK、第二开关装置64、移位寄存器的输出信号N与第二电压电平VSS。第二下拉模块62连接时钟信号XCLK、第一开关装置63、移位寄存器的输出信号N、前级移位寄存器输出信号(N-1)以及第二电压电平VSS。当移位寄存器的输出信号N为高电压电平时，第一开关装置63与第二开关装置64关断第二下拉模块62与第一下拉模块61。当该第一时钟信号为该高电压电平时，连接移位寄存器的输出信号N至该第二电压电平VSS。当该前级移位寄存器的输出信号(N-1)为该第二电压电平VSS且该第二时钟信号为该高电压电平时，连接移位寄存器的输出信号N至该第二电压电平VSS。FIG. 6B is a schematic diagram of a second embodiment of the second voltage level pull-down module 50 in FIG. 5 . In FIG. 6B , the second voltage level pull-down module 50 includes a first pull-down module 61 , a second pull-down module 62 , a first switch device 63 and a second switch device 64 . The first pull-down module 61 is connected to the clock signal CLK, the second switch device 64 , the output signal N of the shift register, and the second voltage level V SS . The second pull-down module 62 is connected to the clock signal XCLK, the first switch device 63 , the output signal N of the shift register, the output signal (N−1) of the preceding shift register, and the second voltage level V SS . When the output signal N of the shift register is at a high voltage level, the first switch device 63 and the second switch device 64 turn off the second pull-down module 62 and the first pull-down module 61 . When the first clock signal is at the high voltage level, the output signal N of the shift register is connected to the second voltage level V SS . When the output signal (N-1) of the previous stage shift register is the second voltage level V SS and the second clock signal is the high voltage level, connect the output signal N of the shift register to the second voltage Level V SS .

在本发明的实施例中，第一下拉模块61与第二下拉模块62可能由多任务器、晶体管或逻辑门所组成的电路。In the embodiment of the present invention, the first pull-down module 61 and the second pull-down module 62 may be circuits composed of multiplexers, transistors or logic gates.

为更清楚说明第一下拉模块61与第二下拉模块62，本发明说明书以一电路图说明如下。In order to illustrate the first pull-down module 61 and the second pull-down module 62 more clearly, a circuit diagram of the present invention is described as follows.

图7为图6A中第一下拉模块61的一实施例的电路图。晶体管T71的第一源/漏极连接移位寄存器的输出信号N，其第二源/漏极连接第二电压电平VSS。晶体管T72的第二源/漏极连接第二电压电平VSS，晶体管T72的栅极连接晶体管T71的栅极。晶体管T73的栅极与其第一源/漏极连接第一时钟信号CLK，晶体管T73的第二源/漏极连接晶体管T71的栅极。晶体管T74的第二源/漏极连接第二电压电平VSS，晶体管T74的栅极连接第二时钟信号XCLK，且晶体管T74的第一源/漏极连接该晶体管T71的栅极。当第一时钟信号CLK为高电压电平时，第二时钟信号XCLK为低电压电平，晶体管T73导通且晶体管T74关断。晶体管T71与T72亦被导通，使得移位寄存器的输出信号N被连接至第二电压电平VSS。FIG. 7 is a circuit diagram of an embodiment of the first pull-down module 61 in FIG. 6A . The first source/drain of the transistor T71 is connected to the output signal N of the shift register, and the second source/drain of the transistor T71 is connected to the second voltage level V SS . The second source/drain of the transistor T72 is connected to the second voltage level V SS , and the gate of the transistor T72 is connected to the gate of the transistor T71 . The gate of the transistor T73 and its first source/drain are connected to the first clock signal CLK, and the second source/drain of the transistor T73 is connected to the gate of the transistor T71. The second source/drain of the transistor T74 is connected to the second voltage level V SS , the gate of the transistor T74 is connected to the second clock signal XCLK, and the first source/drain of the transistor T74 is connected to the gate of the transistor T71 . When the first clock signal CLK is at a high voltage level and the second clock signal XCLK is at a low voltage level, the transistor T73 is turned on and the transistor T74 is turned off. The transistors T71 and T72 are also turned on, so that the output signal N of the shift register is connected to the second voltage level V SS .

图8为图6A中第二下拉模块62的一实施例的电路图。晶体管T81的第一源/漏极连接移位寄存器的输出信号N，其第二源/漏极连接第二电压电平VSS。晶体管T82的第二源/漏极连接第二电压电平VSS，晶体管T82的栅极连接晶体管T81的栅极。晶体管T83的栅极与该其第一源/漏极连接第二时钟信号XCLK，晶体管T83的第二源/漏极连接晶体管T82的栅极。晶体管T84的第二源/漏极连接第二电压电平VSS，晶体管T84的栅极连接第一时钟信号CLK，晶体管T84的第一源/漏极连接晶体管T82的栅极。晶体管T85的第二源/漏极连接第二电压电平VSS，晶体管T85的栅极连接前级移位寄存器的输出信号(N-1)，晶体管T85的第一源/漏极连接晶体管T82的栅极。当前级移位寄存器的输出信号(N-1)为低电压电平且第二时钟信号XCLK为该高电压电平时，晶体管T85关断且晶体管T81与T82导通，使得移位寄存器的输出信号N被连接至该第二电压电平VSS。FIG. 8 is a circuit diagram of an embodiment of the second pull-down module 62 in FIG. 6A . The first source/drain of the transistor T81 is connected to the output signal N of the shift register, and the second source/drain of the transistor T81 is connected to the second voltage level V SS . The second source/drain of the transistor T82 is connected to the second voltage level V SS , and the gate of the transistor T82 is connected to the gate of the transistor T81 . The gate of the transistor T83 is connected to the first source/drain of the second clock signal XCLK, and the second source/drain of the transistor T83 is connected to the gate of the transistor T82. The second source/drain of the transistor T84 is connected to the second voltage level V SS , the gate of the transistor T84 is connected to the first clock signal CLK, and the first source/drain of the transistor T84 is connected to the gate of the transistor T82 . The second source/drain of the transistor T85 is connected to the second voltage level V SS , the gate of the transistor T85 is connected to the output signal (N-1) of the previous shift register, and the first source/drain of the transistor T85 is connected to the transistor T82 the grid. When the output signal (N-1) of the front-stage shift register is at a low voltage level and the second clock signal XCLK is at the high voltage level, the transistor T85 is turned off and the transistors T81 and T82 are turned on, so that the output signal of the shift register N is connected to this second voltage level V SS .

图9为图5中第三电压电平下拉模块51的一实施例的电路图。晶体管T91的栅极连接次级移位寄存器的输出信号(N+1)，晶体管T91的第二源/漏极连接第二电压电平VSS。晶体管T92的第一源/漏极连接移位寄存器的输出信号N，晶体管T92的第二源/漏极连接第三电压电平VSS’，晶体管T92的栅极连接晶体管T91的栅极。晶体管T93的栅极连接晶体管T91的栅极，晶体管T93的第二源/漏极连接第二电压电平VSS。当次级移位寄存器的输出信号(N+1)为高电压电平时，晶体管T91、T92以及T93被导通，移位寄存器的输出信号N因此被连接至第三电压电平VSS’。FIG. 9 is a circuit diagram of an embodiment of the third voltage level pull-down module 51 in FIG. 5 . The gate of the transistor T91 is connected to the output signal (N+1) of the secondary shift register, and the second source/drain of the transistor T91 is connected to the second voltage level V SS . The first source/drain of the transistor T92 is connected to the output signal N of the shift register, the second source/drain of the transistor T92 is connected to the third voltage level V SS ′, and the gate of the transistor T92 is connected to the gate of the transistor T91. The gate of the transistor T93 is connected to the gate of the transistor T91 , and the second source/drain of the transistor T93 is connected to the second voltage level V SS . When the output signal (N+1) of the secondary shift register is at a high voltage level, the transistors T91 , T92 and T93 are turned on, and the output signal N of the shift register is thus connected to the third voltage level V SS ′.

图10为根据本发明的一实施例的移位寄存器电路图。晶体管T1的栅极与其第一源/漏极连接一前级移位寄存器的输出信号(N-1)。晶体管T2栅极连接该晶体管T1的第二源/漏极，晶体管T2的第一源/漏极连接一第一时钟信号CLK，晶体管T2的第二源/漏极连接一移位寄存器的输出信号N。晶体管T3的栅极连接移位寄存器的输出信号N，晶体管T3的第二源/漏极连接第二电压电平VSS。晶体管T4的栅极连接次级移位寄存器的输出信号(N+1)，晶体管T4的第一源/漏极连接晶体管T3第一源/漏极，晶体管T4的第二源/漏极连接第二电压电平VSS。晶体管T5的第一源/漏极连接移位寄存器的输出信号具N，晶体管T5的第二源/漏极连接第三电压电平VSS’，晶体管T5的栅极连接该晶体管T4的栅极。晶体管T6的栅极连接晶体管T4的栅极，晶体管T6的第二源/漏极连接第二电压电平VSS，晶体管T6的第一源/漏极连接晶体管T2的栅极。晶体管T7的第一源/漏极连接该移位寄存器的输出信号N，晶体管T7的第二源/漏极连接第二电压电平VSS，晶体管T7的栅极连接晶体管T4的第二源/漏极。晶体管T8的第二源/漏极连接该第二电压电平VSS，晶体管T8的栅极连接晶体管T7的栅极，晶体管T8的第一源/漏极连接晶体管T2的栅极。晶体管T9的栅极与其第一源/漏极连接第二时钟信号XCLK，晶体管T9的第二源/漏极连接晶体管T8的栅极。晶体管T10的第二源/漏极连接第二电压电平VSS，晶体管T10的栅极连接第一时钟信号CLK，晶体管T10的第一源/漏极连接晶体管T8的栅极。晶体管T11的第二源/漏极连接第二电压电平VSS，晶体管T11的栅极连接前级移位寄存器的输出信号(N-1)，晶体管T11的第一源/漏极连接晶体管T8的栅极与晶体管T3的第一源/漏极。晶体管T12的第二源/漏极连接第二电压电平VSS，晶体管T12的栅极连接移位寄存器的输出信号N。晶体管T13的第一源/漏极连接移位寄存器的输出信号N，晶体管T13的第二源/漏极连接第二电压电平VSS，晶体管T13的栅极连接晶体管T12的第一源/漏极。晶体管T14的第二源/漏极连接第二电压电平VSS，晶体管T14的栅极连接晶体管T13的栅极，晶体管T14的第一源/漏极连接晶体管T2的栅极。晶体管T15的栅极与其第一源/漏极连接第一时钟信号CLK，晶体管T15的第二源/漏极连接晶体管T13的栅极。晶体管T16的第二源/漏极连接第二电压电平VSS，晶体管T16的栅极连接第二时钟信号XCLK，晶体管T16的第一源/漏极连接晶体管T13的栅极。FIG. 10 is a circuit diagram of a shift register according to an embodiment of the present invention. The gate of the transistor T1 and its first source/drain are connected to an output signal (N-1) of a previous shift register. The gate of the transistor T2 is connected to the second source/drain of the transistor T1, the first source/drain of the transistor T2 is connected to a first clock signal CLK, and the second source/drain of the transistor T2 is connected to an output signal of a shift register N. The gate of the transistor T3 is connected to the output signal N of the shift register, and the second source/drain of the transistor T3 is connected to the second voltage level V SS . The gate of the transistor T4 is connected to the output signal (N+1) of the secondary shift register, the first source/drain of the transistor T4 is connected to the first source/drain of the transistor T3, and the second source/drain of the transistor T4 is connected to the second Two voltage levels V SS . The first source/drain of the transistor T5 is connected to the output signal of the shift register with N, the second source/drain of the transistor T5 is connected to the third voltage level V SS ', and the gate of the transistor T5 is connected to the gate of the transistor T4 . The gate of the transistor T6 is connected to the gate of the transistor T4, the second source/drain of the transistor T6 is connected to the second voltage level V SS , and the first source/drain of the transistor T6 is connected to the gate of the transistor T2. The first source/drain of the transistor T7 is connected to the output signal N of the shift register, the second source/drain of the transistor T7 is connected to the second voltage level V SS , and the gate of the transistor T7 is connected to the second source/drain of the transistor T4. drain. The second source/drain of the transistor T8 is connected to the second voltage level V SS , the gate of the transistor T8 is connected to the gate of the transistor T7 , and the first source/drain of the transistor T8 is connected to the gate of the transistor T2 . The gate of the transistor T9 and its first source/drain are connected to the second clock signal XCLK, and the second source/drain of the transistor T9 is connected to the gate of the transistor T8. The second source/drain of the transistor T10 is connected to the second voltage level V SS , the gate of the transistor T10 is connected to the first clock signal CLK, and the first source/drain of the transistor T10 is connected to the gate of the transistor T8 . The second source/drain of the transistor T11 is connected to the second voltage level V SS , the gate of the transistor T11 is connected to the output signal (N-1) of the previous shift register, and the first source/drain of the transistor T11 is connected to the transistor T8 The gate is connected to the first source/drain of transistor T3. The second source/drain of the transistor T12 is connected to the second voltage level V SS , and the gate of the transistor T12 is connected to the output signal N of the shift register. The first source/drain of the transistor T13 is connected to the output signal N of the shift register, the second source/drain of the transistor T13 is connected to the second voltage level V SS , and the gate of the transistor T13 is connected to the first source/drain of the transistor T12 pole. The second source/drain of the transistor T14 is connected to the second voltage level V SS , the gate of the transistor T14 is connected to the gate of the transistor T13 , and the first source/drain of the transistor T14 is connected to the gate of the transistor T2 . The gate of the transistor T15 and its first source/drain are connected to the first clock signal CLK, and the second source/drain of the transistor T15 is connected to the gate of the transistor T13. The second source/drain of the transistor T16 is connected to the second voltage level V SS , the gate of the transistor T16 is connected to the second clock signal XCLK, and the first source/drain of the transistor T16 is connected to the gate of the transistor T13 .

图11为图10的移位寄存器电路的时序图。再时间t1时，前级移位寄存器的输出信号(N-1)为第一电压电平V1，使得晶体管T1、T2以及T11导通，端点N1的电位为高电压电平。此时第一时钟信号CLK为低电压电平，因此移位寄存器的输出信号N仍为第二电压电平VSS。FIG. 11 is a timing diagram of the shift register circuit of FIG. 10 . At time t1, the output signal (N-1) of the previous stage shift register is at the first voltage level V1, so that the transistors T1, T2 and T11 are turned on, and the potential of the terminal N1 is at a high voltage level. At this moment, the first clock signal CLK is at a low voltage level, so the output signal N of the shift register is still at the second voltage level V SS .

在时间t2时，前级移位寄存器的输出信号(N-1)被下拉至第三电压电平VSS’，第一时钟信号CLK为高电压电平，使得晶体管T2因栅极与源/漏极的间的耦合电容，造成端点N1的电位变得更高。移位寄存器的输出信号N的电位因为晶体管T2的导通与第一时钟信号的高电压电平而位于第一电压电平V1。At time t2, the output signal (N-1) of the previous stage shift register is pulled down to the third voltage level V SS ', and the first clock signal CLK is at a high voltage level, so that the transistor T2 is connected to the gate and source/ The coupling capacitance between the drains causes the potential of the terminal N1 to become higher. The potential of the output signal N of the shift register is at the first voltage level V 1 due to the conduction of the transistor T2 and the high voltage level of the first clock signal.

在时间t3时，次级移位寄存器的输出信号(N+1)为第一电压电平V1，使得晶体管T4、T5以及T6导通。使得端点N1的电位通过晶体管T6被下拉至第二电压电平VSS，移位寄存器的输出信号N通过晶体管T5被下拉至第三电压电平VSS’。At time t3, the output signal (N+1) of the secondary shift register is at the first voltage level V 1 , so that the transistors T4 , T5 and T6 are turned on. The potential of the terminal N1 is pulled down to the second voltage level V SS through the transistor T6 , and the output signal N of the shift register is pulled down to the third voltage level V SS ′ through the transistor T5 .

在时间t4时，次级移位寄存器的输出信号(N+1)被下拉至第三电压电平VSS’，得晶体管T4、T5以及T6关断。此时第一时钟信号CLK为高电压电平，晶体管T15被导通，端点N2为高电压电平，导通晶体管T13，移位寄存器的输出信号从第三电压电平VSS’上拉到第二电压电平VSS。At time t4, the output signal (N+1) of the secondary shift register is pulled down to the third voltage level V SS ′, so that the transistors T4 , T5 and T6 are turned off. At this time, the first clock signal CLK is at a high voltage level, the transistor T15 is turned on, the terminal N2 is at a high voltage level, and the transistor T13 is turned on, and the output signal of the shift register is pulled up from the third voltage level V SS ' to The second voltage level V SS .

在时间t1-t4的外，当第一时钟信号CLK为高电压电平时，由晶体管T13负责将移位寄存器的输出信号N维持在第二电压电平VSS。当第二时钟信号XCLK为高电压电平且前级移位寄存器的输出信号(N-1)为第二或第三电压电平时，由晶体管T7负责将移位寄存器的输出信号N维持在第二电压电平VSS。Outside of time t1-t4, when the first clock signal CLK is at a high voltage level, the transistor T13 is responsible for maintaining the output signal N of the shift register at the second voltage level V SS . When the second clock signal XCLK is at a high voltage level and the output signal (N-1) of the previous stage shift register is at the second or third voltage level, the transistor T7 is responsible for maintaining the output signal N of the shift register at the first Two voltage levels V SS .

本发明虽以优选实施例公开如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围的情况下，可进行更动与修改，因此本发明的保护范围以所提出的权利要求所限定的范围为准。Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope is as defined by the appended claims.

Claims (19)

1. a shift register circuit has a plurality of shift registers that are connected in series level, and wherein each shift register comprises:
One the first transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the grid of this first transistor is connected the output signal of a prime shift register with first source/drain electrode of this first transistor, if current shift register is a first order shift register, then the grid of its first transistor is connected a sensitizing pulse signal with first source/drain electrode;
One transistor seconds, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the grid of this transistor seconds connects second source/drain electrode of this first transistor, first source of this transistor seconds/drain electrode connects one first clock signal, second source of this transistor seconds/drain electrode connects an output terminal, when this transistor seconds conducting and this first clock signal were a high-voltage level, this output terminal had one first voltage level; And
Drawing-die piece once, the output signal, one second voltage level and the tertiary voltage level that connect the output signal of this output terminal, this prime shift register, a level shift register, when the output signal of this prime shift register be this second or during the tertiary voltage level, connect this output terminal and this second voltage level; When the output signal of this secondary shift register is this first voltage level, connect this output terminal and this tertiary voltage level.
2. shift register circuit as claimed in claim 1, wherein this drop-down module comprises drop-down module of one second voltage level and the drop-down module of a tertiary voltage level.
3. shift register circuit as claimed in claim 2, wherein the drop-down module of this second voltage level also comprises:
One first drop-down module connects this output terminal and this first clock signal, when this first clock signal is this high-voltage level, connects this output terminal to this second voltage level; And
One second drop-down module connects this output terminal and a second clock signal, when the output signal of this prime shift register is this second voltage level and this second clock signal during for this high-voltage level, connects this output terminal to this second voltage level.
4. shift register circuit as claimed in claim 3, wherein the drop-down module of this second voltage level also comprises one first switchgear, when this output terminal has this first voltage level, turn-offs this first drop-down module.
5. shift register circuit as claimed in claim 3, wherein the drop-down module of this second voltage level also comprises a second switch device, when this output terminal has this first voltage level, turn-offs this second drop-down module.
6. shift register circuit as claimed in claim 3, wherein this second clock signal and first clock signal have 180 degree phase differential.
7. shift register circuit as claimed in claim 1, wherein this first clock signal has 50% or be lower than for 50% work period.
8. shift register circuit as claimed in claim 1, wherein this tertiary voltage level is lower than this second voltage level.
9. shift register circuit as claimed in claim 2, wherein the drop-down module of this tertiary voltage level comprises:
One the 4th transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein the 4th transistorized grid connects the output signal of this secondary shift register, and the 4th transistorized second source/drain electrode connects this second voltage level;
One the 5th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 5th transistorized first source/drain electrode connects this output terminal, the 5th transistorized second source/drain electrode connects this tertiary voltage level, and the 5th transistorized grid connects the 4th transistorized grid; And
One the 6th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 6th transistorized grid connects the 4th transistorized grid, the 6th transistorized second source/drain electrode connects this second voltage level, and the 6th transistorized first source/drain electrode connects the grid of this transistor seconds.
10. shift register circuit as claimed in claim 3, wherein this second drop-down module comprises:
One the 7th transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein the 7th transistorized first source/drain electrode connects this output terminal, and the 7th transistorized second source/drain electrode connects this second voltage level;
One the 8th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 8th transistorized second source/drain electrode connects this second voltage level, the 8th transistorized grid connects the 7th transistorized grid, and the 8th transistorized first source/drain electrode connects the grid of this transistor seconds;
One the 9th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 9th transistorized grid is connected this second clock signal with the 9th transistorized first source/drain electrode, and the 9th transistorized second source/drain electrode connects the 8th transistorized grid;
The tenth transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the tenth transistorized second source/drain electrode connects this second voltage level, the tenth transistorized grid connects this first clock signal, and the tenth transistorized first source/drain electrode connects the 8th transistorized grid; And
The 11 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 11 transistorized second source/drain electrode connects this second voltage level, the 11 transistorized grid connects the output signal of this prime shift register, the 11 transistorized first source/drain electrode connects the 8th transistorized grid, if current shift register is a first order shift register, then its 11 transistorized grid connects a sensitizing pulse signal.
11. shift register circuit as claimed in claim 3, wherein this first drop-down module comprises:
The 13 transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein the 13 transistorized first source/drain electrode connects this output terminal, and the 13 transistorized second source/drain electrode connects this second voltage level;
The 14 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 14 transistorized second source/drain electrode connects this second voltage level, the 14 transistorized grid connects the 13 transistorized grid, and the 14 transistorized first source/drain electrode connects the grid of this transistor seconds;
The 15 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 15 transistorized grid is connected this first clock signal with the 15 transistorized first source/drain electrode, and the 15 transistorized second source/drain electrode connects the 13 transistorized grid; And
The 16 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 16 transistorized second source/drain electrode connects this second voltage level, the 16 transistorized grid connects this second clock signal, and the 16 transistorized first source/drain electrode connects the 13 transistorized grid.
12. shift register circuit as claimed in claim 4, wherein this switchgear is one the 3rd transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 3rd transistorized grid connects this output terminal, the 3rd transistorized first source/drain electrode connects this second drop-down module, and the 3rd transistorized second source/drain electrode connects this second voltage level.
13. shift register circuit as claimed in claim 5, wherein this switchgear is 1 the tenth two-transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the grid of the tenth two-transistor connects this output terminal, first source of the tenth two-transistor/drain electrode connects this first drop-down module, and second source of the tenth two-transistor/drain electrode connects this second voltage level.
14. a shift register circuit is formed on the glass substrate, has three rank driving voltages, comprises the shift register of a plurality of serial connection levels, wherein each shift register comprises:
One the first transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the grid of this first transistor is connected the output signal of a prime shift register with first source/drain electrode of this first transistor, if current shift register is a first order shift register, then the grid of its first transistor is connected a sensitizing pulse signal with first source/drain electrode;
One transistor seconds, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the grid of this transistor seconds connects second source/drain electrode of this first transistor, first source of this transistor seconds/drain electrode connects one first clock signal, second source of this transistor seconds/drain electrode connects an output terminal, when this transistor seconds conducting and this first clock signal were a high-voltage level, this output terminal had one first voltage level;
One the 3rd transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein the 3rd transistorized grid connects this output terminal, and the 3rd transistorized second source/drain electrode connects one second voltage level;
One the 4th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 4th transistorized grid connects the output signal of a level shift register, the 4th transistorized first source/drain electrode connects the first source/drain electrode of the 3rd transistor, and the 4th transistorized second source/drain electrode connects this second voltage level;
One the 5th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 5th transistorized first source/drain electrode connects this output terminal, the 5th transistorized second source/drain electrode connects a tertiary voltage level, and the 5th transistorized grid connects the 4th transistorized grid;
One the 6th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 6th transistorized grid connects the 4th transistorized grid, the 6th transistorized second source/drain electrode connects this second voltage level, and the 6th transistorized first source/drain electrode connects the grid of this transistor seconds;
One the 7th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 7th transistorized first source/drain electrode connects this output terminal, the 7th transistorized second source/drain electrode connects this second voltage level, and the 7th transistorized grid connects the 4th transistorized second source/drain electrode;
One the 8th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 8th transistorized second source/drain electrode connects this second voltage level, the 8th transistorized grid connects the 7th transistorized grid, and the 8th transistorized first source/drain electrode connects the grid of this transistor seconds;
One the 9th transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 9th transistorized grid is connected a second clock signal with the 9th transistorized first source/drain electrode, and the 9th transistorized second source/drain electrode connects the 8th transistorized grid;
The tenth transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the tenth transistorized second source/drain electrode connects this second voltage level, the tenth transistorized grid connects this first clock signal, and the tenth transistorized first source/drain electrode connects the 8th transistorized grid;
The 11 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 11 transistorized second source/drain electrode connects this second voltage level, the 11 transistorized grid connects the output signal of this prime shift register, the 11 transistorized first source/drain electrode connects the 8th transistorized grid and the 3rd transistorized first source/drain electrode, if current shift register is a first order shift register, then its 11 transistorized grid connects a sensitizing pulse signal;
The tenth two-transistor has a grid, one first source/drain electrode and one second source/drain electrode, and wherein second of the tenth two-transistor source/drain electrode connects this second voltage level, and the grid of the tenth two-transistor connects this output terminal;
The 13 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 13 transistorized first source/drain electrode connects this output terminal, the 13 transistorized second source/drain electrode connects this second voltage level, and the 13 transistorized grid connects first source/drain electrode of the tenth two-transistor;
The 14 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 14 transistorized second source/drain electrode connects this second voltage level, the 14 transistorized grid connects the 13 transistorized grid, and the 14 transistorized first source/drain electrode connects the grid of this transistor seconds;
The 15 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 15 transistorized grid is connected this first clock signal with the 15 transistorized first source/drain electrode, and the 15 transistorized second source/drain electrode connects the 13 transistorized grid; And
The 16 transistor, have a grid, one first source/drain electrode and one second source/drain electrode, wherein the 16 transistorized second source/drain electrode connects this second voltage level, the 16 transistorized grid connects this second clock signal, and the 16 transistorized first source/drain electrode connects the 13 transistorized grid.
15. shift register circuit as claimed in claim 14, wherein these a plurality of transistors are nmos pass transistor, are formed on the glass substrate.
16. shift register circuit as claimed in claim 14, wherein these a plurality of transistors are amorphous silicon film transistor, are formed on the glass substrate.
17. shift register circuit as claimed in claim 15, wherein this second clock signal and first clock signal have 180 degree phase differential.
18. shift register circuit as claimed in claim 14, wherein this first clock signal has 50% or be lower than for 50% work period.
19. shift register circuit as claimed in claim 14, wherein this tertiary voltage level is lower than this second voltage level.
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