CN102693692B - Shift register unit and LCD (liquid crystal display) grid driving device - Google Patents
Shift register unit and LCD (liquid crystal display) grid driving device Download PDFInfo
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- CN102693692B CN102693692B CN201110074579.2A CN201110074579A CN102693692B CN 102693692 B CN102693692 B CN 102693692B CN 201110074579 A CN201110074579 A CN 201110074579A CN 102693692 B CN102693692 B CN 102693692B
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Abstract
The invention discloses a shift register unit and an LCD (liquid crystal display) grid driving device, which solve the problem that in the prior art, a shift register can not denoise when the CLK (clock) is at a high level. In the shift register unit, a denoising circuit when the CLK is at a high level is added based on a transistor structure in the prior art, thereby enhancing the denoising capacity and then increasing the operating stability of the shift register.
Description
Technical field
The present invention relates to liquid crystal display-driving technology, relate in particular to a kind of shift register cell and LCD device grid drive device.
Background technology
In prior art, shift register cell comprises 10 thin film transistor (TFT)s, and as shown in Figure 1 wherein, the grid of the first film transistor M1 is all connected with shift register start signal input end INPUT-1 with drain electrode, the drain electrode of the second thin film transistor (TFT) M2 is connected with the source electrode of the first film transistor M1, and the grid of the second thin film transistor (TFT) M2 is connected with reset signal input end RESETIN, and the source electrode of the second thin film transistor (TFT) M2 is connected with low level signal input end VSSIN, the drain electrode of the 3rd thin film transistor (TFT) M3 is connected with the first clock signal input terminal CLKIN, and the grid of the 3rd thin film transistor (TFT) M3 is connected with the source electrode of the first film transistor M1, and the source electrode of the 3rd thin film transistor (TFT) M3 is connected with signal output part OUT, the grid of the 4th thin film transistor (TFT) M4 is connected with reset signal input end RESETIN, and the drain electrode of the 4th thin film transistor (TFT) M4 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, and the source electrode of the 4th thin film transistor (TFT) M4 is connected with low level signal input end VSSIN, the grid of the 5th thin film transistor (TFT) M5 is all connected with second clock signal input part CLKBIN with drain electrode, the source electrode of the 5th thin film transistor (TFT) M5 is connected with the grid of the 7th thin film transistor (TFT) M7, the grid of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the first film transistor M1, the drain electrode of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the 5th thin film transistor (TFT) M5, the source electrode of the 6th thin film transistor (TFT) M6 is connected with low level signal input end VSSIN, the drain electrode of the 7th thin film transistor (TFT) M7 is connected with second clock signal input part CLKBIN, the source electrode of the 7th thin film transistor (TFT) M7 is connected with the grid of the tenth thin film transistor (TFT) M10 with the grid of the 9th thin film transistor (TFT) M9 respectively, the grid of the 8th thin film transistor (TFT) M8 is connected with the source electrode of the first film transistor M1, the drain electrode of the 8th thin film transistor (TFT) M8 is connected with the source electrode of the 7th thin film transistor (TFT) M7, the source electrode of the 8th thin film transistor (TFT) M8 is connected with low level signal input end VSSIN, the drain electrode of the 9th thin film transistor (TFT) M9 is connected with the source electrode of the first film transistor M1, the source electrode of the 9th thin film transistor (TFT) M9 is connected with low level signal input end VSSIN, the drain electrode of the tenth thin film transistor (TFT) M10 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, the source electrode of the tenth thin film transistor (TFT) M10 is connected with low level signal input end VSSIN.The place of converging of the source electrode of the first film transistor M1, the drain electrode of the second thin film transistor (TFT) M2, the drain electrode of the 9th thin film transistor (TFT) M5, the grid of the grid of the 6th thin film transistor (TFT) M6, the 8th thin film transistor (TFT) M8 and the grid of the 3rd thin film transistor (TFT) M3 is PU node, the place of converging of the grid of the grid of the drain electrode of the source electrode of the 7th thin film transistor (TFT) M7, the 8th thin film transistor (TFT) M8, the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10 is PD_ck node, and the place of converging of the grid of the source electrode of the 5th thin film transistor (TFT) M5 and the 7th thin film transistor (TFT) M7 is PD_CN_ck node.
Be illustrated in figure 2 the sequential chart of Fig. 1 shift register cell, in Fig. 1, shift register start signal input end INPUT-1 input start signal INPUT, the first clock signal input terminal CLKIN inputs the first clock signal clk, second clock signal input part CLKBIN inputs second clock signal CLKB (the first clock signal is the inversion signal of second clock signal), low voltage signal input end VSSIN input low voltage signal VSS, reset signal input end RESETIN input reset signal RESET, signal output part OUT output gate drive signal OUTPUT.Low voltage signal VSS is not shown in Fig. 2, and low voltage signal VSS is one and keeps low level signal always.This shift register is removed the transistor of noise and only when CLKB is high level, is opened, and cannot when CLK is high level, open denoising, a little less than making shift register denoising ability relatively, thereby affects the job stability of shift register.
Summary of the invention
The object of the invention is for the shift register existing in prior art cannot be when CLK be high level the problem of denoising, a kind of shift register cell and LCD device grid drive device are provided.
For achieving the above object, the invention provides a kind of shift register cell, comprising:
The first film transistor, its grid is connected with shift register start signal input end, and drain electrode is connected with first input end, and first input end is for when shift register start signal input end is high level, and port level is also the port of high level;
The second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of described the first film, and grid is connected with reset signal input end, and source electrode is connected with low level signal input end;
The 3rd thin film transistor (TFT), its drain electrode is connected with the first clock signal input terminal, and grid is connected with the transistorized source electrode of described the first film, and source electrode is connected with signal output part;
The 4th thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and grid is connected with described reset signal input end, and source electrode is connected with described low level signal input end;
The first clock signal input terminal and second clock signal input part;
With the first clock signal terminal and second clock signal end the first noise canceling circuit and second noise canceling circuit of corresponding setting one by one, described in each, noise canceling circuit includes:
Control circuit, connect with the corresponding transistorized source electrode of clock signal input terminal, the first film and low level signal input end, for the clock signal input terminal output high level signal corresponding, and the transistorized source electrode of the first film is when low level, exports a control signal;
Noise canceller circuit, be connected with described control circuit, also be connected with the source electrode of the transistorized source electrode of described the first film or the 3rd thin film transistor (TFT) simultaneously, for when receiving described control signal from described control electronic circuit, carry out noise cancellation operation, the noise of the transistorized source electrode of the first film that elimination is attached thereto and/or the source electrode of the 3rd thin film transistor (TFT).
The present invention also provides a kind of LCD device grid drive device, comprises a plurality of aforesaid shift register cell being deposited on LCD (Liquid Crystal Display) array substrate;
Except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells is all connected with the reset signal input end of a upper shift register cell that is adjacent the signal input part of next shift register cell and is adjacent, the signal output part of first shift register cell is connected with the signal input part of second shift register cell, the reset signal input end of the signal output part of last shift register cell and the upper shift register cell being adjacent and the reset signal input end of self are connected,
The signal input part incoming frame start signal of first shift register cell;
The first clock signal input terminal of odd number shift register cell is inputted the first clock signal, second clock signal input part input second clock signal, the first clock signal input terminal input second clock signal of even number shift register cell, second clock signal input part input system the first clock signal;
The low level signal input end input low level signal of each shift register cell.
The shift register cell that the embodiment of the present invention provides and LCD device grid drive device, the denoising circuit owing to having increased that CLK is high level, thus strengthened denoising ability, and then increased the job stability of shift register.
Accompanying drawing explanation
Figure 1 shows that a kind of shift register cell structural representation of the prior art;
Figure 2 shows that the sequential chart of Fig. 1 shift register cell;
Figure 3 shows that shift register cell embodiment mono-structural representation of the present invention;
Figure 4 shows that shift register cell embodiment bis-structural representations of the present invention;
Structural representation after the distortion of Fig. 5-Figure 7 shows that shift register cell shown in Fig. 4 of the present invention;
Figure 8 shows that the sequential chart of Fig. 4 shift register cell;
Figure 9 shows that shift register cell denoising effect schematic diagram of the present invention;
Figure 10 shows that shift register cell embodiment tri-structural representations of the present invention;
Figure 11 shows that shift register cell embodiment tetra-structural representations of the present invention;
Figure 12 shows that shift register cell embodiment five structural representations of the present invention;
Figure 13 shows that LCD device grid drive device structural representation of the present invention;
Figure 14 shows that the input and output sequential chart of LCD device grid drive device shown in Figure 13.
Embodiment
Fig. 3 is shift register cell embodiment mono-structural representation of the present invention, and the grid of the first film transistor M1 is all connected with shift register start signal input end INPUT-1 with drain electrode; The drain electrode of the second thin film transistor (TFT) M2 is connected with the source electrode of the first film transistor M1, and the grid of the second thin film transistor (TFT) M2 is connected with reset signal input end RESETIN, and the source electrode of the second thin film transistor (TFT) M2 is connected with low level signal input end VSSIN; The drain electrode of the 3rd thin film transistor (TFT) M3 is connected with the first clock signal input terminal CLKIN, and the grid of the 3rd thin film transistor (TFT) M3 is connected with the source electrode of the first film transistor M1, and the source electrode of the 3rd thin film transistor (TFT) M3 is connected with signal output part OUT; The grid of the 4th thin film transistor (TFT) M4 is connected with reset signal input end RESETIN, and the drain electrode of the 4th thin film transistor (TFT) M4 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, and the source electrode of the 4th thin film transistor (TFT) M4 is connected with low level signal input end VSSIN.
The first noise canceling circuit of shift register cell and the second noise canceling circuit and the first clock signal input terminal CLKIN and second clock signal input part CLKBIN corresponding setting one by one, described in each, noise canceling circuit includes: control circuit, connect with the corresponding transistorized source electrode of clock signal input terminal, the first film and low level signal input end, for the clock signal input terminal output high level signal corresponding, and the transistorized source electrode of the first film is when low level, export a control signal; Noise canceller circuit, be connected with described control circuit, also be connected with the source electrode of the transistorized source electrode of described the first film or the 3rd thin film transistor (TFT) simultaneously, for when receiving described control signal from described control electronic circuit, carry out noise cancellation operation, the noise of the transistorized source electrode of the first film that elimination is attached thereto and/or the source electrode of the 3rd thin film transistor (TFT).
Wherein, the first noise canceling circuit comprises, first control circuit 11 and the first noise canceller circuit 12, the first control input end of first control circuit 11 is connected with the first clock signal input terminal, the second control input end of first control circuit 11 is connected with the transistorized source electrode of the first film, the output terminal of first control circuit 11 is connected with the control signal input end of the first noise canceller circuit, the noise output terminal of the first noise canceller circuit 12 is connected with described low level signal input end, the first noise inputs end of the first noise canceller circuit 12 is connected with the source electrode of described the 3rd thin film transistor (TFT) and/or the transistorized source electrode of described the first film, first control circuit 11, be used in the first clock signal in high level, the transistorized source electrode of the first film is when low level, send the first control signal, the first noise canceller circuit 12, for the source electrode of the transistorized source electrode of low level signal input end and the first film and/or the 3rd thin film transistor (TFT) being connected according to the first control signal,
The second noise canceling circuit comprises, second control circuit 21 and the second noise canceller circuit 22, the 3rd control input end of second control circuit 21 is connected with second clock signal input part, the 4th control input end of second control circuit 21 is connected with the transistorized source electrode of the first film, the output terminal of second control circuit 21 is connected with the control signal input end of the second noise canceller circuit, the noise output terminal of the second noise canceller circuit 22 is connected with described low level signal input end, the second noise inputs end of the second noise canceller circuit 22 is connected with the source electrode of described the 3rd thin film transistor (TFT) and/or the transistorized source electrode of described the first film, second control circuit 21, be used at second clock signal in high level, the transistorized source electrode of the first film is when low level, send the second control signal, the second noise canceller circuit 22, for according to the second control signal by low level signal input end with, the source electrode of the transistorized source electrode of the first film and/or the 3rd thin film transistor (TFT) connects.
Fig. 4 is shift register cell embodiment bis-structural representations of the present invention, and as preferred scheme, second control circuit comprises: the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7 and the 8th thin film transistor (TFT) M8; The second noise canceller circuit comprises: the 9th thin film transistor (TFT) M9 and/or the tenth thin film transistor (TFT) M10; First control circuit comprises: the 11 thin film transistor (TFT) M11, the 12 thin film transistor (TFT) M12, the 13 thin film transistor (TFT) M13 and the 14 thin film transistor (TFT) M14; The first noise canceller circuit comprises: the 15 thin film transistor (TFT) M15 and/or the 16 thin film transistor (TFT) M16.
The grid of the 5th thin film transistor (TFT) M5 is all connected with second clock signal input part CLKBIN with drain electrode, the source electrode of the 5th thin film transistor (TFT) M5 is connected with the grid of the 7th thin film transistor (TFT) M7, the grid of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the first film transistor M1, the drain electrode of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the 5th thin film transistor (TFT) M5, the source electrode of the 6th thin film transistor (TFT) M6 is connected with low level signal input end VSSIN, the drain electrode of the 7th thin film transistor (TFT) M7 is connected with second clock signal input part CLKBIN, the source electrode of the 7th thin film transistor (TFT) M7 is connected with the grid of the tenth thin film transistor (TFT) M10 with the grid of the 9th thin film transistor (TFT) M9 respectively, the grid of the 8th thin film transistor (TFT) M8 is connected with the source electrode of the first film transistor M1, the drain electrode of the 8th thin film transistor (TFT) M8 is connected with the source electrode of the 7th thin film transistor (TFT) M7, the source electrode of the 8th thin film transistor (TFT) M8 is connected with low level signal input end VSSIN, the drain electrode of the 9th thin film transistor (TFT) M9 is connected with the source electrode of the first film transistor M1, the source electrode of the 9th thin film transistor (TFT) M9 is connected with low level signal input end VSSIN, the drain electrode of the tenth thin film transistor (TFT) M10 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, the source electrode of the tenth thin film transistor (TFT) M10 is connected with low level signal input end VSSIN, the grid of the 11 thin film transistor (TFT) M11 is all connected with the first clock signal input terminal CLKIN with drain electrode, the source electrode of the 11 thin film transistor (TFT) M11 is connected with the grid of the 13 thin film transistor (TFT) M13, the grid of the 12 thin film transistor (TFT) M12 is connected with the source electrode of the first film transistor M1, the drain electrode of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the 5th thin film transistor (TFT) M5, the source electrode of the 12 thin film transistor (TFT) M12 is connected with low level signal input end VSSIN, the drain electrode of the 13 thin film transistor (TFT) M13 is connected with the first clock signal input terminal CLKIN, the source electrode of the 13 thin film transistor (TFT) M13 is connected with the grid of the 16 thin film transistor (TFT) M16 with the grid of the 15 thin film transistor (TFT) M15 respectively, the grid of the 14 thin film transistor (TFT) M14 is connected with the source electrode of the first film transistor M1, the drain electrode of the 14 thin film transistor (TFT) M14 is connected with the source electrode of the 13 thin film transistor (TFT) M13, the source electrode of the 14 thin film transistor (TFT) M14 is connected with low level signal input end VSSIN, the drain electrode of the 15 thin film transistor (TFT) M15 is connected with the source electrode of the first film transistor M1, the source electrode of the 15 thin film transistor (TFT) M15 is connected with low level signal input end VSSIN, the drain electrode of the 16 thin film transistor (TFT) M16 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, the source electrode of the 16 thin film transistor (TFT) M16 is connected with low level signal input end VSSIN.The source electrode of the first film transistor M1, the drain electrode of the second thin film transistor (TFT) M2, the drain electrode of the 9th thin film transistor (TFT) M5, the grid of the 6th thin film transistor (TFT) M6, the place of converging of the grid of the grid of the 8th thin film transistor (TFT) M8 and the 3rd thin film transistor (TFT) M3 is PU node, the source electrode of the 7th thin film transistor (TFT) M7, the drain electrode of the 8th thin film transistor (TFT) M8, the place of converging of the grid of the grid of the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10 is PD_ckb node, the place of converging of the grid of the source electrode of the 5th thin film transistor (TFT) M5 and the 7th thin film transistor (TFT) M7 is PD_CN_ckb node, the source electrode of the 13 thin film transistor (TFT) M13, the drain electrode of the 14 thin film transistor (TFT) M14, the place of converging of the 15 grid of thin film transistor (TFT) M15 and the grid of the 16 thin film transistor (TFT) M16 is PD_ck node, the place of converging of the 11 source electrode of thin film transistor (TFT) M11 and the grid of the 13 thin film transistor (TFT) M13 is PD_CN_ck node.
In Fig. 4, adopt thin film transistor (TFT) M5-M16 to build control circuit and the noise canceller circuit of shift register cell, it is a preferred scheme in the present embodiment, as the deformation program of Fig. 4 scheme as shown in Figure 5, wherein control circuit can also be the 7th thin film transistor (TFT) M7 and the 8th thin film transistor (TFT) M8 removing in Fig. 4, only adopt the 5th thin film transistor (TFT) M5 and the 6th thin film transistor (TFT) M6 to build, now the grid of the 9th thin film transistor (TFT) M9 is connected with the 5th thin film transistor (TFT) M5 source electrode.Deformation program as Fig. 4 scheme can also be as shown in Figure 6, remove the 7th thin film transistor (TFT) M7 in Fig. 4, only adopt the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6 to build and the 8th thin film transistor (TFT) M8, now drain electrode all with five thin film transistor (TFT) M5 source electrode of the grid of the 9th thin film transistor (TFT) M9, the 8th thin film transistor (TFT) M8 is connected.As shown in Figure 7, be with the difference of Fig. 5, noise canceller circuit can also be built by the 9th thin film transistor (TFT) M9 and the 9th backup thin film transistor (TFT) M9 ', the drain electrode of the 9th thin film transistor (TFT) M9 is connected with the drain electrode of the 9th backup thin film transistor (TFT) M9 ', the grid of the 9th thin film transistor (TFT) M9 is connected with the grid of the 9th backup thin film transistor (TFT) M9 ', and the source electrode of the 9th thin film transistor (TFT) M9 is connected with the source electrode of the 9th backup thin film transistor (TFT) M9 '.At the tenth thin film transistor (TFT) M10, the 15 thin film transistor (TFT) M15 and the 16 thin film transistor (TFT) M16, add similar circuit and can realize too noise canceller circuit, no matter adopt as can be seen here any one circuit as Fig. 4 to Fig. 7, can realize aforesaid control circuit and noise canceller circuit.
Certainly the present embodiment adopts is that the transistor of N-shaped is realized aforesaid control circuit and noise canceller circuit, just as preferred embodiment, similarly adopting the transistor of p-type or mixing N-shaped p-type equally also can implement, is that those skilled in the art are easy to just can complete, and repeats no more herein.
The structural difference part of shift register cell shown in shift register cell provided by the invention and Fig. 1 is: increased squelch circuit when CLK is high level, this squelch circuit comprises the tenth thin film transistor (TFT) M10, the 11 thin film transistor (TFT) M11, the 12 thin film transistor (TFT) M12, the 13 thin film transistor (TFT) M13, the 14 thin film transistor (TFT) M14, the 15 thin film transistor (TFT) M15 and the 16 thin film transistor (TFT) M16.
Be illustrated in figure 8 the sequential chart of Fig. 4 shift register cell, the principle of work of shift register cell of the present invention is described below in conjunction with Fig. 4 and Fig. 8.
Select a part for sequential chart shown in Fig. 8 and be divided into double teacher.
In the I stage, INPUT is high level, and RESET is low level, and PU node is high level, transistor M1, M3, M6, M8, M12 and M14 conducting; CLK is low level, M11, M13 cut-off, and PD_CN_ck and PD_ck are low level, M15, M16 cut-off; CLKB is high level, and transistor M5 conducting, by the ratio of M5/M6 channel width-over-length ratio is set, makes PD_ckb node approach low level, and then transistor M9 and M10 cut-off; RESET is low level, transistor M2, M4 cut-off; Due to transistor M4, M10, M16 cut-off, M3 conducting output equals CLK, so CLK is low level, is output as low level.
In the I I stage, INPUT becomes low level, and RESET is still low level, and PU node is still high level, still conducting of transistor M3, M6, M8, M12, M14; CLKB becomes low level, transistor M5, M7 cut-off, and node PD_ckb is still low level so, transistor M9 and M10 still end; RESET is still low level, and transistor M2, M4 still end; CLK becomes high level, and M11 conducting, by arranging the ratio of M11/M12 channel width-over-length ratio, making PD_ck node is low level, and then transistor M15 and M16 cut-off, due to transistor M4, M10, M16 cut-off, M3 conducting output equals CLK, so CLK is high level output, becomes high level.
In the III stage, INPUT is still low level, transistor M1 cut-off; RESET becomes high level, transistor M2, M4 conducting; So PU node is discharged to low level, transistor M3, M6, M8, M12, M14 cut-off; CLKB is high level, transistor M5, M7 conducting, and node PD_ckb becomes high level so, transistor M9, M10 conducting; CLK is low level, M11, M13 cut-off, and PD_ck is low level, M15, M16 cut-off; Due to M3 cut-off, transistor M4, M10, M16 conducting output equal low level VSS, so output becomes low level.
In the IV stage, INPUT is still low level, transistor M1 cut-off; RESET becomes low level, transistor M2, M4 cut-off; PU node is still low level, and transistor M3, M6, M8, M12, M14 still end; CLKB is low level, transistor M5, M7 cut-off, and node PD_ckb level is reduced gradually by peak so, and transistor M9, M10 are ended gradually by maximum conducting; CLK becomes high level, M11, M13 conducting, and PD_ck node becomes high level, and transistor M15 and M16 conducting (now,, if PU node has noise, can bleed off by M15; If output has noise, can bleed off by M16), due to transistor M3, M4 cut-off, so output keeps low level.
In the V stage, INPUT is still low level, transistor M1 cut-off; RESET is still low level, transistor M2, M4 cut-off; PU node is still low level, and transistor M3, M6, M8, M12, M14 still end; CLKB is high level, transistor M5, M7 conducting, and node PD_ckb level is raise gradually by minimum point so, and transistor M9, M10 (now,, if PU node has noise, can bleed off by M9 to maximum conducting by closing gradually; If output has noise, can bleed off by M10); CLK is low level, M11, M13 cut-off, and PD_ck is low level, M15, M16 cut-off; Due to transistor M3, M4 cut-off, so output remains low level.
In this double teacher, I stage shift register start signal input end INPUT-1 input start signal INPUT is high level, the gate drive signal OUTPUT of II stage signal output terminal OUT output is high level, complete once displacement, the reset signal RESET of III stage reset signal input end RESETIN end input is high level, complete the operation of reset, so can be by I, II, III stage definitions is the working time of shift register cell, the 4th, five-stage, the initial INPUT of shift register start signal input end INPUT-1 input signal, the reset signal RESET of reset signal input end RESETIN end input is low level, so can be by IV, V stage definitions is the non-working time of shift register cell.After this double teacher, repeat IV, the state in V stage, until again there is I, II, the sequential in III stage always.Complete I, II, III stage, completed once displacement.In Fig. 8, only drawn the part sequential chart of shift register cell, every demonstration one two field picture of liquid crystal display, control the shift register cell of certain a line liquid crystal pixel and all can export a high level signal, the initial INPUT of shift register start signal input end INPUT-1 input signal, the first clock signal clk of the reset signal RESET of reset signal input end RESETIN input and the first clock signal input terminal CLKIN input all can repeat an order I, II, the input timing in III stage, in liquid crystal display, show in the time of a two field picture, except I, II, III all the other times outside the stage, shift register start signal input end INPUT-1 input start signal INPUT, the reset signal RESET of reset signal input end RESETIN input can repeat and the 4th input timing identical with five-stage with the first clock signal clk of the first clock signal input terminal CLKIN input.
From above to finding out the detailed description of double teacher, in fourth stage, CLK becomes high level, M11 conducting, PU node becomes low level, M12 and M13 cut-off, M13 conducting, so PD_ck node becomes high level, transistor M15 and M16 conducting, now, if PU node has noise, can bleed off by M15; If output has noise, can bleed off by M16.Similarly at five-stage, CLKB is high level, transistor M5, PU node is still low level, M6 and M8 cut-off, M13 conducting, node PD_ckb level is raise gradually by minimum point so, transistor M9, M10, by closing gradually to maximum conducting now, if PU node has noise, can bleed off by M9; If output has noise, can bleed off by M10.
Compare with shift register cell of the prior art as shown in Figure 1, in shift register cell provided by the invention, increased denoising circuit when CLK is high level, can avoid in fourth stage by noise like this, thereby strengthened denoising ability, and then increased the job stability of shift register, Fig. 9 is that in the embodiment of the present invention, shift register improves front and back output noise comparison, from Fig. 9, can obviously find out, compare with the noise level 200 before improving, noise level 100 after improvement, output noise obviously reduces.
Figure 10 is shift register cell embodiment tri-structural representations of the present invention, adds capacitor C 1, can further strengthen the denoising ability of shift register cell, thereby strengthens the job stability of shift register.Due to C1, increased on the one hand the total capacitance of PU node, reduced the proportion of the 3rd transistor M3 drain parasitic capacitance Cgd3 at PU node, thereby can reduce the noise that the first clock signal input terminal CLKIN is coupled to PU node by stray capacitance Cgd3, and then the noise being indirectly coupled to signal output part OUT also can reduce, simultaneously, the 3rd thin film transistor (TFT) M3 leakage current also can correspondingly reduce, and the noise of signal output part OUT can further reduce.
Be shift register cell embodiment tetra-structural representations of the present invention as shown in figure 11, this embodiment has increased by the 17 thin film transistor (TFT) M17 on the basis of the shift register cell shown in Fig. 4.The grid of the 17 thin film transistor (TFT) M17 is connected with second clock signal input part CLKBIN, and drain electrode is connected with shift register start signal input end INPUT-1, and source electrode is connected with PU node.In this embodiment, in the first stage, when second clock signal CLKB is high level, the 17 thin film transistor (TFT) M17 conducting, due to shift register start signal input end INPUT-1 input start signal, INPUT is high level, the source electrode of the 17 thin film transistor (TFT) M17 is high level, the rise time of the level that adds the signal of locating output that can reduce PU node of the 17 thin film transistor (TFT) M17, make the rising edge of the signal at PU node place become precipitous, thereby reduce the rise time of the gate drive signal of signal output part OUT output.
Be shift register cell embodiment five structural representations of the present invention as shown in figure 12, this embodiment has increased the input end VDDIN of a DC high voltage VDD on the basis of the shift register cell shown in Fig. 4, connect respectively the drain electrode of M1, M5, M7, M11, M13, also can only connect wherein part, as M1, M5, M11, like this can be along the serviceable life of long M9, M10, M15, M16.
No matter be the shift register cell shown in Fig. 4, or the shift register cell shown in Figure 12, the input end that drain electrode connects for the first film transistor M1, this input end is for when shift register start signal input end INPUT-1 is high level, also for the port of high level, (Fig. 4 is shift register start signal input end INPUT-1 to port level, Figure 12 is the input end VDDIN of DC high voltage VDD), the input end connecting for the 5th thin film transistor (TFT) M5 drain electrode, this input end is for when second clock signal input part CLKBIN is high level, also for the port of high level, (Fig. 4 is second clock signal input part CLKBIN to port level, Figure 12 is the input end VDDIN of DC high voltage VDD), the input end connecting for the 7th thin film transistor (TFT) M7 drain electrode, this input end is for when second clock signal input part CLKBIN is high level, also for the port of high level, (Fig. 4 is second clock signal input part CLKBIN to port level, Figure 12 is the input end VDDIN of DC high voltage VDD), the input end connecting for the 11 thin film transistor (TFT) M11 drain electrode, this input end is for when the first clock signal input terminal CLKIN is high level, also for the port of high level, (Fig. 4 is second clock signal input part CLKIN to port level, Figure 12 is the input end VDDIN of DC high voltage VDD), the input end connecting for the 13 thin film transistor (TFT) M13 drain electrode, this input end is for when the first clock signal input terminal CLKIN is high level, also for the port of high level, (Fig. 4 is second clock signal input part CLKIN to port level, Figure 12 is the input end VDDIN of DC high voltage VDD).
Be LCD device grid drive device structural representation of the present invention as shown in figure 13, be the input and output sequential chart of LCD device grid drive device shown in Figure 13 as shown in figure 14, STV is frame start signal, STV is only input to the shift register start signal input end INPUT-1 of the first shift register cell, low level signal VSS (not shown VSS in Figure 14) is input to the low level signal input end VSSIN of each shift register cell, the first clock signal input terminal CLKIN of odd number shift register cell inputs the first clock signal clk, second clock signal input part CLKBIN input second clock signal CLK, the first clock signal input terminal CLKIN input second clock signal CLKB of even number shift register cell, second clock signal input part CLKBIN input system the first clock signal clk, except first shift register cell and last shift register cell, the signal output part of each shift register cell is all connected with the shift register start signal input end INPUT-1 of the reset signal input end RETSETIN of the upper shift register cell being adjacent and next shift register of being adjacent, the signal output part OUT of first shift register cell is only connected with the shift register start signal input end INPUT-1 of second shift register cell, the output terminal OUT of last shift register cell (the n+1 shift register cell in figure as shown in figure 13) is connected with the reset signal input end RETSETIN of n the shift register cell being adjacent and the reset signal input end RETSETIN of self respectively, wherein n is positive integer.
Thin Film Transistor-LCD adopts the mode of lining by line scan, grid with the thin film transistor (TFT) being connected with liquid crystal pixel in a line is all connected with same shift register cell, and the shift register cell in LCD device grid drive device can be controlled conducting and the cut-off of the whole thin film transistor (TFT)s in colleague.In Figure 13, the concrete principle of LCD device grid drive device is: supposing has the capable pixel of n in panel of LCD, sequential chart shown in Figure 14, is input to the shift register start signal input end INPUT-1 of the first shift register cell in first stage frame start signal; Subordinate phase, the signal output part OUT output high level signal OUTPUT1 of the first shift register cell, this high level signal OUTPUT1 is input to the shift register start signal input end INPUT-1 of the second shift register cell simultaneously; Phase III, the signal output part OUT output high level signal OUTPUT2 of the second shift register cell, after this each shift register cell is exported high level signal successively, and for controlling the conducting of the thin film transistor (TFT) of going together being connected with this shift register cell, principle is with second and third stage; To fourth stage, n shift register cell output high level signal OUTPUTn, the high level signal OUTPUTn of n shift register cell output is as the input start signal of the shift register start signal input end INPUT-1 of n+1 shift register cell simultaneously; Five-stage, n+1 shift register cell output high level signal OUTPUTn+1, the high level signal OUTPUTn+1 of this n+1 shift register cell output is not used in driving load, the thin film transistor (TFT) of one-row pixels is controlled in the i.e. not responsible driving of n+1 shift register cell, and the high level signal OUTPUTn+1 of its output is only for as n shift register cell and the reset signal of himself.Each shift register cell in Figure 13 can be the shift register cell as shown in Fig. 4, Fig. 5, Fig. 6, Fig. 7, Figure 10, Figure 11 or Figure 12.
In Figure 13, last shift register cell, n+1 shift register cell is not used in driving load, can be regarded as redundancy shift register cell.In gate drive apparatus shown in Figure 13, only include a redundancy shift register cell, in fact, can also comprise more redundancy shift register cells, each redundancy shift register cell can combine and guarantee that LCD device grid drive device resets more reliably.
The shift register cell that the embodiment of the present invention provides and LCD device grid drive device, the denoising circuit owing to having increased that CLK is high level (comprises M11, M12, M13, M14, M15 and M16), in the IV stage, transistor M3, M4 cut-off, output keeps low level, CLK becomes high level, M11, M13 conducting, and PD_ck node becomes high level, transistor M15 and M16 conducting, now, if PU node has noise, can bleed off by M15; If output has noise, can bleed off by M16, thereby strengthen denoising ability, and then increase the job stability of shift register.
Finally it should be noted that: above embodiment is only in order to technical scheme of the present invention to be described but not be limited, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that: it still can be modified or be equal to replacement technical scheme of the present invention, and these modifications or be equal to replacement and also can not make amended technical scheme depart from the spirit and scope of technical solution of the present invention.
Claims (10)
1. a shift register cell, is characterized in that, comprising:
The first film transistor, its grid is connected with shift register start signal input end, and drain electrode is connected with first input end, and first input end is for when shift register start signal input end is high level, and port level is also the port of high level;
The second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of described the first film, and grid is connected with reset signal input end, and source electrode is connected with low level signal input end;
The 3rd thin film transistor (TFT), its drain electrode is connected with the first clock signal input terminal, and grid is connected with the transistorized source electrode of described the first film, and source electrode is connected with signal output part;
The 4th thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and grid is connected with described reset signal input end, and source electrode is connected with described low level signal input end;
The first clock signal input terminal and second clock signal input part;
With the first clock signal input terminal and second clock signal input part the first noise canceling circuit and second noise canceling circuit of corresponding setting one by one, described in each, noise canceling circuit includes:
Control circuit, connect with the corresponding transistorized source electrode of clock signal input terminal, the first film and low level signal input end, for the clock signal input terminal output high level signal corresponding, and the transistorized source electrode of the first film is when low level, exports a control signal;
And, noise canceller circuit, be connected with described control circuit, also be connected with the source electrode of the transistorized source electrode of described the first film or the 3rd thin film transistor (TFT) simultaneously, for when receiving described control signal from described control circuit, carry out noise cancellation operation, the noise of the transistorized source electrode of the first film that elimination is attached thereto and/or the source electrode of the 3rd thin film transistor (TFT).
2. shift register cell according to claim 1, is characterized in that,
Described the second noise canceling circuit comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT), also comprise the 9th thin film transistor (TFT) and/or the tenth thin film transistor (TFT);
Described the first noise canceling circuit comprises: the 11 thin film transistor (TFT), the 12 thin film transistor (TFT), the 13 thin film transistor (TFT) and the 14 thin film transistor (TFT), also comprise the 15 thin film transistor (TFT) and/or the 16 thin film transistor (TFT);
The 5th thin film transistor (TFT), its grid is connected with described second clock signal input part, and source electrode is connected with the grid of described the 7th thin film transistor (TFT), and drain electrode is connected with the second input end, the second input end is for when second clock signal input part is high level, and port level is also the port of high level;
The 6th thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 5th thin film transistor (TFT), and grid is connected with the transistorized source electrode of described the first film, and source electrode is connected with described low level signal input end;
The 7th thin film transistor (TFT), its drain electrode is connected with the 3rd input end, the 3rd input end is for when second clock signal input part is high level, and port level is also the port of high level, and source electrode is connected with the grid of described the tenth thin film transistor (TFT) with the grid of described the 9th thin film transistor (TFT) respectively;
The 8th thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 7th thin film transistor (TFT), and grid is connected with the transistorized source electrode of described the first film, and source electrode is connected with described low level signal input end;
The 9th thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of described the first film, and source electrode is connected with described low level signal input end;
The tenth thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with described low level signal input end;
The 11 thin film transistor (TFT), its grid is connected with described the first clock signal input terminal, and source electrode is connected with the grid of described the 13 thin film transistor (TFT), and drain electrode is connected with four-input terminal, four-input terminal is for when the first clock signal input terminal is high level, and port level is also the port of high level;
The 12 thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 11 thin film transistor (TFT), and grid is connected with the transistorized source electrode of described the first film, and source electrode is connected with described low level signal input end;
The 13 thin film transistor (TFT), its drain electrode is connected with the 5th input end, the 5th input end is for when the first clock signal input terminal is high level, and port level is also the port of high level, and source electrode is connected with the grid of described the 16 thin film transistor (TFT) with the grid of described the 15 thin film transistor (TFT) respectively;
The 14 thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 13 thin film transistor (TFT), and grid is connected with the transistorized source electrode of described the first film, and source electrode is connected with described low level signal input end;
The 15 thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of described the first film, and source electrode is connected with described low level signal input end;
The 16 thin film transistor (TFT), its drain electrode is connected with the source electrode of described the 3rd thin film transistor (TFT), and source electrode is connected with described low level signal input end.
3. shift register cell according to claim 2, is characterized in that, first input end, the second input end, the 3rd input end, four-input terminal and the 5th input end are all high level signal input end.
4. shift register cell according to claim 2, it is characterized in that, first input end is shift register start signal input end, the second input end is that second clock signal input part, the 3rd input end are that second clock signal input part, four-input terminal are the first clock signal input terminal, and the 5th input end is the first clock signal input terminal.
5. shift register cell according to claim 2, it is characterized in that, first input end is shift register start signal input end, the second input end is second clock signal input part, four-input terminal is the first clock signal input terminal, and the 3rd input end and the 5th input end are high level signal input end.
6. according to the shift register cell described in arbitrary claim in claim 1-5, it is characterized in that, also comprise electric capacity, the two ends of described electric capacity are connected with described signal output part with the grid of described the 3rd thin film transistor (TFT) respectively.
7. shift register cell according to claim 6, it is characterized in that, also comprise the 17 thin film transistor (TFT), its drain electrode is connected with described shift register start signal input end, grid is connected with described second clock signal input part, and source electrode is connected with the transistorized source electrode of described the first film.
8. according to the shift register cell described in arbitrary claim in claim 2-5, it is characterized in that, when the level value of second clock signal and the first film transistor source is high level, make the level value of the source electrode of the 7th thin film transistor (TFT) approach low level, and then to cause the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT) be cut-off state; When the level value of the first clock signal and the first film transistor source is high level, make the level value of the source electrode of the 7th thin film transistor (TFT) approach low level, and then to cause the 15 thin film transistor (TFT) and the 16 thin film transistor (TFT) be cut-off state.
9. shift register cell according to claim 8, is characterized in that, the ratio between the breadth length ratio of described the 5th thin film transistor channel and the breadth length ratio of the 6th thin film transistor channel is 1～1/50; Ratio between described the 11 breadth length ratio of thin film transistor channel and the breadth length ratio of the 12 thin film transistor channel is 1～1/50.
10. a LCD device grid drive device, is characterized in that, comprises a plurality of shift register cells as described in arbitrary claim in claim 1～9 that are deposited on LCD (Liquid Crystal Display) array substrate;
Except first shift register cell and last shift register cell, the shift register output end of all the other each shift register cells is all connected with the reset signal input end of a upper shift register cell that is adjacent the shift register start signal input end of next shift register cell and is adjacent, the shift register output end of first shift register cell is connected with the shift register start signal input end of second shift register cell, the reset signal input end of the shift register output end of last shift register cell and the upper shift register cell being adjacent and the reset signal input end of self are connected,
The shift register start signal input end incoming frame start signal of first shift register cell;
The first clock signal input terminal of odd number shift register cell is inputted the first clock signal, second clock signal input part input second clock signal, the first clock signal input terminal input second clock signal of even number shift register cell, second clock signal input part input system the first clock signal;
The low level signal input end input low level signal of each shift register cell.
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| CN105528986B (en) | 2016-02-03 | 2018-06-01 | 京东方科技集团股份有限公司 | Denoising method, denoising device, gate driving circuit and display device |
| CN105632446B (en) | 2016-03-30 | 2019-10-18 | 京东方科技集团股份有限公司 | GOA unit and its driving method, GOA circuit, display device |
| CN105741740B (en) * | 2016-04-27 | 2019-11-08 | 京东方科技集团股份有限公司 | GOA unit and its driving method, GOA circuit, display device |
| CN105976786B (en) * | 2016-07-21 | 2018-04-20 | 京东方科技集团股份有限公司 | Drive element of the grid and its driving method, gate driving circuit and display device |
| CN106531112B (en) * | 2017-01-03 | 2019-01-11 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, shift register and display device |
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| CN100397468C (en) * | 2005-08-31 | 2008-06-25 | 友达光电股份有限公司 | Shift register circuit |
| KR101192777B1 (en) * | 2005-12-02 | 2012-10-18 | 엘지디스플레이 주식회사 | A shift register |
| CN101546607B (en) * | 2008-03-26 | 2012-02-29 | 北京京东方光电科技有限公司 | Shift register and grid driving device for liquid crystal display |
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