CN102693692A - Shift register unit and LCD (liquid crystal display) grid driving device - Google Patents
Shift register unit and LCD (liquid crystal display) grid driving device Download PDFInfo
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- CN102693692A CN102693692A CN2011100745792A CN201110074579A CN102693692A CN 102693692 A CN102693692 A CN 102693692A CN 2011100745792 A CN2011100745792 A CN 2011100745792A CN 201110074579 A CN201110074579 A CN 201110074579A CN 102693692 A CN102693692 A CN 102693692A
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Abstract
The invention discloses a shift register unit and an LCD (liquid crystal display) grid driving device, which solve the problem that in the prior art, a shift register can not denoise when the CLK (clock) is at a high level. In the shift register unit, a denoising circuit when the CLK is at a high level is added based on a transistor structure in the prior art, thereby enhancing the denoising capacity and then increasing the operating stability of the shift register.
Description
Technical field
The present invention relates to the liquid crystal display-driving technology, relate in particular to a kind of shift register cell and LCD device grid drive device.
Background technology
Shift register cell comprises 10 thin film transistor (TFT)s in the prior art, and is wherein as shown in Figure 1, and the grid of the first film transistor M1 all is connected with shift register start signal input end INPUT-1 with drain electrode; The drain electrode of the second thin film transistor (TFT) M2 is connected with the source electrode of the first film transistor M1, and the grid of the second thin film transistor (TFT) M2 is connected with reset signal input end RESETIN, and the source electrode of the second thin film transistor (TFT) M2 is connected with low level signal input end VSSIN; The drain electrode of the 3rd thin film transistor (TFT) M3 is connected with the first clock signal input terminal CLKIN, and the grid of the 3rd thin film transistor (TFT) M3 is connected with the source electrode of the first film transistor M1, and the source electrode of the 3rd thin film transistor (TFT) M3 is connected with signal output part OUT; The grid of the 4th thin film transistor (TFT) M4 is connected with reset signal input end RESETIN, and the drain electrode of the 4th thin film transistor (TFT) M4 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, and the source electrode of the 4th thin film transistor (TFT) M4 is connected with low level signal input end VSSIN; The grid of the 5th thin film transistor (TFT) M5 all is connected with second clock signal input part CLKBIN with drain electrode; The source electrode of the 5th thin film transistor (TFT) M5 is connected with the grid of the 7th thin film transistor (TFT) M7; The grid of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the first film transistor M1; The drain electrode of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the 5th thin film transistor (TFT) M5; The source electrode of the 6th thin film transistor (TFT) M6 is connected with low level signal input end VSSIN; The drain electrode of the 7th thin film transistor (TFT) M7 is connected with second clock signal input part CLKBIN, and the source electrode of the 7th thin film transistor (TFT) M7 is connected with the grid of the 9th thin film transistor (TFT) M9 and the grid of the tenth thin film transistor (TFT) M10 respectively, and the grid of the 8th thin film transistor (TFT) M8 is connected with the source electrode of the first film transistor M1; The drain electrode of the 8th thin film transistor (TFT) M8 is connected with the source electrode of the 7th thin film transistor (TFT) M7; The source electrode of the 8th thin film transistor (TFT) M8 is connected with low level signal input end VSSIN, and the drain electrode of the 9th thin film transistor (TFT) M9 is connected with the source electrode of the first film transistor M1, and the source electrode of the 9th thin film transistor (TFT) M9 is connected with low level signal input end VSSIN; The drain electrode of the tenth thin film transistor (TFT) M10 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, and the source electrode of the tenth thin film transistor (TFT) M10 is connected with low level signal input end VSSIN.The place of converging of the grid of the drain electrode of the source electrode of the first film transistor M1, the drain electrode of the second thin film transistor (TFT) M2, the 9th thin film transistor (TFT) M5, the grid of the 6th thin film transistor (TFT) M6, the 8th thin film transistor (TFT) M8 and the grid of the 3rd thin film transistor (TFT) M3 is the PU node; The place of converging of the grid of the grid of the drain electrode of the source electrode of the 7th thin film transistor (TFT) M7, the 8th thin film transistor (TFT) M8, the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10 is the PD_ck node, and the place of converging of the grid of the source electrode of the 5th thin film transistor (TFT) M5 and the 7th thin film transistor (TFT) M7 is the PD_CN_ck node.
Be illustrated in figure 2 as the sequential chart of Fig. 1 shift register cell; Among Fig. 1; Shift register start signal input end INPUT-1 input start signal INPUT; The first clock signal input terminal CLKIN imports first clock signal clk, and second clock signal input part CLKBIN imports second clock signal CLKB (first clock signal is the inversion signal of second clock signal), low voltage signal input end VSSIN input low voltage signal VSS; Reset signal input end RESETIN input reset signal RESET, signal output part OUT output gate drive signal OUTPUT.Low voltage signal VSS is not shown among Fig. 2, and low voltage signal VSS is one and keeps low level signal always.The transistor that this shift register is removed noise is only opened during for high level at CLKB, can't open denoising during for high level at CLK, make shift register denoising ability relatively a little less than, thereby influence the job stability of shift register.
Summary of the invention
The objective of the invention is to the shift register that exists in the prior art can't be when CLK be high level the problem of denoising, a kind of shift register cell and LCD device grid drive device are provided.
For realizing above-mentioned purpose, the invention provides a kind of shift register cell, comprising:
The first film transistor, its grid is connected with shift register start signal input end, and drain electrode is connected with first input end, and first input end is for when shift register start signal input end is high level, and the port level also is the port of high level;
Second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of said the first film, and grid is connected with the reset signal input end, and source electrode is connected with the low level signal input end;
The 3rd thin film transistor (TFT), its drain electrode is connected with first clock signal input terminal, and grid is connected with the transistorized source electrode of said the first film, and source electrode is connected with signal output part;
The 4th thin film transistor (TFT), its drain electrode is connected with the source electrode of said the 3rd thin film transistor (TFT), and grid is connected with said reset signal input end, and source electrode is connected with said low level signal input end;
First clock signal input terminal and second clock signal input part;
With first noise canceling circuit and second noise canceling circuit of first clock signal terminal and the corresponding one by one setting of second clock signal end, each said noise canceling circuit includes:
Control circuit; Connect with corresponding transistorized source electrode of clock signal input terminal, the first film and low level signal input end; Be used at the clock signal input terminal of correspondence output high level signal, and the transistorized source electrode of the first film is exported a control signal when being in low level;
Noise canceller circuit; Be connected with said control circuit; Also be connected simultaneously with the source electrode of transistorized source electrode of said the first film or the 3rd thin film transistor (TFT); Be used for carrying out noise cancellation operation, eliminate the noise of the source electrode of the transistorized source electrode of the first film that is attached thereto and/or the 3rd thin film transistor (TFT) when said control electronic circuit receives said control signal.
The present invention also provides a kind of LCD device grid drive device, comprises a plurality of aforesaid shift register cell that is deposited on the LCD (Liquid Crystal Display) array substrate;
Except that first shift register cell and last shift register cell; The signal output part of all the other each shift register cells all is connected with the reset signal input end of signal input part that is adjacent next shift register cell and the last shift register cell that is adjacent; The signal output part of first shift register cell is connected with the signal input part of second shift register cell, and the signal output part of last shift register cell and the reset signal input end of a last shift register cell that is adjacent and the reset signal input end of self is connected;
The signal input part incoming frame start signal of first shift register cell;
First clock signal input terminal of odd number shift register cell is imported first clock signal; Second clock signal input part input second clock signal; First clock signal input terminal input second clock signal of even number shift register cell, second clock signal input part input system first clock signal;
The low level signal input end input low level signal of each shift register cell.
Shift register cell that the embodiment of the invention provides and LCD device grid drive device, owing to increased the denoising circuit when CLK is high level, thus strengthened the denoising ability, and then increased the job stability of shift register.
Description of drawings
Shown in Figure 1 is a kind of shift register cell structural representation of the prior art;
Shown in Figure 2 is the sequential chart of Fig. 1 shift register cell;
Shown in Figure 3 is shift register cell embodiment one structural representation of the present invention;
Shown in Figure 4 is shift register cell embodiment two structural representations of the present invention;
Structural representation after Fig. 5-the present invention of being shown in Figure 7 shift register cell shown in Figure 4 is out of shape;
Shown in Figure 8 is the sequential chart of Fig. 4 shift register cell;
Shown in Figure 9 is shift register cell denoising effect synoptic diagram of the present invention;
Shown in Figure 10 is shift register cell embodiment three structural representations of the present invention;
Shown in Figure 11 is shift register cell embodiment four structural representations of the present invention;
Shown in Figure 12 is shift register cell embodiment five structural representations of the present invention;
Shown in Figure 13 is LCD device grid drive device structural representation of the present invention;
Shown in Figure 14 is the input and output sequential chart of LCD device grid drive device shown in Figure 13.
Embodiment
Fig. 3 is shift register cell embodiment one structural representation of the present invention, and the grid of the first film transistor M1 all is connected with shift register start signal input end INPUT-1 with drain electrode; The drain electrode of the second thin film transistor (TFT) M2 is connected with the source electrode of the first film transistor M1, and the grid of the second thin film transistor (TFT) M2 is connected with reset signal input end RESETIN, and the source electrode of the second thin film transistor (TFT) M2 is connected with low level signal input end VSSIN; The drain electrode of the 3rd thin film transistor (TFT) M3 is connected with the first clock signal input terminal CLKIN, and the grid of the 3rd thin film transistor (TFT) M3 is connected with the source electrode of the first film transistor M1, and the source electrode of the 3rd thin film transistor (TFT) M3 is connected with signal output part OUT; The grid of the 4th thin film transistor (TFT) M4 is connected with reset signal input end RESETIN, and the drain electrode of the 4th thin film transistor (TFT) M4 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, and the source electrode of the 4th thin film transistor (TFT) M4 is connected with low level signal input end VSSIN.
First noise canceling circuit of shift register cell and second noise canceling circuit and the first clock signal input terminal CLKIN and the corresponding one by one setting of second clock signal input part CLKBIN; Each said noise canceling circuit includes: control circuit; Connect with corresponding transistorized source electrode of clock signal input terminal, the first film and low level signal input end; Be used for clock signal input terminal output high level signal in correspondence; And the transistorized source electrode of the first film is exported a control signal when being in low level; Noise canceller circuit; Be connected with said control circuit; Also be connected simultaneously with the source electrode of transistorized source electrode of said the first film or the 3rd thin film transistor (TFT); Be used for carrying out noise cancellation operation, eliminate the noise of the source electrode of the transistorized source electrode of the first film that is attached thereto and/or the 3rd thin film transistor (TFT) when said control electronic circuit receives said control signal.
Wherein, First noise canceling circuit comprises; The first control circuit 11 and first noise canceller circuit 12, first control input end of first control circuit 11 is connected with first clock signal input terminal, and second control input end of first control circuit 11 is connected with the transistorized source electrode of the first film; The output terminal of first control circuit 11 is connected with the signal input end of first noise canceller circuit; The noise output terminal of first noise canceller circuit 12 is connected with said low level signal input end, and the first noise input end of first noise canceller circuit 12 is connected first control circuit 11 with the source electrode of said the 3rd thin film transistor (TFT) and/or the transistorized source electrode of said the first film; Be used for being in high level in first clock signal, when the transistorized source electrode of the first film is in low level; Send first control signal, first noise canceller circuit 12 is used for being connected according to the source electrode of first control signal with transistorized source electrode of low level signal input end and the first film and/or the 3rd thin film transistor (TFT);
Second noise canceling circuit comprises; The second control circuit 21 and second noise canceller circuit 22; The 3rd control input end of second control circuit 21 is connected with the second clock signal input part, and the 4th control input end of second control circuit 21 is connected with the transistorized source electrode of the first film, and the output terminal of second control circuit 21 is connected with the signal input end of second noise canceller circuit; The noise output terminal of second noise canceller circuit 22 is connected with said low level signal input end; The second noise input end of second noise canceller circuit 22 is connected with the source electrode of said the 3rd thin film transistor (TFT) and/or the transistorized source electrode of said the first film, and second control circuit 21 is used for being in high level at the second clock signal, when the transistorized source electrode of the first film is in low level; Send second control signal; Second noise canceller circuit 22, be used for according to second control signal with the low level signal input end with, the source electrode of transistorized source electrode of the first film and/or the 3rd thin film transistor (TFT) connects.
Fig. 4 is shift register cell embodiment two structural representations of the present invention, and as preferred scheme, second control circuit comprises: the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7 and the 8th thin film transistor (TFT) M8; Second noise canceller circuit comprises: the 9th thin film transistor (TFT) M9 and/or the tenth thin film transistor (TFT) M10; First control circuit comprises: the 11 thin film transistor (TFT) M11, the 12 thin film transistor (TFT) M12, the 13 thin film transistor (TFT) M13 and the 14 thin film transistor (TFT) M14; First noise canceller circuit comprises: the 15 thin film transistor (TFT) M15 and/or the 16 thin film transistor (TFT) M16.
The grid of the 5th thin film transistor (TFT) M5 all is connected with second clock signal input part CLKBIN with drain electrode; The source electrode of the 5th thin film transistor (TFT) M5 is connected with the grid of the 7th thin film transistor (TFT) M7; The grid of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the first film transistor M1; The drain electrode of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the 5th thin film transistor (TFT) M5; The source electrode of the 6th thin film transistor (TFT) M6 is connected with low level signal input end VSSIN; The drain electrode of the 7th thin film transistor (TFT) M7 is connected with second clock signal input part CLKBIN; The source electrode of the 7th thin film transistor (TFT) M7 is connected with the grid of the 9th thin film transistor (TFT) M9 and the grid of the tenth thin film transistor (TFT) M10 respectively; The grid of the 8th thin film transistor (TFT) M8 is connected with the source electrode of the first film transistor M1, and the drain electrode of the 8th thin film transistor (TFT) M8 is connected with the source electrode of the 7th thin film transistor (TFT) M7, and the source electrode of the 8th thin film transistor (TFT) M8 is connected with low level signal input end VSSIN; The drain electrode of the 9th thin film transistor (TFT) M9 is connected with the source electrode of the first film transistor M1; The source electrode of the 9th thin film transistor (TFT) M9 is connected with low level signal input end VSSIN, and the drain electrode of the tenth thin film transistor (TFT) M10 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, and the source electrode of the tenth thin film transistor (TFT) M10 is connected with low level signal input end VSSIN; The grid of the 11 thin film transistor (TFT) M11 all is connected with the first clock signal input terminal CLKIN with drain electrode; The source electrode of the 11 thin film transistor (TFT) M11 is connected with the grid of the 13 thin film transistor (TFT) M13, and the grid of the 12 thin film transistor (TFT) M12 is connected with the source electrode of the first film transistor M1, and the drain electrode of the 6th thin film transistor (TFT) M6 is connected with the source electrode of the 5th thin film transistor (TFT) M5; The source electrode of the 12 thin film transistor (TFT) M12 is connected with low level signal input end VSSIN; The drain electrode of the 13 thin film transistor (TFT) M13 is connected with the first clock signal input terminal CLKIN, and the source electrode of the 13 thin film transistor (TFT) M13 is connected with the grid of the 15 thin film transistor (TFT) M15 and the grid of the 16 thin film transistor (TFT) M16 respectively, and the grid of the 14 thin film transistor (TFT) M14 is connected with the source electrode of the first film transistor M1; The drain electrode of the 14 thin film transistor (TFT) M14 is connected with the source electrode of the 13 thin film transistor (TFT) M13; The source electrode of the 14 thin film transistor (TFT) M14 is connected with low level signal input end VSSIN, and the drain electrode of the 15 thin film transistor (TFT) M15 is connected with the source electrode of the first film transistor M1, and the source electrode of the 15 thin film transistor (TFT) M15 is connected with low level signal input end VSSIN; The drain electrode of the 16 thin film transistor (TFT) M16 is connected with the source electrode of the 3rd thin film transistor (TFT) M3, and the source electrode of the 16 thin film transistor (TFT) M16 is connected with low level signal input end VSSIN.The place of converging of the grid of the drain electrode of the source electrode of the first film transistor M1, the drain electrode of the second thin film transistor (TFT) M2, the 9th thin film transistor (TFT) M5, the grid of the 6th thin film transistor (TFT) M6, the 8th thin film transistor (TFT) M8 and the grid of the 3rd thin film transistor (TFT) M3 is the PU node; The place of converging of the grid of the grid of the drain electrode of the source electrode of the 7th thin film transistor (TFT) M7, the 8th thin film transistor (TFT) M8, the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10 is the PD_ckb node; The place of converging of the grid of the source electrode of the 5th thin film transistor (TFT) M5 and the 7th thin film transistor (TFT) M7 is the PD_CN_ckb node; The place of converging of the grid of the source electrode of the 13 thin film transistor (TFT) M13, the drain electrode of the 14 thin film transistor (TFT) M14, the 15 thin film transistor (TFT) M15 and the grid of the 16 thin film transistor (TFT) M16 is the PD_ck node, and the place of converging of the source electrode of the 11 thin film transistor (TFT) M11 and the grid of the 13 thin film transistor (TFT) M13 is the PD_CN_ck node.
Adopt thin film transistor (TFT) M5-M16 to build the control circuit and the noise canceller circuit of shift register cell among Fig. 4; It is a preferred scheme in the present embodiment; Deformation program as Fig. 4 scheme is as shown in Figure 5; Wherein control circuit can also be the 7th thin film transistor (TFT) M7 and the 8th thin film transistor (TFT) M8 that removes among Fig. 4, only adopts the 5th thin film transistor (TFT) M5 and the 6th thin film transistor (TFT) M6 to build, and this moment, the grid of the 9th thin film transistor (TFT) M9 was connected with the 5th thin film transistor (TFT) M5 source electrode.Deformation program as Fig. 4 scheme can also be as shown in Figure 6; Remove the 7th thin film transistor (TFT) M7 among Fig. 4; Only adopt the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6 to build and the 8th thin film transistor (TFT) M8, the grid of the 9th thin film transistor (TFT) M9, the drain electrode of the 8th thin film transistor (TFT) M8 at this moment all is connected with the 5th thin film transistor (TFT) M5 source electrode.As shown in Figure 7; Be with the difference of Fig. 5; Noise canceller circuit can also be built by the 9th thin film transistor (TFT) M9 and the 9th backup thin film transistor (TFT) M9 '; The drain electrode of the 9th thin film transistor (TFT) M9 is connected with the drain electrode of the 9th backup thin film transistor (TFT) M9 ', and the grid of the 9th thin film transistor (TFT) M9 is connected with the grid of the 9th backup thin film transistor (TFT) M9 ', and the source electrode of the 9th thin film transistor (TFT) M9 is connected with the source electrode of the 9th backup thin film transistor (TFT) M9 '.Add similar circuit at the tenth thin film transistor (TFT) M10, the 15 thin film transistor (TFT) M15 and the 16 thin film transistor (TFT) M16 and can realize noise canceller circuit too; This shows any one circuit that no matter adopts like Fig. 4 to Fig. 7, can realize aforesaid control circuit and noise canceller circuit.
Certainly present embodiment adopts is that the transistor of n type is realized aforesaid control circuit and noise canceller circuit; Just as embodiment preferred; Similarly adopting the transistor of p type or mixing n type p type equally also can implement, is that those skilled in the art are easy to just can accomplish, and repeats no more here.
Shift register cell provided by the invention and the structural difference part of shift register cell shown in Figure 1 are: increased the squelch circuit when CLK is high level, this squelch circuit comprises the tenth thin film transistor (TFT) M10, the 11 thin film transistor (TFT) M11, the 12 thin film transistor (TFT) M12, the 13 thin film transistor (TFT) M13, the 14 thin film transistor (TFT) M14, the 15 thin film transistor (TFT) M15 and the 16 thin film transistor (TFT) M16.
Be illustrated in figure 8 as the sequential chart of Fig. 4 shift register cell, the principle of work of shift register cell of the present invention is described below in conjunction with Fig. 4 and Fig. 8.
Select the part of sequential chart shown in Figure 8 and it is divided into five stages.
In the I stage, INPUT is a high level, and RESET is a low level, and then the PU node is a high level, transistor M1, M3, M6, M8, M12 and M14 conducting; CLK is a low level, and M11, M13 end, and PD_CN_ck and PD_ck are low level, and then M15, M16 end; CLKB is a high level, and transistor M5 conducting through the ratio of M5/M6 channel width-over-length ratio is set, makes the PD_ckb node near low level, and then transistor M9 and M10 end; RESET is a low level, and then transistor M2, M4 end; Because transistor M4, M10, M16 end, M3 conducting output equals CLK, is output as low level so CLK is a low level.
In the I I stage, INPUT becomes low level, and RESET still is a low level, and then the PU node still is a high level, still conducting of transistor M3, M6, M8, M12, M14; CLKB becomes low level, and transistor M5, M7 end, and node PD_ckb still is a low level so, and then transistor M9 and M10 still end; RESET still is a low level, and then transistor M2, M4 still end; CLK becomes high level, and then M11 conducting is through being provided with the ratio of M11/M12 channel width-over-length ratio; Make that the PD_ck node is a low level, and then transistor M15 and M16 end, because transistor M4, M10, M16 end; M3 conducting output equals CLK, so CLK is high level output a becoming high level.
In the III stage, INPUT still is a low level, and transistor M1 ends; RESET becomes high level, then transistor M2, M4 conducting; So the PU node is discharged to low level, transistor M3, M6, M8, M12, M14 end; CLKB is a high level, transistor M5, M7 conducting, and node PD_ckb becomes high level so, then transistor M9, M10 conducting; CLK is a low level, and M11, M13 end, and PD_ck is a low level, and then M15, M16 end; Because M3 ends, transistor M4, M10, M16 conducting output equal low level VSS, so output becomes low level.
In the IV stage, INPUT still is a low level, and transistor M1 ends; RESET becomes low level, and then transistor M2, M4 end; The PU node still is a low level, and then transistor M3, M6, M8, M12, M14 still end; CLKB is a low level, and transistor M5, M7 end, and node PD_ckb level is reduced by peak gradually so, and then transistor M9, M10 are ended by maximum conducting gradually; CLK becomes high level, then M11, M13 conducting, and the PD_ck node becomes high level, and then transistor M15 and M16 conducting (if the PU node has noise, then can bleed off through M15 at this moment; If output has noise, then can bleed off through M16), owing to transistor M3, M4 end, so output keeps low level.
In the V stage, INPUT still is a low level, and transistor M1 ends; RESET still is a low level, and then transistor M2, M4 end; The PU node still is a low level, and transistor M3, M6, M8, M12, M14 still end; CLKB is a high level, transistor M5, M7 conducting, and node PD_ckb level is raise by minimum point gradually so, and then transistor M9, M10 (if the PU node has noise, then can bleed off through M9 to maximum conducting by closing gradually at this moment; If output has noise, then can bleed off) through M10; CLK is a low level, and M11, M13 end, and PD_ck is a low level, and then M15, M16 end; Because transistor M3, M4 end, so output remains low level.
In this five stages; I stage shift register start signal input end INPUT-1 input start signal INPUT is a high level; The gate drive signal OUTPUT of II stage signal output terminal OUT output is a high level; Accomplish once displacement, the reset signal RESET of III stage reset signal input end RESETIN end input is a high level, accomplishes the operation that resets; So can be the working time of shift register cell with I, II, III stage definitions; In fourth, fifth stage, the reset signal RESET of the initial INPUT of shift register start signal input end INPUT-1 input signal, the input of reset signal input end RESETIN end is low level, so can be the non-working time of shift register cell with IV, V stage definitions.After this five stages, then repeat IV, the state in V stage, up to occurring I, II, the sequential in III stage once more always.Accomplish I, II, III stage, then accomplished once displacement.The part sequential chart of shift register cell has only drawn among Fig. 8; Every demonstration one two field picture of LCD; Control the shift register cell of certain delegation's liquid crystal pixel and all can export a high level signal; First clock signal clk of the reset signal RESET of the initial INPUT of shift register start signal input end INPUT-1 input signal, reset signal input end RESETIN input and first clock signal input terminal CLKIN input all can repeat an order I, II, the input timing in III stage; In the time of liquid crystal display displays one two field picture; Except that I, II, III all the other times the stage, the reset signal RESET of shift register start signal input end INPUT-1 input start signal INPUT, reset signal input end RESETIN input and first clock signal clk of first clock signal input terminal CLKIN input all can repeat the input timing identical with five-stage with the 4th.
To finding out the detailed description in five stages, in stage, CLK becomes high level from above; Then M11 conducting, the PU node becomes low level, and then M12 and M13 end; Then M13 conducting, so the PD_ck node becomes high level, then transistor M15 and M16 conducting; At this moment, if the PU node has noise, then can bleed off through M15; If output has noise, then can bleed off through M16.Similarly at five-stage, CLKB is a high level, transistor M5; The PU node still is a low level, and then M6 and M8 end, then M13 conducting; Node PD_ckb level is raise by minimum point gradually so; Then transistor M9, M10, then can bleed off through M9 if the PU node has noise by closing gradually to maximum conducting at this moment; If output has noise, then can bleed off through M10.
Compare with shift register cell of the prior art as shown in Figure 1, in the shift register cell provided by the invention, increased the denoising circuit when CLK is high level; Can avoid like this by noise in stage; Thereby strengthened the denoising ability, and then increased the job stability of shift register, Fig. 9 is that output noise compared before and after shift register improved in the embodiment of the invention; From Fig. 9, can obviously find out; Compare with the noise level 200 before improving, the noise level 100 after the improvement, output noise obviously reduces.
Figure 10 is shift register cell embodiment three structural representations of the present invention, adds capacitor C 1, can further strengthen the denoising ability of shift register cell, thereby strengthens the job stability of shift register.On the one hand because C1 has increased the total capacitance of PU node; Reduced the proportion of the 3rd transistor M3 drain parasitic capacitance Cgd3 at the PU node; Thereby can reduce by the first clock signal input terminal CLKIN through the noise of stray capacitance Cgd3, and then also can reduce to the noise of signal output part OUT coupling indirectly, simultaneously to PU node coupling; The 3rd thin film transistor (TFT) M3 leakage current also can correspondingly reduce, and the noise of signal output part OUT can further reduce.
Shown in figure 11 is shift register cell embodiment four structural representations of the present invention, and this embodiment has increased by the 17 thin film transistor (TFT) M17 on the basis of shift register cell shown in Figure 4.The grid of the 17 thin film transistor (TFT) M17 is connected with second clock signal input part CLKBIN, and drain electrode is connected with shift register start signal input end INPUT-1, and source electrode is connected with the PU node.Among this embodiment; In the phase one; When second clock signal CLKB was high level, the 17 thin film transistor (TFT) M17 conducting was because shift register start signal input end INPUT-1 input start signal INPUT is a high level; The source electrode of the 17 thin film transistor (TFT) M17 is a high level; The adding of the 17 thin film transistor (TFT) M17 can reduce rise time of level of the signal of locating to export of PU node, makes the rising edge of signal at PU node place become precipitous, thereby reduces the rise time of the gate drive signal of signal output part OUT output.
Shown in figure 12 is shift register cell embodiment five structural representations of the present invention; This embodiment has increased the input end VDDIN of a dc high voltage VDD on the basis of shift register cell shown in Figure 4; Connect the drain electrode of M1, M5, M7, M11, M13 respectively; Also can only connect wherein part, like M1, M5, M11, like this can be along the serviceable life of long M9, M10, M15, M16.
No matter be shift register cell shown in Figure 4; Or shift register cell shown in Figure 12, the input end that drain electrode connects for the first film transistor M1, this input end is for when shift register start signal input end INPUT-1 is high level; Also (Fig. 4 is shift register start signal input end INPUT-1 to the port level for the port of high level; Figure 12 is the input end VDDIN of dc high voltage VDD), the input end that drain electrode connects for the 5th thin film transistor (TFT) M5, this input end is for when second clock signal input part CLKBIN is high level; Also (Fig. 4 is second clock signal input part CLKBIN to the port level for the port of high level; Figure 12 is the input end VDDIN of dc high voltage VDD), the input end that drain electrode connects for the 7th thin film transistor (TFT) M7, this input end is for when second clock signal input part CLKBIN is high level; Also (Fig. 4 is second clock signal input part CLKBIN to the port level for the port of high level; Figure 12 is the input end VDDIN of dc high voltage VDD), the input end that drain electrode connects for the 11 thin film transistor (TFT) M11, this input end is for when the first clock signal input terminal CLKIN is high level; Also (Fig. 4 is second clock signal input part CLKIN to the port level for the port of high level; Figure 12 is the input end VDDIN of dc high voltage VDD), the input end that drain electrode connects for the 13 thin film transistor (TFT) M13, this input end is for when the first clock signal input terminal CLKIN is high level; The port level also is the port of high level (Fig. 4 is second clock signal input part CLKIN, and Figure 12 is the input end VDDIN of dc high voltage VDD).
Shown in figure 13 is LCD device grid drive device structural representation of the present invention; Shown in figure 14 is the input and output sequential chart of LCD device grid drive device shown in Figure 13; STV is a frame start signal; STV only is input to the shift register start signal input end INPUT-1 of first shift register cell; Low level signal VSS (not shown VSS among Figure 14) is input to the low level signal input end VSSIN of each shift register cell, and the first clock signal input terminal CLKIN of odd number shift register cell imports first clock signal clk, second clock signal input part CLKBIN input second clock signal CLK; The first clock signal input terminal CLKIN input second clock signal CLKB of even number shift register cell; Second clock signal input part CLKBIN input system first clock signal clk; Except that first shift register cell and last shift register cell; The signal output part of each shift register cell all is connected with the shift register start signal input end INPUT-1 of the reset signal input end RETSETIN of a last shift register cell that is adjacent and next shift register of being adjacent; The signal output part OUT of first shift register cell only is connected with the shift register start signal input end INPUT-1 of second shift register cell; The output terminal OUT of last shift register cell (the n+1 shift register cell among the figure shown in figure 13) is connected with the reset signal input end RETSETIN of n the shift register cell that is adjacent and the reset signal input end RETSETIN of self respectively, and wherein n is a positive integer.
Thin Film Transistor-LCD adopts the mode of lining by line scan; Grid with the thin film transistor (TFT) that is connected with liquid crystal pixel in the delegation all links to each other with same shift register cell, and the shift register cell in the LCD device grid drive device can be controlled the conducting that is in the whole thin film transistor (TFT)s among the colleague and end.The concrete principle of LCD device grid drive device is among Figure 13: suppose to have in the panel of LCD the capable pixel of n; Referring to sequential chart shown in Figure 14, be input to the shift register start signal input end INPUT-1 of first shift register cell in the phase one frame start signal; Subordinate phase, the signal output part OUT output high level signal OUTPUT1 of first shift register cell, this high level signal OUTPUT1 is input to the shift register start signal input end INPUT-1 of second shift register cell simultaneously; Phase III; The signal output part OUT output high level signal OUTPUT2 of second shift register cell; After this each shift register cell is exported high level signal successively, is used to control the conducting of the thin film transistor (TFT) of going together that links to each other with this shift register cell, and principle is with second and third stage; To stage; N shift register cell output high level signal OUTPUTn, the high level signal OUTPUTn of n shift register cell output is as the input start signal of the shift register start signal input end INPUT-1 of n+1 shift register cell simultaneously; Five-stage; N+1 shift register cell output high level signal OUTPUTn+1; The high level signal OUTPUTn+1 of this n+1 shift register cell output is not used in the driving load; The i.e. thin film transistor (TFT) of the not responsible drive controlling one-row pixels of n+1 shift register cell, the high level signal OUTPUTn+1 of its output only are used for as n shift register cell and the reset signal of himself.Each shift register cell among Figure 13 can be like Fig. 4, Fig. 5, Fig. 6, Fig. 7, Figure 10, Figure 11 or shift register cell shown in Figure 12.
Among Figure 13, last shift register cell, promptly the n+1 shift register cell is not used in the driving load, can be regarded as redundant shift register cell.In the gate drive apparatus shown in Figure 13; Include only a redundant shift register cell; In fact, can also comprise more a plurality of redundant shift register cells, each redundant shift register cell can combine and guarantee that LCD device grid drive device resets more reliably.
Shift register cell that the embodiment of the invention provides and LCD device grid drive device are because the denoising circuit that has increased when CLK is high level (comprises M11, M12, M13; M14, M15 and M16), in the IV stage, transistor M3, M4 end; Output keeps low level, and CLK becomes high level, then M11, M13 conducting, and the PD_ck node becomes high level; Then transistor M15 and M16 conducting at this moment, if the PU node has noise, then can bleed off through M15; If output has noise, then can bleed off, thereby strengthen the denoising ability, and then increase the job stability of shift register through M16.
What should explain at last is: above embodiment is only in order to technical scheme of the present invention to be described but not limit it; Although the present invention has been carried out detailed explanation with reference to preferred embodiment; Those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, also can not make amended technical scheme break away from the spirit and the scope of technical scheme of the present invention and these are revised or be equal to replacement.
Claims (10)
1. a shift register cell is characterized in that, comprising:
The first film transistor, its grid is connected with shift register start signal input end, and drain electrode is connected with first input end, and first input end is for when shift register start signal input end is high level, and the port level also is the port of high level;
Second thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of said the first film, and grid is connected with the reset signal input end, and source electrode is connected with the low level signal input end;
The 3rd thin film transistor (TFT), its drain electrode is connected with first clock signal input terminal, and grid is connected with the transistorized source electrode of said the first film, and source electrode is connected with signal output part;
The 4th thin film transistor (TFT), its drain electrode is connected with the source electrode of said the 3rd thin film transistor (TFT), and grid is connected with said reset signal input end, and source electrode is connected with said low level signal input end;
First clock signal input terminal and second clock signal input part;
With first noise canceling circuit and second noise canceling circuit of first clock signal terminal and the corresponding one by one setting of second clock signal end, each said noise canceling circuit includes:
Control circuit; Connect with corresponding transistorized source electrode of clock signal input terminal, the first film and low level signal input end; Be used at the clock signal input terminal of correspondence output high level signal, and the transistorized source electrode of the first film is exported a control signal when being in low level;
Noise canceller circuit; Be connected with said control circuit; Also be connected simultaneously with the source electrode of transistorized source electrode of said the first film or the 3rd thin film transistor (TFT); Be used for carrying out noise cancellation operation, eliminate the noise of the source electrode of the transistorized source electrode of the first film that is attached thereto and/or the 3rd thin film transistor (TFT) when said control electronic circuit receives said control signal.
2. shift register cell according to claim 1 is characterized in that,
Second noise canceller circuit comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT) also comprise the 9th thin film transistor (TFT) and/or the tenth thin film transistor (TFT);
First noise canceller circuit comprises: the 11 thin film transistor (TFT), the 12 thin film transistor (TFT), the 13 thin film transistor (TFT), the 14 thin film transistor (TFT) also comprise the 15 thin film transistor (TFT) and/or the 16 thin film transistor (TFT);
The 5th thin film transistor (TFT); Its grid is connected with said second clock signal input part, and source electrode is connected with the grid of said the 7th thin film transistor (TFT), and drain electrode is connected with second input end; Second input end is for when the second clock signal input part is high level, and the port level also is the port of high level;
The 6th thin film transistor (TFT), its drain electrode is connected with the source electrode of said the 5th thin film transistor (TFT), and grid is connected with the transistorized source electrode of said the first film, and source electrode is connected with said low level signal input end;
The 7th thin film transistor (TFT); Its drain electrode is connected with the 3rd input end; The 3rd input end is for when the second clock signal input part is high level, and the port level also is the port of high level, and source electrode is connected with the grid of said the 9th thin film transistor (TFT) and the grid of said the tenth thin film transistor (TFT) respectively;
The 8th thin film transistor (TFT), its drain electrode is connected with the source electrode of said the 7th thin film transistor (TFT), and grid is connected with the transistorized source electrode of said the first film, and source electrode is connected with said low level signal input end;
The 9th thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of said the first film, and source electrode is connected with said low level signal input end;
The tenth thin film transistor (TFT), its drain electrode is connected with the source electrode of said the 3rd thin film transistor (TFT), and source electrode is connected with said low level signal input end;
The 11 thin film transistor (TFT); Its grid is connected with said first clock signal input terminal, and source electrode is connected with the grid of said the 13 thin film transistor (TFT), and drain electrode is connected with four-input terminal; Four-input terminal is for when first clock signal input terminal is high level, and the port level also is the port of high level;
The 12 thin film transistor (TFT), its drain electrode is connected with the source electrode of said the 11 thin film transistor (TFT), and grid is connected with the transistorized source electrode of said the first film, and source electrode is connected with said low level signal input end.
The 13 thin film transistor (TFT); Its drain electrode is connected with the 5th input end; The 5th input end is for when first clock signal input terminal is high level, and the port level also is the port of high level, and source electrode is connected with the grid of said the 15 thin film transistor (TFT) and the grid of said the 16 thin film transistor (TFT) respectively;
The 14 thin film transistor (TFT), its drain electrode is connected with the source electrode of said the 13 thin film transistor (TFT), and grid is connected with the transistorized source electrode of said the first film, and source electrode is connected with said low level signal input end;
The 15 thin film transistor (TFT), its drain electrode is connected with the transistorized source electrode of said the first film, and source electrode is connected with said low level signal input end;
The 16 thin film transistor (TFT), its drain electrode is connected with the source electrode of said the 3rd thin film transistor (TFT), and source electrode is connected with said low level signal input end.
3. shift register cell according to claim 2 is characterized in that, first input end, second input end, the 3rd input end, four-input terminal and the 5th input end all are the high level signal input end.
4. shift register cell according to claim 2; It is characterized in that; First input end is a shift register start signal input end; Second input end is that second clock signal input part, the 3rd input end are that second clock signal input part, four-input terminal are first clock signal input terminal, and the 5th input end is first clock signal input terminal.
5. shift register cell according to claim 2; It is characterized in that; First input end is a shift register start signal input end; Second input end is the second clock signal input part, and four-input terminal is first clock signal input terminal, and the 3rd input end and the 5th input end are the high level signal input end.
6. according to the described shift register cell of arbitrary claim among the claim 1-5, it is characterized in that, also comprise electric capacity, the two ends of said electric capacity are connected with said signal output part with the grid of said the 3rd thin film transistor (TFT) respectively.
7. shift register cell according to claim 6; It is characterized in that; Also comprise the 17 thin film transistor (TFT); Its drain electrode is connected with said shift register start signal input end, and grid is connected with said second clock signal input part, and source electrode is connected with the transistorized source electrode of said the first film.
8. according to the described shift register cell of arbitrary claim among the claim 2-5; It is characterized in that; Ratio between the breadth length ratio of the breadth length ratio of said the 5th thin film transistor channel and the 6th thin film transistor channel satisfies following condition; When the level value of second clock signal and the first film transistor source is high level, make that the level value of source electrode of the 7th thin film transistor (TFT) is flat near low spot, and then to cause the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT) be cut-off state; Ratio between the breadth length ratio of said the 11 thin film transistor channel and the breadth length ratio of the 12 thin film transistor channel satisfies following condition; When the level value of first clock signal and the first film transistor source is high level; Make that the level value of source electrode of the 7th thin film transistor (TFT) is flat near low spot, and then to cause the 15 thin film transistor (TFT) and the 16 thin film transistor (TFT) be cut-off state.
9. shift register cell according to claim 8 is characterized in that, the ratio between the breadth length ratio of the breadth length ratio of said the 5th thin film transistor channel and the 6th thin film transistor channel is 1～1/50; Ratio between the breadth length ratio of said the 11 thin film transistor channel and the breadth length ratio of the 12 thin film transistor channel is 1～1/50.
10. a LCD device grid drive device is characterized in that, comprise be deposited on the LCD (Liquid Crystal Display) array substrate like the described a plurality of shift register cells of arbitrary claim in the claim 1～9;
Except that first shift register cell and last shift register cell; The shift register output terminal of all the other each shift register cells all is connected with the reset signal input end of shift register start signal input end that is adjacent next shift register cell and the last shift register cell that is adjacent; The shift register output terminal of first shift register cell is connected with the shift register start signal input end of second shift register cell, and the shift register output terminal of last shift register cell and the reset signal input end of a last shift register cell that is adjacent and the reset signal input end of self is connected;
The shift register start signal input end incoming frame start signal of first shift register cell;
First clock signal input terminal of odd number shift register cell is imported first clock signal; Second clock signal input part input second clock signal; First clock signal input terminal input second clock signal of even number shift register cell, second clock signal input part input system first clock signal;
The low level signal input end input low level signal of each shift register cell.
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