JP3038139B2 - Graphic processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a command storage unit for storing a plurality of image processing command information received from a data bus of a host processor, and the image processing command information stored in the command storage unit. A geometric operation unit that converts the graphic data to be displayed into display graphic data to be displayed on a monitor by processing according to the arrangement order, and displays the display graphic data obtained by the geometry operation unit in the arrangement. A graphics processor provided with a rendering operation unit for performing conversion processing to display pixel data for each pixel in order, and graphic data to be displayed according to image processing command information received from a host processor via a data bus. To convert the image into display graphic data displayed on the monitor. And Li calculating unit, regarding the graphics processor and rendering computer is provided for the conversion process to the display pixel data for each pixel to display graphic data determined by its geometry calculation unit according to the arrangement order.

[0002]

2. Description of the Related Art Such a graphic processor is a processor which performs various processes mainly for displaying a three-dimensional image on a monitor in place of a host processor, and is roughly divided into a geometry calculation unit and a rendering calculation unit. Pipeline processing system. The geometry calculation unit converts the graphic data to be displayed in the so-called world coordinate system into display graphic data to be displayed on a monitor by performing coordinate conversion, clipping processing, and the like. Since the display graphic data is data represented by lines or planes, it needs to be converted into data for each pixel in order to be displayed on a monitor, and this rendering processing is performed by a rendering unit.

The rendering section not only converts display graphic data into pixel data, but also executes processing such as so-called hidden surface processing on a pixel-by-pixel basis, and finally converts the data into display pixel data to be displayed on a monitor. You. The display pixel data is written into a so-called frame buffer, and the written information is displayed on a monitor after D / A conversion.

[0004] As described above, the graphic processor performs image processing in a pipeline manner in place of the host processor. On the host processor side, the command information is piped in the geometry operation unit or the rendering operation unit of the graphic processor. You may want to know that the processing on the line has been completed. As a case where it is desired to know the end of the processing in the geometry operation unit, for example, a case where the host processor confirms whether or not the display image data created in the geometry operation unit properly includes the data to be displayed. is there. If you want to know the end of the processing in the rendering operation, for example,
A rendering mechanism that can write to one frame buffer is also provided in addition to the above-described rendering operation unit. As a condition for switching the rendering mechanism to be used,
There is a case where it is desired to confirm the end of the processing in one drawing mechanism. Note that as a drawing mechanism that can write to a frame buffer other than the above-described rendering operation unit, there is a drawing mechanism that handles only two-dimensional images. Further, when it is necessary to rewrite the table data of the color look-up table when the writing of the predetermined pixel data to the frame buffer is completed, it may be necessary to know the timing of rewriting the table data.

Conventionally, in order to know the end of the processing in the geometry calculation unit, a command storage unit for storing a plurality of pieces of image processing command information such as drawing commands received from a data bus of a host processor stores the information of the stored commands. When all processes are completed, the host processor has a function of sending an end signal to the host processor, or the command storage unit has a counter that counts each time one image processing command information process is completed. A configuration for monitoring the count value of a counter has been considered.
Also, in order to know the end of the processing in the rendering operation unit,
Conventionally, the rendering operation unit has a function of generating an interrupt signal to the host processor every time the writing to the frame buffer is completed, and the host processor can switch whether or not to generate an interrupt signal. Configuration is considered.

[0006]

However, in the above-mentioned prior art for knowing the end of the processing in the geometry operation unit, the conventional technique for detecting the end of the processing of all the image processing command information stored in the command storage unit. In the configuration, it is impossible to know the end of the processing on the pipeline of the image processing command information in the middle of the plurality of image processing command information stored in the command storage unit, and in the configuration including the counter in the command information storage, The host processor must constantly monitor the count value of the counter, and the use efficiency of the host processor decreases. Further, in the above-described prior art for knowing the end of the processing in the rendering operation unit, if an interrupt signal is generated every time the writing processing to the frame buffer is completed, the host processor is executing each time. Is interrupted, and the processing speed of the host processor is reduced. If the host processor switches and controls the prohibition and release of the interrupt from the graphic processor, such a reduction in processing speed can be prevented. Since it is impossible to grasp the progress of the processing in the upper rendering operation unit, it is difficult to release the interrupt prohibition at an appropriate timing. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to prevent the termination of processing on a pipeline in a graphic processor while minimizing the processing capability of a host processor. That is, the host processor can accurately detect it.

[0007]

According to the first aspect of the present invention, the geometry calculation unit sequentially pipeline-processes the image processing command information stored in the command storage unit in accordance with the arrangement order. In the process, when the interrupt signal generation command included in the image processing command information is detected,
An interrupt signal, which is a signal for notifying the completion of the drawing process and the like that has been executed up to that point, is output. Upon receiving this interrupt signal, the host processor interrupts other ongoing processing and starts processing according to the interrupt signal. That is, by including the interrupt signal generation instruction in the image processing command information, the host processor can know that all the pipeline processing of the image processing command information before the interrupt signal generation instruction has been completed in the geometry operation unit. It is.

[0008] With the above configuration, the pixel data processing unit, which is the last stage of the processing in the graphic processor, performs display for writing the pixel data sent from the rasterizer to the pixel data storage unit to the frame buffer. Is sequentially converted into pixel data for use. The pixel data processing unit outputs an interrupt signal to the host processor when receiving an interrupt signal generation command from the pixel data storage unit during the execution of the sequential processing in units of pixel data. Upon receiving this interrupt signal, the host processor interrupts other processing and starts processing according to the interrupt signal. That is, the geometry calculation unit sends the interrupt signal generation command included in the image processing command information to the rasterizer while maintaining the display graphic data obtained as a result of the processing based on the preceding and following image processing command information in the same order. The rasterizer sends the interrupt signal generation command received together with the display graphic data to the pixel data storage unit while maintaining the arrangement order with the pixel data obtained by converting the preceding and following display graphic data. By including the interrupt signal generation command in the information, the host processor can complete the pipeline processing related to the image processing command information before the interrupt signal generation command in the pixel data processing unit, and substantially write the image data into the frame buffer. You can know that has ended.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a graphic processor according to an embodiment of the present invention; As shown in FIG. 1, the three-dimensional graphics device TD includes a host processor 1 that controls the entire device, and three-dimensional graphics including image processing command information (hereinafter, may be simply referred to as “command information”). Main memory 2 for storing an operation program of the image processing device TD, a graphic processor 3 for executing image processing command information among various commands stored in the main memory 2, and pasting on the surface of an image of a three-dimensional object Buffer 4 for storing texture information as information such as two-dimensional images for
A frame buffer 5 for storing an image for display, a Z buffer 6 for a hidden surface erasing process, a D / A converter 7 for converting digital image data created by the graphic processor 3 into an analog signal, A converter 7
And a monitor 8 for displaying image data converted into analog signals. The three-dimensional graphics device TD includes various input / output devices and storage devices in addition to the above, but is not shown.

As shown in FIG. 2, the graphic processor 3 has an interface circuit 30 for exchanging data with the host processor 1 and the main memory 2 via a data bus DB and an address bus AB, and an interface circuit 30 via an interface circuit 30. A command storage unit 31 for storing a plurality of pieces of command information received from the data bus DB in a FIFO format, and command information received from the command storage unit 31 are sequentially processed to display a graphic to be displayed expressed in a so-called world coordinate system. A geometry operation unit GC that performs processing such as coordinate conversion in consideration of the position of the viewpoint to convert the data into graphic data for display displayed on the monitor 8, and converts the graphic data for display into each pixel. Operation unit RC for converting the display pixel data into display pixel data
And a memory control circuit 32 for controlling the flow of data between the rendering operation unit RC and the frame buffer 5 or the like
And a sprite controller 36, which is a drawing mechanism which is composed of a pipeline from the command storage unit 31 to the rendering operation unit RC and mainly handles three-dimensional images, and which is in charge of processing of two-dimensional images. Provided. The rendering operation unit RC includes a rasterizer 33 that converts display graphic data received from the geometry operation unit GC into pixel data, and a pixel data storage unit that stores a plurality of pixel data received from the rasterizer 33 in a FIFO format. And a pixel data processing unit 35 that performs a process such as a hidden surface process on the pixel data received from the pixel data storage unit 34 and converts the pixel data into display pixel data for each pixel.

The configuration of the geometry operation unit GC will be described in further detail. As shown in FIG. 3, the geometry operation unit GC controls each unit of the geometry operation unit GC based on command information received from the command storage unit 31. A working memory 41 which stores the vertex coordinates, normal data and color data of the graphic data to be displayed, which are included in the command information, and serves as a working area for various operations; An arithmetic unit 42 that performs arithmetic operations such as addition, subtraction, multiplication, and division on the data stored in
Data output memory 4 for storing the operation result of operation unit 42
3, a selector 44 for selecting which of the data from the command storage unit 31 and the data from the arithmetic unit 42 is to be written into the working memory 41, and a register for managing the operation state of the geometry arithmetic unit GC. 45 are provided.

The configuration of the pixel data processing unit 35 will be described in further detail. The pixel data processing unit 35 includes a controller 50 for controlling each unit in the pixel data processing unit 35,
An arithmetic unit 51 that performs processing such as dithering on the pixel data received from the pixel data storage unit 34, and data to be written into the frame buffer 5 as data for display (display data). A selector 52 for selecting from three of data not processed by the arithmetic unit 51 or texture data read from the texture buffer; a Z comparison circuit 53 for comparing Z values for hidden surface processing; and a pixel data processing unit 35 And a register 54 for managing the operation state of the CPU.

The data received by the pixel data processing unit 35 from the pixel data storage unit 34 is mainly pixel data.
The data may be data to be written to the register 54, and the data received from the pixel data storage unit 34 includes a command indicating whether to process the pixel data or a command to write to the register 54. ing. The pixel data further includes a display address on the monitor screen, a Z value that is a distance from the viewpoint, color data, a texture address when using data in the texture buffer 4, and the like. Are assigned to each. In the case of a write command to the register 54, a value to be written to the register 54 is assigned to the bit assigned to the display address and the Z value in the pixel data.

Hereinafter, the operation of the three-dimensional graphics device TD having the above configuration will be described. The host processor 1
Interface circuit 30 of graphic processor 3
In this state, the command information stored in the main memory 2 is sequentially output to the data bus DB. The command information includes, in addition to the drawing command, an interrupt signal generation command (hereinafter, referred to as a “first interrupt signal generation command” for convenience) for generating an interrupt signal from the geometry operation unit GC to the host processor 1. An interrupt signal generation command for generating an interrupt signal from the pixel data processing unit 35 to the host processor 1 (hereinafter, referred to as an interrupt signal generation command).
For convenience, this will be referred to as a “second interrupt signal generation command”). The first interrupt signal generation instruction is an instruction for writing “1” to an interrupt signal generation bit of the register 45 of the geometry operation unit GC, and the second interrupt signal generation instruction is an interrupt signal of the register 54 of the pixel data processing unit 35. This is an instruction to write “1” to the generation bit.

The position where the first interrupt signal generation command in the command information is written may be, for example, when certain command information is processed by the geometry operation unit GC.
When it is desired to use the processing result, it is sufficient to write immediately after the command information. The position where the second interrupt signal generation command in the command information is written may be, for example, from the state where the pixel data processing unit 35 writes the display pixel data to the frame buffer 5 or the state where the sprite controller 36 writes the display pixel data to the frame buffer 5. When it is desired to switch to a state in which the display pixel data is written by writing, the pixel data processing unit 35 may write the display immediately after the command information which is the basis of the display pixel data to be finally written into the frame buffer 5.

The command information output to the data bus DB is sequentially written to the command storage unit 31 via the interface circuit 30. The command storage unit 31
In the FIFO format, the command information stored in advance is sent to the geometry operation unit GC in order, and the geometry operation unit GC sequentially processes the received command information. In other words, the geometry operation unit processes the GC in the order in which the command information is arranged. The controller 40 of the geometry operation unit GC controls the selector 44, the operation unit 42, and the like to perform the coordinate conversion and the like, and writes the operation result to the data output memory 43. The controller 40 sends the first
Upon receiving the interrupt signal generation command, at the time of receiving the command, data is written to the register 45 as instructed. As a result, the interrupt signal generation bit of the register 45 becomes “1”, and this signal is sent to the interrupt signal input of the host processor 1 via the interface circuit 30. The host processor 1 receives this interrupt request, suspends the processing up to that point, and can read, for example, data written in the data output memory 43 of the geometry operation unit GC.

When the controller 40 receives the above-described second interrupt signal generation command from the command storage unit 31, the rendering is performed while maintaining the display graphic data generated by processing the preceding and following command information in the same order as the display graphic data. This is sent to the rasterizer 33 of the arithmetic unit RC. Rasterizer 33
When receiving the graphic data for display from the geometry calculation unit GC, the data is converted into pixel data of the above format while appropriately performing interpolation processing and the like, and sequentially written into the pixel data storage unit 34. When the second interrupt signal generation command is received in the middle of this process, the command is sent to the pixel data storage unit 34 while maintaining the arrangement order with the pixel data generated by the processing of the preceding and following display graphic data.

Since the pixel data storage unit 34 is in the FIFO format, the pixel data is sent to the pixel data processing unit 35 in order from the previously written pixel data. Upon receiving the pixel data from the pixel data storage unit 34, the controller 50 of the pixel data processing unit 35 controls the arithmetic unit 51 and the Z value comparison circuit,
It sequentially performs Z value comparison for hidden surface processing, dither processing for improving color resolution, shadow processing for calculating brightness for expressing a shadow of an object, and brightness calculation for expressing perspective by light and dark. The fog / depth skew processing, the pasting of data of the texture buffer, etc. are executed, and the color data of those processing results are used as display pixel data, and the frame buffer 5 is designated while considering the processing results of the Z value comparison circuit. To the specified display address.

The controller 50 includes a pixel data storage 3
4 receives the above-mentioned second interrupt signal generation command,
Upon receipt, data is written to the register 54 as instructed. As a result, the interrupt signal generation bit of the register 54 becomes “1”, and this signal is sent to the interrupt signal input of the host processor 1 via the interface circuit 30. Upon receiving this interrupt request, the host processor 1 interrupts the processing up to that point, and for example, switches from the state of writing from the pixel data processing unit 35 to the frame buffer 5 to the state of writing from the sprite controller 36 to the frame buffer 5. it can. As described above, the display pixel data written in the frame buffer 5 is converted into an analog signal by the D / A converter 7 and displayed on the monitor 8.

[Other Embodiments] Other embodiments will be listed below. In the above embodiment, the register 45 or the register 54 is provided to generate an interrupt signal.
The controller 40 or the controller 50 may output the interrupt signal directly to the host processor 1. In the above embodiment, the rendering operation unit RC
Z value comparison for hidden surface processing, dither processing for improving color resolution, shadow processing for calculating brightness to express shadows of objects, fog / to calculate brightness for expressing perspective with light and dark Although the configuration is such that depth skew processing, pasting of data in a texture buffer, and the like are performed, these functions can be appropriately omitted and changed.

In the claims, reference numerals are provided for convenience of comparison with the drawings, but the present invention is not limited to the structure shown in the accompanying drawings.

[Brief description of the drawings]

FIG. 1 is a schematic block configuration diagram according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram of a graphic processor according to the embodiment of the present invention;

FIG. 3 is a block diagram of a main part according to the embodiment of the present invention;

FIG. 4 is a block diagram of a main part according to the embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 host processor 8 monitor 31 command storage unit 33 rasterizer 34 pixel data storage unit 35 pixel data processing unit DB data bus GC geometry calculation unit RC rendering calculation unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-149735 (JP, A) JP-A-2-32452 (JP, A) JP-A-56-149644 (JP, A) Field (Int.Cl. ⁷ , DB name) G06F 9 / 38,9 / 46 G06T 1 / 20,11 / 00,15 / 00 G06T 17/00-17/50 JICST file (JOIS)

Claims (2)

(57) [Claims] A command storage unit (31) for storing a plurality of pieces of image processing command information received from a data bus (DB) of a host processor (1), and the image stored in the command storage unit (31). A geometry calculation unit (GC) for converting the graphics data to be displayed into graphics data for display to be displayed on the monitor (8) by processing the processing command information in accordance with the arrangement order; The rendering operation unit (R) that converts the display graphic data obtained in (GC) into display pixel data for each pixel in accordance with the arrangement order.
C), wherein the geometry calculation unit (GC) sends an interrupt signal to the host processor (1) based on an interrupt signal generation command included in the image processing command information. A graphics processor configured to output. 2. A geometry for converting graphic data to be displayed into graphic data for display displayed on a monitor (8) according to image processing command information received from a data bus (DB) of a host processor (1). A calculation unit (GC); and a rendering calculation unit (R) that converts display graphic data obtained by the geometry calculation unit (GC) into display pixel data for each pixel in accordance with the arrangement order.
C) wherein the rendering operation unit (RC) converts the display graphic data received from the geometry operation unit (GC) into pixel data, and a rasterizer (33). A pixel data storage unit (34) for storing a plurality of the pixel data output by the rasterizer (33), and the pixel data stored in the pixel data storage unit (34) are processed in accordance with the arrangement order. A pixel data processing unit (35) for converting the pixel data into the display pixel data.
The geometry calculation unit (GC) receives an interrupt signal generation command included in the image processing command information, and receives the interrupt signal generation command and other image processing command information in the order of arrangement. The rasterizer (33) is configured to be sent to the rasterizer (33) in a state where the interrupt signal generation command is mixed with the display graphic data converted based on the respective image processing command information. ) Is configured to output the interrupt signal generation command together with the pixel data while maintaining the arrangement order, and the pixel data processing unit (35) is configured to output the host signal based on the interrupt signal generation command. A graphics processor configured to output an interrupt signal to the processor (1).