JP3603792B2 - Image memory LSI and image display device using the same - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a three-dimensional graphic display device that performs hidden surface elimination and color mixing (blending), and particularly relates to a configuration of a high-performance image memory and a configuration of a graphic display device using the same.
[0002]
[Prior art]
A conventional image memory, as disclosed in JP-A-59-131979 and U.S. Pat. No. 427,236, comprises a normal dynamic RAM and a serial buffer, and has a first port for random access. , A second port for reading display data is a memory that can be accessed almost independently,
The performance of random access and readout of display data was significantly improved as compared with the RAM.
[0003]
Conventionally, the configuration of a three-dimensional graphic display device using this image memory includes, as shown in FIG. 3, a pixel generation unit 301 that develops pixel information from information of a straight line or a triangle provided from the CPU 200, and information of a developed pixel. Is converted to an address of the image memory 600, the luminance blending is performed to mix the luminance of the developed pixel with the luminance of the pixel stored in the image memory, and the Z coordinate is compared. WID comparison for controlling erasing and writing windows for each pixel and controlling writing, reading of the image memory when obtaining these, and writing to the image memory according to the obtained address, luminance, Z coordinate, and presence or absence of writing. The memory controller 302 for controlling the memory to be controlled and the serial buffer 602 of the image memory 600 are sent to the RAMDAC. A drawing processor 300 including a serial buffer control unit 303 for generating a signal for controlling display data; a memory cell 601 for holding pixel information including luminance information, Z coordinates, and window information; and a pixel for display. It comprises an image memory 600 comprising a serial buffer 602 holding data.
[0004]
[Problems to be solved by the invention]
In the prior art, when the performance of writing pixel data to the image memory is to be improved, the number of data signal lines between the drawing processor and the image memory has been increased. However, there is a problem that the number of signal lines is limited when the rendering processor and the image memory are realized by an LSI.
[0005]
Also, a plurality of images to be displayed are stored in the memory cells of the image memory, and the image memory to be rewritten and the image memory to be displayed are separately provided, so that the screen can be smoothly switched. When trying to realize a double buffer function of selecting one image for each pixel, it is necessary to output the output of the serial buffer for a plurality of pixels from the image memory. There was a problem of increasing.
[0006]
SUMMARY OF THE INVENTION It is an object of the present invention to provide an image memory LSI capable of rapidly improving pixel data writing performance with a small number of signal lines.
[0007]
Another object of the present invention is to reduce the number of output signal lines of a serial buffer of a pixel memory when a double buffer is realized, thereby reducing costs.
[0008]
[Means for Solving the Problems]
According to the present invention, a memory cell holding luminance information and window information of a pixel is compared with window information of a pixel to be written and window information of a corresponding pixel held in the memory cell. It is characterized in that means for determining whether a pixel to be written is to be written to the memory cell is provided on the same chip.
[0009]
Further, the memory cell holding the luminance information and the depth information of the pixel is compared with the depth information of the pixel to be written and the depth information of the corresponding pixel held in the memory cell, and the writing is performed based on the comparison result. It is characterized in that hidden surface erasing means for determining whether or not a pixel to be written should be written to the memory cell is provided on the same chip.
[0010]
Furthermore, in a memory cell that holds luminance information and window information of a pixel, and a serial buffer that reads a plurality of pixels from the memory cell and sequentially outputs the pixels to the outside, the same coordinate read out from the serial buffer is used. Double buffer control means for selecting and outputting desired luminance information based on the window information read from the serial buffer among the plurality of luminance information is provided on the same chip.
[0011]
Furthermore, the present invention provides a CPU that generates coordinates and brightness of each vertex of a figure or a line segment, a drawing processor that generates pixel information of a pixel inside the figure or a pixel on the line segment, An image display device having an image memory for storing pixel information generated by a drawing processor and a display unit for displaying the information stored in the image memory on a screen holds luminance information and window information as the pixel information. Means for comparing the window information of the memory cell to be written, the window information of the pixel to be written and the window information of the corresponding pixel held in the memory cell, and determining whether or not the pixel to be written should be written to the memory cell Is built in the image memory.
[0012]
[Action]
Pixels generated by the drawing processor are basically based on XY coordinates, Z coordinates, and luminance (RGB), and may be provided with window information, blend information, and the like.
[0013]
According to the present invention, in the image memory LSI, the window information held in the memory cell corresponding to the pixel to be written is read, and the read window information and the window information of the pixel to be written are compared. It is compared, and it is determined whether or not a pixel to be written is to be written to the memory cell based on the comparison result.
[0014]
Further, according to the present invention, in the image memory LSI, the depth information held in the memory cell corresponding to the pixel to be written is read, and the read depth information and the depth information of the pixel to be written are read. Is determined based on the comparison result, and it is determined whether or not a pixel to be written is to be written to the memory cell (a hidden surface process is performed).
[0015]
Therefore, since processing such as pixel reading, comparison, and writing is performed on the image memory side, the amount of information given from the drawing processor to the image memory can be halved. In general, the memory access time between the inside and outside of the LSI is shorter in the inside, so that the processing speed is increased. Further, in the LSI, a large amount of pixel information is read and written from memory cells at once. Therefore, it is possible to perform processing by effectively using many pixels once read out.
[0016]
Further, according to the present invention, in the image memory LSI, desired luminance information is determined based on the window information read from the serial buffer among a plurality of pieces of luminance information on the same coordinates read from the serial buffer. Is selected and output as display data, so that the number of display output lines from the image memory can be reduced to one luminance information.
[0017]
【Example】
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0018]
FIG. 1 is a block diagram showing the internal configuration of the high-performance image memory 100. The high-performance image memory 100 receives a 4-bit mode signal MOD, a read / write signal RW, a clock signal PCLK of a parallel port, and a chip select signal PS, generates a timing signal inside the image memory, and controls the internal state of the image memory. The XY coordinates given by the data signal PIO and the parallel port control unit 102 that outputs a signal WAIT indicating access wait and the XY coordinates given by the data register PIO are stored in the mode register 107 according to the screen size and the bit length of one pixel. An XY coordinate conversion unit 103 for converting to an address, and luminance for mixing (blending) the luminance of a pixel already stored in the memory cell 101 and the luminance with the blend coefficient according to the luminance information and the blend coefficient given by the data signal PIO. Given by blending unit 104 and data signal PIO The hidden depth information (Z coordinate) is compared with the depth information already stored in the memory cell 101 to determine whether or not to perform writing, the window information given by the data signal PIO, A plurality of comparison circuits 105 for performing WID comparison for determining whether to perform writing by comparing the window information stored in the window information 101 with an image memory access request from the parallel port control unit 102, and a serial port control unit A memory control unit 106 that generates a control signal for the memory cell 101 based on a memory read request for display from the memory 110 and a memory refresh request, and a screen size (for example, the maximum value of the X coordinate and the Y coordinate). And a minimum value). A mode is a register that specifies the bit length of one pixel and the form of the memory configuration. A register 107, a serial buffer 108 storing display data read from the memory cell 101, and a plurality of pieces of luminance information on the same coordinates read from the serial buffer are selected according to window information read together from the serial buffer. A double buffer control unit 109 for outputting a timing signal for reading display data into a serial buffer in synchronization with an external vertical synchronization signal VSYNC, and a control signal for sequentially updating data output from the serial buffer are transmitted in serial. And a serial port control unit 110 generated in accordance with the port clock SCLK.
[0019]
FIG. 2 is a diagram showing an outline of a graphic display system using the high-performance image memory 100. A CPU 200 that generates coordinates and luminance of each vertex of a figure (hereinafter, a triangle is described as an example) and a line segment (a line is described as an example). And a high-performance image memory 100 that generates hidden pixels and pixels on the straight line, stores the pixels generated by the drawing processor 300 in an internal memory cell by performing hidden surface elimination, blending of luminance, and the like. It comprises a converter DAC 400 for converting digital display data constantly read from the functional image memory into an analog video signal, and a CRT 500 for generating an image on the display screen from the video signal.
[0020]
Here, the operation of the high-performance image memory will be described with reference to FIGS.
[0021]
First, the CPU 200 executes the application program as described above to generate XYZ coordinates and luminance (RGB) of vertices of a triangle or a straight line. This information is passed to the drawing processor 300, which generates pixel information of pixels inside the triangle and pixel information of pixels on a straight line. The pixel information including the XYZ coordinates, the luminance (RGB), and the like (here, there is a window number of the pixel, a blend coefficient, and an overlay) does not have the access wait signal WAIT asserted in the high-performance image memory 100. When written by the drawing processor.
[0022]
At this time, if the number of signal lines of the data signal PIO of the high-performance image memory 100 is 32 bits, the information amount of one pixel is 90 bits or more (11 bits each for XY coordinates, 24 bits for luminance information, 32 bits for Z coordinates, etc.). Therefore, writing is performed in synchronism with the clock signal PCLK of the parallel port in the order of XY coordinates, luminance, Z coordinates, and the like by the mode signal MOD. When the access wait signal WAIT is negated, when the chip select signal PS and the read / write signal RW are in the write state, and when the mode signal MOD indicates the XY coordinate, The data on the signal PIO is written to the XY coordinate conversion unit 103. Similarly, according to the instruction of the mode signal MOD, the luminance and the blend coefficient are written to the luminance blending unit 104, the Z coordinate and the window information are written to the comparing unit 105, and the screen size, the bit length of one pixel, and the like are written to the mode register unit 107. It is. At this time, the mode signal MOD includes a state in which the pixel writing execution is activated. If the pixel signal is not in the pixel writing execution activation state, as described above, only the given pixel information is taken into the register in the high-performance image memory. Not sure. If the pixel writing execution is in the activated state, the memory control unit 106 determines the following for the memory cell 101 based on the pixel information set up to that point and other information (screen size, bit length of one pixel). Perform the writing as follows.
[0023]
First, the XY coordinate conversion unit 103 converts the given XY coordinates into the address of the memory cell 101. Specifically, it is obtained by multiplying the horizontal width of the screen size, the bit length of one pixel, and the Y coordinate, and adding the X coordinate.
[0024]
Next, the normal dynamic memory has a large buffer for one row inside, and takes in data for one row including a pixel to be accessed. If the stored buffer for one row already contains a pixel to be written from now on, this operation is not performed. This operation is controlled by the memory control unit 106 based on the address information of the memory cell output by the XY coordinate conversion unit 103. Next, the luminance blending unit 104 creates a new luminance and a new blend coefficient calculated based on the luminance information in the buffer for one row and the blend coefficient. The calculation for these is performed by a combination of arithmetic operations such as multiplication, addition and subtraction, maximum and minimum, and logical operations such as AND and EOR, and the combination is set in a register in the luminance blending unit 104 in advance. .
[0025]
Next, the Z coordinate and the window information are taken into the comparing unit 105, and are compared with the Z coordinate and the window information given from the parallel port side. The comparison result is sent to the memory control unit 106. The comparison unit has a register for selecting, for example, writing when the value of Z is large, writing when the value of Z is small, and the like.
[0026]
Next, when there is neither a read request for a memory cell for display nor a refresh request for a memory cell, the memory control unit 106 writes the obtained luminance information, the Z coordinate, and the like into the buffer for one row. When a read request for a memory cell for display, a refresh request for a memory cell, or a request for access to a pixel that is not in the buffer for one row is received, the data stored in the buffer for one row is stored in the memory cell. Written back.
[0027]
By the above processing, the pixel information given from the parallel port is stored in the memory cell 101 after the hidden surface elimination and the brightness blending processing are performed.
[0028]
Next, output of display data and control of memory refresh will be described.
[0029]
First, a basic clock signal depending on the display device is always supplied to the clock SCLK of the serial port. In synchronization with this, when the vertical synchronization signal VSYNC is asserted, the display counter inside the serial port control unit 110 is initialized, and the display counter is sequentially updated in synchronization with SCLK. By decoding the value of the display counter, a request signal for transferring data to be displayed from the memory cell to the serial buffer is transmitted to the memory control unit 106. Also, the dynamic RAM needs to refresh all memory contents in 10 ms, and sends a refresh request signal to the memory control unit 106 to satisfy this. Specifically, by referring to the register indicating the screen size and the bit length of one pixel in the mode register 107, a necessary minimum refresh request signal is output according to the value counted by the clock signal SCLK. Usually, the display counter can be used.
[0030]
When the memory control unit 106 receives the display data read request signal and the refresh request signal, the access request to the memory cell from the parallel port is promptly completed, and the request is received in the order of the refresh request and the display data read request. In the former case, the memory cell is read out using the value of the refresh counter in the memory control unit 106 as a refresh address and immediately rewritten, and in the latter case, the display address sent from the serial port control unit 110 is read out, and the serial buffer 108 is read out. To be stored.
[0031]
Next, the display data stored in the serial buffer 108 has a plurality of pieces of luminance information per pixel, window information, and overlay information, and the double buffer control unit 109 selects the luminance information according to the window information. Output to data signal SIO. Specifically, the selection is made by referring to a double buffer selection register in the double buffer control unit 109, which indicates which window selects which luminance information.
[0032]
FIG. 4 is a table showing the meaning of the mode signal MOD of the high-performance image memory. The mode signal MOD is a 4-bit signal line that indicates what data is to be set in the data signal PIO of the parallel port and what data is to be read, as shown in FIG. Has meaning. That is, when the lower 3 bits are 0, 1, 2, and 3, the XY coordinates, luminance information (blend coefficient, RGB), other pixel information (window information, overlay information), and depth information (Z coordinate) are set. . When the most significant bit is 1, it indicates that the memory cell is actually accessed after setting the information of the set pixel. In addition, when the MOD is “0111”, the address of the internal register is specified. When the MOD is “1111”, the data to be written to or read from the register specified by the address of the internal register is specified.
[0033]
Otherwise, it is undefined.
[0034]
Next, FIG. 5 is a table showing the contents of the internal registers. The RESET register is an insubstantial register for initializing the internal state of the high-performance image memory, and when accessed, sets the contents of the internal register to a default value. At this time, the contents of the memory cell do not change.
[0035]
The CONFIG register sets the screen size, the bit length of one pixel, and the number of memories in the X and Y directions. Specifically, the screen size can be selected from 640 × 400 pixels, 1024 × 768 pixels, 1152 × 900 pixels, 1280 × 1024 pixels, 1600 × 1200 pixels, and 1920 × 1035 pixels in 3 bits. Further, the bit length of one pixel is 3 bits, and one pixel of 8, 16, 32, 64, 96, or 128 can be selected. The number of memories in the X and Y directions can be selected from one, two, four and eight with two bits each for X and Y.
[0036]
The STATUS register is a read-only register and is used to read an internal state. The internal state includes the contents of the display counter and refresh counter, the transition state of the internal control logic, and the like, and is mainly used for debugging and maintenance.
[0037]
The WT_FUNC register holds, to the set luminance information, luminance information after performing a blending process and information for selecting the calculation content when calculating the write destination luminance information. Logical product, exclusive OR, addition, subtraction, maximum, minimum, etc. are specified by 5 bits.
[0038]
The BLEND register is a 6-bit register that specifies how to calculate the set luminance information with the blend coefficient. The BLEND register determines which of the 0, 1, and the blend coefficient (1-blend coefficient) is to be multiplied with the luminance information. (The luminance information set from the parallel port and the luminance information of the already stored pixels can be set respectively, and the blend coefficient can be selected from the above two types of luminance information, so that a total of 6 bits are required. ).
[0039]
Z_CMP is a bit for designating whether or not to perform a comparison with the Z coordinate, and 3 bits for selecting what kind of comparison operation is to be performed, for example, =, ≠, ≦, ≧,>, <. Bit register.
[0040]
WID_CMP is a 1-bit register indicating whether to compare window information.
[0041]
PL_MASK_AC, PL_MASK_WO, and PL_MASK_Z are registers each indicating a blend plane, luminance information, window information, overlay information, and a write plane mask for a buffer of the Z coordinate. It is possible to set each time.
[0042]
BUF_SEL is a register that indicates which side of the double buffer the pixel that is going to write or read is currently selected. When the value of this register is 0, the buffer is 0; 1 is written to the buffer.
[0043]
HBLANK indicates a horizontal blanking period, and is a register for designating how many times SCLK has started to start outputting display data from SIO based on the falling cycle of VSYNC.
[0044]
VBLANK indicates a vertical blanking period, and is a register for specifying how many rasters later the display period starts from the falling edge of the VSYNC signal. One raster is the horizontal width of the screen size and the horizontal width set in the HBLANK register. Indicates the period including the blanking period.
[0045]
Next, the BUF_LUT register indicates the correspondence between the window information and the buffer to be displayed. When the window information is 4 bits, it is a 16-bit register.
[0046]
Among the above-mentioned registers, the RESET register has its internal state initialized at the same time as the writing, and the other registers have the most significant bit of the mode signal MOD of 1 and have an access request and the vertical synchronization signal VSYNC. Influences the operation from the moment it comes. In other words, these registers have a two-stage configuration. The first stage is a register that can be freely set from the parallel port, and the second stage is a register used for a process currently in operation. The transfer from the first stage to the second stage is performed when the access request is received and when the vertical synchronization signal VSYNC is received.
[0047]
The outline and operation of the high-performance image memory have been described above. Next, a method of applying the present invention to some graphics systems will be described with reference to FIGS.
[0048]
First, FIG. 6 shows a system configuration using a plurality of drawing processors 310 and a plurality of high-performance image memories 100 for realizing high performance. The rendering processor 310 performs processing of decomposing one rendering command, for example, a straight line or a triangle into pixels, and writing the same into the high-performance image memory 100. Four high-performance image memories 100 are connected to one drawing processor 310 in a one-to-one relationship, and the four high-performance image memories can be accessed independently.
[0049]
One of the drawing processors supplies a vertical synchronization signal to the other drawing processors and all the high-performance image memories. For the RAMDAC, a vertical synchronization signal for the RAMDAC and a horizontal synchronization signal are supplied. To supply. In this configuration, the register indicating the memory configuration of the CONFIG register in each high-performance image memory is designated as having four pixels and four rasters in both X and Y directions. By reading display data from memory cells only when necessary, access from the parallel port can be maximized.
[0050]
Next, FIG. 7 shows a configuration of a graphics system which has high resolution but emphasizes cost. The rendering processor is one in which a plurality of high-performance image memories are connected on the same bus. To access the parallel port of the high-performance image memory, a chip select signal PS is individually given from the rendering processor. It is done by doing. The access wait signal WAIT selects and uses a WAIT output from the high-performance image memory to be accessed. Signals other than the chip select signal PS and the access wait signal WAIT can be commonly connected. Vertical sync signal
The connection of VSYNC is supplied by the rendering processor to all the high-performance image memories, and the horizontal and vertical synchronization signals for the RAMDAC are also supplied by the rendering processor.
[0051]
Next, FIG. 8 shows a configuration of a graphics system with a minimum cost. The bus controller 700 is configured to decode a system bus connecting the CPU and the graphic system and to access a high-performance image memory.
The access address from the CPU is decoded, the mode signal MOD and the chip select signal PS are set, and the access to the high-performance image memory is performed while synchronizing with the access wait signal WAIT. In addition, processing for supplying a vertical synchronizing signal to the high-performance image memory and horizontal and vertical synchronizing signals to the RAMDAC is also performed.
[0052]
Finally, FIG. 9 shows a time chart when the parallel port is accessed.
[0053]
From the top of the figure, a cycle number for explanation corresponding to the clock, PCLK, PIO, MOD, RW, WAIT, and PS, which are interface signals of the parallel port, and read addresses and read, which are internal states of the high-performance image memory. It shows data, a write address, write data, a write control signal to an internal buffer, and a write control signal to a memory cell of the internal buffer.
[0054]
In cycle 1, the high-performance image memory is in an idle state and is waiting for an access request.
[0055]
In cycle 2, when MOD is set to XY coordinates, RW is written, chip select PS is selected, and XY coordinate data is set to the data bus PIO, the XY coordinates are stored in the read address register in the high-performance image memory.
[0056]
In the cycle 3, by setting the blend coefficient and luminance information (RGB) described as AC in the drawing after the XY coordinates, the blend coefficient in the high-performance image memory and the luminance buffer are stored. At the same time, the XY coordinates set in the cycle 2 are converted into the row address and the column address of the memory cell, and it is determined whether or not the row address is the same as the address of the currently read data. The currently read data is written back to the original address, and an operation of newly reading data at the specified address is performed. If the row address is the same as the address of the read data, one pixel data is selected and used according to the column address.
[0057]
In cycle 3 in FIG. 9, it is assumed that the XY coordinates (XY2) have already been read into the buffer in the high-performance image memory.
[0058]
In cycle 4, window information indicated by WO in the figure and overlay information are set. On the other hand, the data read in cycle 3 and the blend coefficient and luminance information set in cycle 3 are also effective from this cycle, and the blending process is started. In the blending process, the time until the result is completed varies depending on the blending method set in the BLEND register. Therefore, a counter for counting the number of cycles depending on the blending method is provided, and the counter is reset when the blend coefficient and the luminance information are set and when the read data becomes valid.
[0059]
In cycle 5, depth information Z indicated by ZE in the figure is set, and writing is started. To start the writing, an internal writing flag is set by designating that the pixel information set up to that point is to be hidden surface erased and blended and written to the memory cell.
[0060]
In cycle 6, the XY coordinates of the next pixel are given. In the high-performance image memory, the blending process is continued, and the Z coordinate set in cycle 5 is compared with the read Z coordinate to determine whether to write.
[0061]
In cycle 7, the blend coefficient and luminance information of the pixel of the XY coordinates set in cycle 6 are given. In the high-performance image memory, the blending process is completed, and a buffer write signal for reading the blended pixel information and writing it to a row buffer is asserted. At this time, it is determined whether or not the XY coordinate XY6 set in cycle 6 has the same row address as the XY coordinate XY2 set in cycle 2.
[0062]
In cycles 8, 9, 10, and 11, the same processing as in cycles 4, 5, 6, and 7, respectively, is performed, and the pixels subjected to blend processing and hidden surface erasure are written at the XY coordinates XY6. However, in the cycle 11, since the XY coordinate XY10 has a different row address from the XY coordinate XY6, in order to write back the contents of the currently buffered row buffer to the memory cell, the WAIT signal is first asserted, and the next access is performed. Do not come.
[0063]
In cycle 12, the contents of the row buffer are written back to the memory cells by asserting the memory write signal. The WAIT signal is asserted until this cycle to prevent the next access.
[0064]
In cycle 13, a process of reading the row data of the XY coordinates XY10 into the row buffer is performed. The WAIT is released here, and the next access is made possible.
[0065]
After cycle 14, the same processing as in cycle 4 is sequentially performed. Here, as shown in cycle 17, when the chip select signal PS is negated, the access in that cycle is invalid, so that the value of cycle 17 is not used for the blend coefficient and the luminance information. The set blend coefficient and luminance information are used. In addition, since the chip select signal PS is negated also in the cycle 20 and thereafter, the mode signal MOD specifies start-up, but is not accepted, and no pixel is drawn.
[0066]
According to the embodiment described above, the register for setting the screen size and the bit length of one pixel and the XY coordinate conversion unit 103 enable the pixel information to be directly transferred to the high-performance image memory in the XY coordinates. Writing can be performed, and the load on the drawing processor that generates the upper pixel can be reduced.
[0067]
In addition, since the brightness blend processing unit 104 and the comparison unit 105 are provided in the high-performance image memory, the data throughput between the memory cell 101 and the memory can be greatly increased. Higher speed is achieved compared to the system.
[0068]
Also, by having the serial port control unit 110 in the high-performance image memory and outputting the access wait signal WAIT, the upper-level drawing processor can be conscious of the display timing and conscious of the refresh cycle of the memory. No load can be reduced. This has the effect of simplifying the configuration of the graphics system, especially when the higher-level drawing processor is a CPU having no special display logic circuit.
[0069]
In addition, the presence of the double buffer control unit 109 does not output a plurality of pieces of pixel information from the high-performance image memory, and thus has the effect of reducing the number of input / output signal lines.
[0070]
【The invention's effect】
According to the present invention, color mixing (blending), hidden surface erasure, and the like can be performed only by writing the pixel information to the image memory by the host processor, so that there is no read access to the image memory. The amount of data transferred between the processor and the image memory is reduced, so that access can be speeded up and cost can be reduced by reducing the number of external signal lines of the image memory.
[0071]
Further, a double buffer control unit is provided in the image memory to output the display pixel information selected according to the window information, so that the number of display output signal lines can be reduced by half, and the cost can be reduced.
[0072]
The image memory itself performs the display data readout process and the memory refresh, and a signal indicating a period during which the host processor cannot access is provided, so that the display data readout process and the image memory refresh process can be performed by the host processor. Since no circuit is required, the cost of the host processor can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the internal structure of a high-performance image memory LSI according to one embodiment of the present invention.
FIG. 2 is a diagram showing an outline of a display system using the high-performance image memory LSI shown in FIG.
FIG. 3 is a diagram showing a configuration of a conventional three-dimensional display device using an image memory.
FIG. 4 is a view showing the meaning of a mode signal MOD of the high-performance image memory.
FIG. 5 is a diagram showing contents of a register in the high-performance image memory.
6 is a diagram showing one configuration example of a display system using the high-performance image memory LSI shown in FIG.
FIG. 7 is a diagram showing another configuration example of the display system.
FIG. 8 is a diagram showing another configuration example of the display system.
FIG. 9 is a diagram showing a time chart at the time of parallel port access.
[Explanation of symbols]
100 high-performance image memory, 101 memory cell, 103 XY coordinate conversion unit, 104 brightness blending unit, 105 comparison unit, 106 memory control unit, 107 mode register unit, 108 serial buffer, 109 double Buffer control unit, 110: serial port control unit, 200: CPU, 300, 310: drawing processor, 400: DAC (DA converter), 500: CRT, 600: conventional image memory.

Claims (2)

A memory cell for holding pixel luminance information and window information;
A serial buffer for reading a plurality of pixels from the memory cell and sequentially outputting the read data to the outside;
Among a plurality of pieces of luminance information on the same coordinates read from the serial buffer, based on the window information read from the serial buffer, a double buffer controller that selects and outputs desired luminance information,
An image memory LSI in which the memory cell, the serial buffer, and the double buffer controller are provided on the same chip. A CPU for generating coordinates and luminance information of each vertex of the figure or the line segment;
A drawing processor that generates pixel information of pixels inside the figure or pixel information of pixels on the line segment,
An image memory for storing pixel information generated from the drawing processor;
A display unit for displaying information stored in the image memory on a screen,
The image memory includes a memory cell that holds the luminance information and the window information that are the pixel information, a serial buffer that reads a plurality of pixels from the memory cell, and sequentially outputs the read pixels to the outside, and an identical memory read from the serial buffer. An image display device comprising: a double buffer controller that selects and outputs desired luminance information based on window information read from the serial buffer among a plurality of pieces of luminance information on coordinates.

Images