JP4191212B2 - Image display system - Google Patents

Description

  The present invention relates to a video interface mechanism for displaying an image on a display panel, and more particularly to a driving method, a driving device, a display device, and the like for driving a display panel and a high-definition panel.

  In general, a display image is processed by a graphics controller of a host device such as a personal computer (PC) and sent to the display device. However, due to recent advances in display devices represented by liquid crystal display (LCD) panels, there has been a large difference in processing capability between host devices and display devices. For example, in the LCD panel, the resolution of the panel itself has been improved, and QXGA (Quad Extended Graphics Array) (2048 × 1536 dots), QSXGA (Quad Super Extended Graphics Array) (2560 × 2048 dots), QUXGA (Quad Ultra) High-definition (ultra-high-definition) panels with very large resolution such as Extended Graphics Array (3200 × 2400 dots) are being put into practical use. However, the system power and the power of the graphics controller cannot follow the progress of the panel, and the current situation is that sufficient display on the ultra-high definition panel cannot be performed.

For example, the performance of an image processing system represented by a graphics controller is limited to a general display function of about QXGA, and three-dimensional (3D) computer graphics (CG) represented by a video game console for home use. ) Has a low resolution processing capability of about VGA (Video Graphics Array) (640 × 480 dots). In this way, for example, the state-of-the-art video still has a resolution of about VGA, while the panel can produce resolutions several to several tens of times higher, and the disparity in processing power has become prominent. It was.
On the other hand, a display device typified by an LCD panel has recently become smaller in the frame around its display unit, so that a so-called tiling in which a plurality of panels are combined into an enlarged panel has become possible. As a result, it is possible to further increase the resolution, and the difference from the host side has become more prominent.

  As a first means for solving the power shortage of the graphics chip, for example, the system configuration shown in FIG. 18 can be considered. In this system configuration, the high-definition panel 201 on the panel side 200 is divided into four, and a plurality of panel control chips 202 corresponding to the four areas are provided. Reference numeral 203 denotes a display dividing line by this division. On the other hand, on the host side 210, the same number of graphics chips 211 are provided for each panel control chip 202 and connected to each panel control chip 202 via the same number of digital interface (I / F) lines 220. Each graphics chip 211 includes a graphics memory 212. In addition, display data from an application is multi-inputted to each graphics chip 211 via the system bus 213. According to this technology, even if the processing capability of each graphics chip 211 is low, for example, four sets can be processed, so that the problem regarding the processing capability can be solved.

  Further, as a second means for solving the power shortage, for example, a method in which a memory is provided on the display device side and the transfer rate is reduced to a transfer rate that can be technically realized can be considered. More specifically, on the host side, only one graphics chip is provided, and a graphics memory having a capacity for the entire screen is connected. On the other hand, on the monitor side, a panel memory is provided for the panel control chip. After the image data is developed in the graphics memory on the host side, the image data is sent to the monitor side at a reduced transfer speed in response to the shortage of processing capacity. The image data sent to the monitor side is temporarily stored in the panel memory by the panel control chip, and then the screen is refreshed. According to this means, the conventional refresh rate can be adopted as it is by slowing down the transfer speed, and a high-definition still image can be displayed.

  As a prior art described in the publication, for example, data organized from a source generation program is sent to a central module of an active module via a high bandwidth channel, and each active module includes a display device driver, a display There is disclosed a technique that includes a device, a memory, and the like, and that enables high-resolution large-screen display, and that can cope with a moving image in real time (see, for example, Patent Document 1). Also, for example, a master personal computer that outputs digital video signals, a video distribution device that distributes a plurality of digital video signals, a plurality of computers that perform signal processing such as partial enlargement, and video output signals from the plurality of personal computers There is a technique that includes a plurality of monitors for display and displays a desired portion of a video signal to be combined on a plurality of monitors for a personal computer (for example, see Patent Document 2).

JP 07-146671 A (page 7, FIG. 2) JP 07-261721 (page 2-3, FIG. 1)

By taking the above-described means, even if a graphics chip having a low processing capability is used, a temporary display can be performed on a high-definition panel.
However, in the first means described above, the first problem is that image processing of a divided screen that straddles the display dividing line 203 of the panel 201 shown in FIG. For example, if the original image data is not QXGA, it is necessary to send the divided data to the graphics chip 211 with the VGA or XGA (Extended Graphics Array) (1024 × 768 dots) enlarged from the beginning. There is. That is, it is required to enlarge beyond the boundary and output an image on the enlarged screen. This means that the host side 210 separates and transfers the image data to the graphics chip 211 every time the system changes with the resolution of the display screen. Almost all current applications are only scheduled to be written on a single screen, and it is practically difficult to execute the processing for dividing and dividing the screen for each chip into the memory in the current application. It is.

  In addition, as a second problem in the first means described above, the system bus 213 performs multiple inputs to the respective graphics chips 211, so that the performance of the system bus 213, which is a common bus, is the overall processing. It becomes a bottleneck. There are two system buses 213: a PCI (peripheral component interconnect) bus and an AGP (accelerated graphics port), and the AGP is 8 times higher in performance. For transferring a large amount of image data such as 3D graphics, the PCI bus has insufficient capability, and it is necessary to use an AGP having a high transfer rate. However, this AGP does not have a bus structure in order to perform high-speed processing, and multi-connection is not possible and one-to-one data processing is performed. Therefore, when there are a plurality of graphics chips 211 as shown in FIG. 18, the AGP cannot be used, and as a result, the performance of the system bus 213 cannot be improved.

  On the other hand, the above-mentioned second means can solve the above-mentioned two problems (scaling of screen breaks and system bus problems) in the first means. However, although display is possible if the transfer rate is reduced to 1/4, for example, reducing the transfer rate is a new problem. That is, when displaying a moving image, frames are dropped due to slow transfer. For example, even if expected at 60 Hz, writing cannot be performed at that speed. With this second means, for example, a window display in which a high-definition still image and a moving image are mixed cannot be realized.

The present invention has been made to solve the technical problems as described above, and the object is to distribute processing between the host side (system side) and the panel side (monitor side). This is to optimize the work load of the entire system including the graphics chip.
Another object of the present invention is to make it possible to sufficiently draw out the processing capability of the image display system including the transfer capability, and to solve problems such as insufficient display capability for ultra-high definition panels and multi-panels.
Still another object is to enable appropriate display on an ultra-high definition panel even in 3D graphics and the like that require a high transfer rate.

  For this purpose, the image display system of the present invention is characterized in that processing is distributed between the host side and the display side. That is, an image display system that includes a host for executing an application and a display connected to the host and displays an image on the display, and the host requests the display to display an image. In this case, image data before image development is transferred to the display, and this display includes a panel memory for image development, and develops the image in the panel memory based on the image data transferred from the host. It is characterized in that the image developed in the panel memory is displayed on the panel.

For example, if this display is characterized in that the panel is refreshed based on the image developed in the panel memory, the portion consumed for the refresh on the host side (system side) can be performed on the display side. This is preferable in that the power consumption for data transfer can be reduced.
Further, for example, the host transfers the image data of the first resolution to the display based on the output from the application executed at the first resolution, and the display has the transferred first resolution. The image data may be converted into a second resolution, which is a higher resolution, and developed on the panel memory. With this configuration, there is no need to transfer data that has been scaled up (scaled up) from the host side. For example, even if the data is enlarged four times in ultra-high-definition display, the amount of transferred data increases. Can be prevented.
Further, the host transfers the compressed image data compressed to the display in a compressed state, and the display decompresses the transferred compressed image data and expands it to the panel memory. The feature is preferable in that, for example, when a part of a DVD (Digital Versatile Disc) screen, which is compressed data, is displayed, the transfer amount can be greatly reduced.

As an aspect of this image display system, in addition to the case where the host side and the display side exist in the same casing as in a notebook PC, the host-side system apparatus and the display-side display apparatus are separate casings. Numerous modes are conceivable, for example, when connecting via an interface (I / F) cable.
Here, transferring image data before development is distinguished from, for example, a conventional technique in which image data scanned over the entire surface of an image as it is output to a display device is transferred.

In the image display system of the present invention, distributed processing using a plurality of systems simultaneously is also possible. That is, a plurality of system devices each for executing an application, and a display device including a panel control unit for dividing a display region into a plurality of regions and controlling driving for the divided regions. The system device is connected to panel control means provided in the display device, and outputs a control signal for synchronizing with the panel control means. The panel control means in the display device includes a plurality of systems. Based on the control signal output from the apparatus, a control signal for synchronizing with a plurality of system apparatuses can be output. According to this, for example, even in a 3D moving image display in which the system power is generally insufficient, driving with four system devices enables a large screen or ultra-high definition display.
In addition, as an aspect of this panel control means, it may be formed by one chip in addition to being divided into a plurality of chips.

The control signal output from the system device is job information that can be processed by each system device in the next frame. The control signal output from the panel control means is a job output from a plurality of system devices. It can be characterized in that it is information indicating the job with the slowest processing speed detected from the information.
This job information can be, for example, the maximum (last) job number that can be executed in the next frame.
Further, the system apparatus determines a job to be executed based on the control signal output from the panel control means, and outputs image data for requesting display to the display area by executing the job. Can be characterized.
According to these configurations, for example, even when a 1/4 screen divided by four system devices is controlled, it is possible to easily control the entire screen and to improve performance in a specific application. Become. In addition, each system device can be synchronized in the exchange with the display device, which is excellent in that it can reduce complicated processing for synchronization on the system side.

  On the other hand, this image display system can develop and display mixed images on the display side in response to display requests output from a plurality of applications. That is, an image display system including a host that executes a plurality of applications having different display characteristics and data amounts required, a display that displays an image, and a digital interface that transfers image data from the host to the display The digital interface changes the transfer format according to the application executed by the host and transfers the image data to the display. The display uses the image data transferred via the digital interface for development. An image can be displayed on the panel after being developed in the panel memory.

  In addition, the digital interface transfers image data by a packet and also transfers the image data by designating a data transfer mode in the packet. The display panel displays the image data based on the designated data transfer mode. It can be characterized by being expanded in a memory. With this configuration, for example, there is room for expansion to receive image data transferred from different applications such as the number of bits, resolution, transfer mode, transfer speed, etc., and develop and display the image on the panel side. There is.

Next, when grasping the present invention from the host device, the host device of the present invention has execution means for executing a plurality of applications having different display characteristics and data amount required, and an image space in which the application is conscious. The window management means for managing the window ID defined for the window and the window ID managed by the window management means are added to the window which is a meaningful area in the window, and the application requests display. And image data transfer means for transferring image data before development.
The image data transfer means can transfer image data by using a packet format, and transfer the image data by changing the transfer data format according to the application.
With this configuration, for example, it is possible to transfer all of the refresh operations that have been conventionally performed on the host side to the display side, and the processing capacity of the host device can be sufficiently extracted by distributing the processing. This is preferable.

  The host device of the present invention is based on an image data transfer means for transferring image data to a connected display, an executed still image application and an executed moving image application, which are the respective applications. Control means for supplying image data to the image data transfer means, and this control means supplies the image data regardless of the refresh timing required for the display for this still image application. The above application can be characterized in that image data is supplied in synchronization with the refresh timing required for the display. According to this configuration, in the host device, for example, only a 3D workpiece can be used, and the processing capability can be improved by a factor of two or more in the case of SXGA.

  On the other hand, when grasping the present invention from the side of the image display device, the image display device of the present invention includes a panel for displaying an image and image data receiving means for receiving image data before development from a host device that executes an application And a panel memory for expanding the image data received from the image data receiving means, and a panel control means for expanding the image data to the panel memory and writing the expanded image on the panel. It is characterized by that.

The image data receiving means receives a plurality of undeveloped image data having different display characteristics and data amounts required, and the panel control means expands the plurality of undeveloped image data to display a display screen. It is characterized by forming.
Further, the panel control means can perform a refresh on the panel based on the image developed in the panel memory.
Further, the image data receiving means receives the image data having the first resolution, and the panel control means scales the image data to a second resolution different from the first resolution and develops the image data in the panel memory. It can be characterized by.

  In addition, the present invention is an image display device that is connected to a plurality of system devices that respectively execute applications, and that displays an image based on image data transferred from the plurality of system devices. A display unit that displays a plurality of display panels as a single panel as a divided panel, and a panel control unit that controls image display with respect to the display unit. A control signal related to a job is received from the system apparatus, and a control signal used for synchronization by the plurality of system apparatuses is transmitted to the plurality of system apparatuses. In the display unit, when a plurality of display panels are collectively displayed as one panel, the display unit is a three-dimensional display or a spatial display other than the case where tiling is performed to form a single panel. A mode in which the panels are separated in the front-rear direction and the like is also conceivable.

Here, the panel control means may be formed of a single chip or the like as its mode.
On the other hand, the panel control means includes a plurality of display panels corresponding to each of the divided panels in the display unit, or corresponding to each of the display panels constituting a plurality of display panels collectively forming one panel. And a control signal received by a specific panel control means, further comprising an internal bus for other panel control means to recognize the control signal received by each of the plurality of panel control means. Based on the above, it is possible to output a control signal for synchronizing the system devices.
The control signal received by the panel control means is a job number that can be executed by the system apparatus in the next frame. The panel control means is configured by the system based on the job number existing on the bus. If the control signal including the job number to be executed in the next frame is transmitted, it is possible to synchronize a plurality of system devices in the exchange with the system device using the job number. preferable.

  Further, the image display device of the present invention has a panel for displaying an image, an image data receiving unit for receiving image data before development from a host side that executes a plurality of applications, and an image data receiving unit that receives the image data. A panel memory for expanding image data, and a panel control means for expanding the image data to the panel memory and writing an image to the panel by performing color adjustment for each different image data by the application It is characterized by that. As an aspect of this configuration, for example, conversion of color adjustment such as gamma can be controlled for each window with respect to image data divided into windows which are transfer processing units for each application.

The image display device according to the present invention is different from the panel for displaying an image, the color image data having the first number of bits resulting from the execution of each application, and the first number of bits. Image data receiving means for receiving monochrome image data consisting of the second number of bits from the host side, a panel memory for expanding the image data received from the image data receiving means, and image data for this panel memory The panel control means is characterized in that the data format is changed between the color image data and the monochrome image data received from the image data receiving means and is developed in the panel memory. According to this configuration, different types of images can be displayed together.
Further, the panel control means may write an identification bit for identifying color image data and monochrome image data in the panel memory, and execute a developing process based on the identification bit.

On the other hand, the present invention is an image display method for displaying an image on a display connected based on a signal from a host executing an application, and image data that has not been developed for image display is displayed on the host. The image data is transferred to the display via a digital interface, the display expands the transferred image data to the memory of the display, and the image expanded in the memory is displayed on the display. It is said.
For example, if the display is refreshed based on the image developed in the memory included in the display, it is possible to distribute processing such as refreshing between the host side and the display side. It is not necessary to transfer a large amount of image data after development from the host each time.

The present invention is also an image display method for displaying an image on a connected display based on a signal from a host executing an application, and the first resolution executed by the application from the host. The image data is transferred to the display, the display scales the image data according to the first resolution transferred from the host, and develops the image at a second resolution different from the first resolution, and the display The display can be output to a panel included in the display.
Further, the display may be a multi-panel in which a plurality of panels are tiled or a high-definition panel having a large resolution, and the scaling of the image data may be an enlarged display.

According to the present invention, processing can be distributed between the host side and the panel side (monitor side), and the work load of the entire system including the graphics chip can be optimized.
Furthermore, the processing capability of the image display system including the transfer capability can be fully exploited, and problems such as insufficient display capability for ultra-high definition panels and multi-panels can be solved.
Furthermore, even in 3D graphics and the like that require a high transfer speed, appropriate display on the ultra-high definition panel is possible.

[Embodiment 1]
First, before entering the detailed description of the components, the configuration of a display screen to which the present embodiment is applied will be briefly described with reference to FIG.
The panel 55 which is a display screen is a liquid crystal display panel having ultra high definition such as QUXGA (3200 × 2400 dots). In the example of FIG. 8, the panel 55 is decomposed into four sub-panels by the display decomposition line 56. Image development on these sub-panels is driven by different panel control chips 51 (described later). This is because the actual panel 55 has too many dots to be processed and cannot be driven by one panel control chip 51. One of the panel control chips 51 is connected to the external data bus 68, and each sub-panel is connected to the in-panel data bus 69. An external data bus 68 input to the panel control chip 51 and indicated by a broken line is externally input from each system to each sub-panel when the multi-system described in detail in the second embodiment is adopted. .

  Here, in this embodiment, the concept of window is introduced. This window is an area that is meaningful on the image space that the host is aware of, and is a unit of image data transfer processing. FIG. 8 shows a window 58 for displaying a three-dimensional (3D) moving image screen and a window 59 used for text display. As shown in FIG. 8, when a text character or the like is displayed on the display screen 57 at a high resolution of 200 dpi (dot per inch), for example, the screen resolution normally used is 100 dpi. Therefore, the size becomes 1/4. For this reason, the text is displayed using a font that is four times larger. On the other hand, the 3D moving picture screen by the window 58 is originally made of VGA (640 × 480 dots), and is displayed on the screen at a horizontal and vertical ratio of 1600 × 1200 dots.

  FIGS. 9A and 9B are explanatory diagrams for explaining the processing for each data and the processing amount. FIG. 9A is a system diagram of the processing of the data source and each component in the present embodiment. In FIG. 9A, the preprocessor 20 in the host-side graphics chip 11 is provided with a prehandler 26 (described later) corresponding to each application such as text data, 3D animation, 32-bit color image, and DVD. ing. The image data from the prehandler 26 is sent to the panel side via the I / F transceiver 15 and the digital I / F line 49. On the panel side, image data is input to a post handler 78 (described later) in the panel control chip 51 via the I / F receiver 53. The post handler 78 is a processing unit in charge of processing one window, and the post handler 78 executes processing to display an image on the panel 55.

  On the other hand, FIG. 9B shows a state in which the data bandwidth is limited from the mode in which the image is developed on the host side and transferred to the panel side in the prior art. In FIG. 9B, image data is developed in the graphics memory 212 by the graphics chip 211 on the host side. Then, for example, image data is transferred to the panel side via the digital interface (I / F) line 220 via the I / F transceiver 15 in synchronization with the refresh on the panel side. On the panel side, image data is transferred to the panel control chip 202 via the I / F receiver 53 and displayed on a panel (not shown).

Here, for example, 3D animation processing typified by games is currently VGA resolution even at the highest speed. This is not yet sufficient, and further improvement in processing capability is expected. Processing of a display screen of UXGA or higher requires a processing capability several tens of times higher. The panel 55 has a resolution of QUXGA (3200 × 2400 dots), and the refresh data amount for generating this screen is 3200 × 2400 × 24 (R / G / B each 8 bits) × 60 [Hz] × 2.5 = 3.45 [Gbyte / s] is required. However, in the prior art shown in FIG. 9B, the maximum processing capacity is determined by the bus width between the graphics chip 211, the graphics memory 212, and the panel control chip 202. Generally, 128 bits × 144 [MHz] = 2.3 [Gbyte / s] is the maximum, and about 90% is actually the maximum capacity that can be used. Therefore, when the panel 55 has a high-definition screen, development of this memory processing chip becomes very difficult.
On the other hand, in the present embodiment shown in FIG. 9A, since the screen of the panel 55 can be divided and driven, the panel control chip 51 can be increased according to the number of divisions, for example, four divisions. If processing is performed, the amount of processing data can be reduced to 1/4.

  Further, as described above, for example, it is desired to increase the number of polygons that can be further processed in 3D animation. On the other hand, for still images such as text screens, a display screen with higher definition than the problem of processing speed is desired. That is, since the text screen is intended to be read by humans, there is no effect even if the writing rate is lowered to about 20 [Hz]. On the other hand, if the definition is increased, it becomes more beautiful than the printed material. In this way, the processing forms required for the display data differ greatly, and if the entire process is not handled by the same process but can be optimized according to the display data, the overall processing capability is improved as a result.

  For this reason, the present embodiment solves this problem by introducing the concept of windows, dividing the data format, and performing distributed processing. That is, as shown in FIG. 9A, a 3D animation window is generated with, for example, VGA resolution and enlarged to 2.5 times, and at the same time, a SXGA screen with a slow transfer speed, for example, 30 [Hz] is updated. Configured to be possible. In the conventional display method shown in FIG. 9B, the transfer speed between the graphics chip 211 and the graphics memory 212 needs about 3 [Gbyte / s]. Further, 1.5 [Gbyte / s] is required as the digital I / F line 220 as a transfer rate, and four sets are required when the DVI interface is used. On the other hand, in this embodiment, half the transfer amount of VGA and SXGA is sufficient for the digital I / F line 49, and the transfer amount is 300 [Mbyte / s] and 1/5. Also, a transfer amount between the panel control chip 51 on the panel side and a panel memory (described later) is sufficient to be 1 [Gbyte / s] or less.

  FIG. 10 is an explanatory diagram simply explaining the image data transfer method using the packet used in the present embodiment in relation to the above-described window. Assume that an area A and an area B exist as image images by the host application. In the present embodiment, the image development work is not performed on the host side 10 (described later), and the image development work is performed on the panel side 50 (described later). On the host side 10, for example, a window ID: 4 is set for the area A, and a window ID: 5 is set for the area B. The transfer of the image information to the panel side 50 is performed for each area by a packet method. More specifically, in response to a display enable signal (Display Enable), for example, the image signal is transferred after being packetized for each scan. ID information indicating a window ID is added to the image signals by these packets and transferred. For example, if each handler (described later) in a specific sub-panel is set to process window ID: 4 and window ID: 5, image information transferred by the packet method and assigned with the window ID is displayed on the designated sub-panel. It becomes possible to expand with. Data transfer by packet will be described in detail later.

The present embodiment has been conceptually described above. Next, the configuration of each unit in the present embodiment will be described in detail.
FIG. 1 is a block diagram showing an embodiment of an image display system to which the present invention is applied. In FIG. 1, reference numeral 10 denotes a host (HOST) side composed of a personal computer (PC) or the like, and has a role as a driving device for driving the display device in the present embodiment. On the host side 10, reference numeral 11 denotes a graphics chip, and image data preprocessing is executed by a preprocessor 20 included therein. Reference numeral 12 denotes a graphics memory, which has a smaller capacity than the conventional one because it is not necessary for the graphics chip 11 to continue refreshing by the distributed processing described later. A system bus 13 is connected to a host system (not shown) that executes applications. Reference numeral 14 denotes a graphics memory bus between the graphics chip 11 and the graphics memory 12. Reference numeral 15 denotes an interface (I / F) transceiver which serializes image data and transmits it to the panel side 50 through a digital I / F line 49.

  On the other hand, the panel side 50 includes a plurality of panel control chips 51 each having a post processor 70 therein. In FIG. 1, the divided panel 55 is driven using four panel control chips 51 corresponding to the four divisions of the panel 55. Reference numeral 52 denotes a panel memory provided in each panel control chip 51. Reference numeral 53 denotes an interface (I / F) receiver for inputting image data. Reference numeral 54 denotes a panel data output for transmitting the output from the panel control chip 51 to the panel 55. Reference numeral 55 denotes a panel for actually displaying an image, which is divided into four areas in FIG. The panel 55 is composed of a high-definition panel. In order to support this high-definition screen, the panel control chip 51 enables a plurality of parallel processes. Reference numeral 68 denotes an external data bus, and 69 denotes an in-panel data bus.

  The characteristic configuration in the present embodiment is that data pre-processing is executed by the preprocessor 20 in the graphics chip 11 and post-processing is performed by the post processor 70 in the panel control chip 51. As a result, the screen generation job that has been performed on the host side 10 such as the image refreshing by mixing image data, which has been performed by the graphics chip 11 until now, is displayed on the display device side (panel side 50). It has moved. That is, the preprocessor 20 adds the tag and image data attributes and error protection to the image data before the image data is expanded, that is, the image data before mixing, and the post processor 70 expands the image data to the panel memory 52 for the first time. That is, it is decompressed, the image data is mixed, and transferred to a refresh circuit (not shown).

  Here, the flow of processing of general image data in the present embodiment will be described. The graphics chip 11 on the host side 10 reads and writes the graphics memory 12 through the graphics memory bus 14. An application system (not shown) that executes an application is handled by the system bus 13. The system bus 13 employs the aforementioned AGP. This AGP has 2 to 8 times the performance of a conventional PCI bus, but since it is not a bus, only one is active in the system. The digital output of the graphics chip 11 is sent to the I / F transceiver 15, where it is serialized and transferred at high speed.

  The image data serialized by the I / F transceiver 15 is sent to the receiving I / F receiver 53 via the digital I / F line 49. The I / F receiver 53 returns the serialized image data to the original parallel video data. The parallel-converted image data is sent to the panel control chip 51. In this panel control chip 51, first, packetized image data (described later) is decompressed by the post processor 70, a window ID (described later) is recognized, data operation corresponding thereto is performed, and the data is expanded in the panel memory 52. Store. Separately, the panel control chip 51 sequentially reads display data from the panel memory 52 and sends it to the panel 55.

  As described above, in the present embodiment, a display processing job (for example, image data expansion, refresh for display, and timing in the H (horizontal) / V (vertical) direction, which has been conventionally performed by the graphics chip 11, is performed. The post-processor 70 of the panel control chip 51 and subsequent circuits perform most of the generation, the memory allocation according to the screen size of the display device, and the number of colors. As described above, in the system according to the present embodiment, the load on the graphics chip 11 on the host side 10 is reduced, and the display processing is performed by the panel control chip 51 capable of a multi-chip configuration. Can function well. In addition, since the graphics chip 11 is simply processed with VGA resolution and enlarged with the panel control chip 51, it is possible to display a moving image such as 3D graphics.

  FIG. 2 is a diagram for explaining the graphics system on the host side 10 described in FIG. The graphics chip 11 includes a DAC (D / A converter) 16 that generates video data and an address generator 17 that generates a synchronization signal. In the prior art, as a form that can be displayed as it is on the display device, the address generator 17 outputs a synchronization signal composed of H-Sync and V-Sync together with a display enable signal. In the present embodiment, the processing of the graphics chip 11 is reduced, and the image data is not expanded and the data can be sent as it is. From the DAC 16, for example, 24-bit color data is output to the preprocessor 20. In addition, only the DE signal indicating data valid and the address (Address) signal for setting the start point and the like are output to the preprocessor 20 from the address generator 17. The preprocessor 20 executes a process for adding a window ID and address information to the image data. For information exchange between the host side 10 and the panel side 50, a 12C-based interface known as DDC (Display Data Channel) is used. The control signal can be transferred between the host side 10 and the panel side 50 through this interface.

  FIG. 3 is a block diagram showing the internal configuration of the preprocessor 20. The input latch 21 latches video data input from the application. In the ID register 22, a window ID given to the packet is set, and a pre-handler 26 corresponding to this window ID can be selected. The pointer 23 converts information such as a simple address and data order into a packet. The sync bit 24 is a bit for synchronizing the display screen and the write data. The vertical counter of the display screen is synchronized with this bit. The check bit generator 25 receives data input from the input latch 21 and a DE (Display Enable) signal indicating data valid, and generates check bits (parity, sum, CRC, etc.) of the image data.

  The prehandler 26 is a handler on the preprocessor 20 side, and has data for each window ID. Here, the handler is a processing unit in charge of processing of one window, and is also provided in a post processor 70 described later on the panel side 50, and has various registers. A window ID register 27 indicates an ID of which window each handler in the pre-handler 26 corresponds to. The clip register 28 is a register indicating an area where data can actually be written. The position register 29 indicates the position of the transfer data. The scale register 30 is a register indicating a magnification for scaling image data. A mode register 31 indicates a transfer mode or a write mode of image data. The priority register 32 indicates the priority for each window ID.

The DDC handler 37 transmits and receives DDC control signals to and from the panel side 50. The job number output register 33 is a register for writing a job number, and this job number is sent to the panel side 50 via the DDC handler 37. In the job number input register 34, the smallest overall job number is read via the DDC. This job number is used for synchronization when a multi-system configuration is adopted, as will be described in the second embodiment described later. The sync back register 35 is used to synchronize from the panel side 50 and is configured to read the normalized vertical information on the panel side 50. The error status register 36 is configured to return error information of processing on the panel side 50.
Further, in the multiplexer 38, header information from the ID register 22, pointer 23, sync bit 24, body information which is video image data from the input latch 21, footer information from the check bit generator 25, command from the prehandler 26 Is multiplexed, packetized and transferred to the panel side 50.

  FIG. 4 is a block diagram showing a schematic configuration of the display circuit on the panel side 50. The panel control chip 51 includes a post processor 70, an input FIFO 61, an output FIFO 62, an input address register 63, and an output address register 64 having an H counter 65 and a V counter 66. The image data serialized and transferred from the host side 10 is converted into parallel image data and a control signal DE by the I / F receiver 53. Unlike the prior art, the data from the I / F receiver 53 is in packet format and is decompressed and processed by the post processor 70. The post processor 70 is provided in the panel control chip 51 in the panel side 50 and processes a packet sent from the host side 10. A process such as a scale is one of the processes executed by the post processor 70. The image data is read / written to the panel memory 52 while the timing is adjusted by the input FIFO 61 and the output FIFO 62, and sent to the next processing. Here, the image data processed by the post processor 70 is an X / Y address, and is converted into a memory address by the input address register 63. The converted memory address is stored in the panel memory 52 and the output address register 64. Entered. The output address register 64 includes an H counter 65 and a V counter 66, and a horizontal / vertical synchronization signal is output to the panel 55. Further, the post processor 70 executes display mode conversion and the like.

  FIG. 5 is a block diagram showing an internal configuration of the post processor 70. The input latch 71 latches input packet data. In the ID register 72, the window ID stored in the packet is set. The pointer 73 converts information such as a packetized simple address and data order. The sync bit 74 is a bit for synchronizing the display screen and the write data. The vertical counter on the display screen is synchronized with this bit. The error generator 75 detects a data error based on the data check bit. On the other hand, the address generator 76 generates an address from the pointer and packet information from the ID register 72, the pointer 73, and the sync bit 74. The clipping circuit 77 is configured to detect a writable area from the clip register 80 and the priority control circuit 89 in the post handler 78 and cut out that portion of the image data from the input latch 71.

  The post handler 78 is a handler in the post processor 70 and functions as a processing unit in charge of window processing. A window ID register 79 in the post handler 78 indicates a window ID of a packet processed by each handler in the post handler 78. The clip register 80 is a register indicating an area where data can actually be written. A position register 81 indicates the position of the transfer data. The scale register 82 is a register indicating a magnification for scaling image data. A mode register 83 indicates a transfer mode or a write mode of image data. The priority register 84 indicates the priority of the clip area of each handler. The error status register 85 is a register indicating an error status of processing on the panel side 50.

  The DDC controller 86 processes a DDC control signal transmitted / received to / from the host side 10. The scaling circuit 87 enlarges / reduces the image data output from the clipping circuit 77 and outputs the image data to the panel 55. The FIFO memory 88 is a memory used for enlarging / reducing by the scaling circuit 87. The priority control circuit 89 sets the writable area of the image data in the window ID from the processing area (clipping area) of each post handler 78 and the respective priority. Further, the synchronization control circuit 90 is a circuit used to synchronize the vertical synchronization of the panel and the data processing in the system, using a normalized vertical counter, and outputs a vertical synchronization signal. The job number register 91 is connected to an internal bus, which is a low-speed bus, and is used when a multi-system is adopted, and stores a minimum job number.

Here, processing performed by the pre-processor 20 on the host side 10 and the post-processor 70 on the panel side 50 will be briefly described with reference to the flowchart of FIG.
First, each register of the pre-handler 26 in the pre-processor 20 is set according to the window by the application (step 301). This information is transferred to the post processor 70 by the DDC control signal via the DDC handler 37, and the window ID register 79 of the post handler 78 is set (step 302). On the other hand, the ID register 22, the pointer 23, and the sync bit 24 are written as the header information of the packet used when transferring the image data (step 303). Further, the preprocessor 20 puts the information of the post handler 78 into the packet body and transfers it as a packet (step 304). The transferred data is stored in the post handler 78 with the matching ID (step 305).

  Next, video data is put into the body of the packet and transferred from the system as a header, body, and footer (step 306). The panel side 50 first cuts out the header from this packet, selects the post handler 78 corresponding to the ID therein, and this is processed by the selected handler (step 307). The data part is processed from the clip information, priority, position information, and header address information. Thereafter, the data and address are sent to the next stage (step 308). At the same time, error detection is executed and error information is stored (step 309). The processing from step 306 to step 309 is performed for each line (for example, 1280 dots) or for one block (for example, a block of 32 × 32 dots) (step 310). Error information is periodically read from the system on the host side 10 via the DDC, and necessary processing (transfer stop and retransfer) is performed (step 311).

FIGS. 7A, 7B, and 7C are explanatory diagrams showing a comparison of data transfer between the prior art and the present embodiment, and a data format.
FIG. 7A shows a conventional video data transfer. In the conventional transfer, R (Red) / G (Green) / B (Blue) video data and V-sync, H-sync, DE, and other two control signals are serialized and sent. Video data is sequentially transferred line by line from the upper left to the lower right according to the display screen. Further, there is a period during which no data is transferred as blanking time. On the other hand, there is a slow reading path of about 100 [KHz] for sending a DDC control signal from the panel to the host.

On the other hand, in the transfer of video data in the present embodiment shown in FIG. 7B, the blanking time in the conventional transfer is used. Information of 16 dots or less is added to the header and footer. This is called packetization. In this embodiment, in order to handle a plurality of source packets at the same time, the V-sync and H-sync synchronization signals are meaningless here, and the V-sync information is included in the header. Therefore, the synchronization signal may be one DE that is a signal indicating the data transfer amount, and this synchronization signal is used in error processing or the like in this embodiment. In addition, information to be processed by the DDC increases, and it becomes a two-way usage. Also, the amount of data is not fixed.
In the present embodiment, consideration is given to making the data format similar to that of the prior art. This is to maintain compatibility with devices adopting the conventional method in consideration of the case where a conventional PC and a monitor device exist in the market. In addition, in order to minimize the change of the graphics chip, consideration is given so that the data format can be supported without much change.

  FIG. 7C shows a data format in the present embodiment. The body is a normal image data part and has a variable length. The header portion includes a window ID corresponding to the name tag of the image data, a pointer indicating the writing position, a synchronization bit instead of V-sync, and the like. There is a footer at the end of each packet bit, which is used to detect errors. This is because the case where a phase error or the like occurs is considered because data is sent through the transmission system.

  As described above, according to the present embodiment, it is possible to reduce the workload by moving the screen refresh work to the display device side (panel side 50) and scaling on the display device, for example. When a window is displayed on an ultra-high definition panel, characters and the like need to be displayed with high definition, and the same applies to still images. However, in 3D display of games and the like, the performance on the CPU side is not sufficient, so for example a VGA screen is displayed. According to the present embodiment, these two portions are divided and the still image portion is refreshed using the memory on the panel side 50. As a result, the system side (host side 10) becomes only a 3D work, and the processing capability can be improved more than twice in the case of SXGA, for example. Furthermore, the conventional 3D display part is scaled up by about 1.5 times on the system side when transferring data at a resolution of VGA (640 x 480 dots) and XGA (1024 x 768 dots). It was. According to the present embodiment, this work can also be processed on the panel side 50. This is a great advantage especially when the display is magnified 4 times in ultra-high-definition display, or when the power consumption is severe in a notebook or the like.

[Embodiment 2]
In the first embodiment, the case where the display device is driven on the host side 10 using the single graphics chip 11 has been described. In the second embodiment, a so-called multi-system display method in which a display device is driven on the host side 10 using a plurality of graphics chips 11 will be described.
In addition, the same code | symbol is used about the function similar to Embodiment 1, and the detailed description is abbreviate | omitted here.

The moving image display processing by the multi-system in the present embodiment has two main features.
One is not only controlling the screens shared by each system as described in the first embodiment, but also being able to control the entire screen from one of the systems. Conventionally, since each system controls each screen, the OS of one system cannot control the whole only by controlling 1/4 of the screen. According to the present embodiment, for example, a normal window process can be performed from one system, and at the same time, it is possible to receive support from a plurality of systems only for a specific 3D window.
Another feature is the difference in synchronization. Conventionally, a system has a high-speed LAN and special communication means, and these are configured to synchronize a plurality of systems. This method is complicated and highly interdependent between systems. On the other hand, in the present embodiment, synchronization between a plurality of systems can be achieved during exchange with the display device (panel side 50).

  FIG. 11 is a block diagram for explaining a system configuration in a multi-system according to the present embodiment. As shown in the figure, the panels 55 divided into four by the display decomposition line 56 are connected to the panel control chip 51, respectively. However, it is not always necessary to have a plurality of panel control chips 51, and it is also possible to configure to control with one control chip. Each panel control chip 51 receives video data from the graphics chip 11 of a separate system 100. On the panel side 50, each panel control chip 51 is connected by an in-panel data bus 69 so that the entire screen can be controlled simultaneously from one system 100.

Here, in general, when displaying a moving image in a plurality of systems (such as a PC), two problems related to synchronization have been pointed out.
One is a synchronization problem related to screen refresh and display data transfer. When there is one display screen, the screen refresh timing is naturally one, and each system must be synchronized with this. For example, consider a case where a person is displayed on the upper and lower screens and the refreshed data is rewritten as the person is moving to the right. If the synchronization is not achieved, for example, only the upper part moves to the right by one dot, and the lower part is left as it is, such a phenomenon occurs in the display separation line 56 that is a joint of the screen.
The other is a synchronization problem of the moving image processing itself, which occurs when the moving image application is not controlled by time. For example, the amount of work to be performed during 16 [msec], which is one frame, is not determined, but the display frame is advanced in accordance with the performance of the system or the display is drawn more finely. When connecting and displaying image data sent from these systems, due to differences in the amount of data being processed, for example, the left screen is faster and fogging (fogging) etc. In some cases, the processing is performed and the right side is slow and fogging does not occur.

FIG. 12 is an explanatory diagram showing a configuration of synchronization processing between the host side 10 and the panel side 50 in the present embodiment. In the present embodiment, the above two problems related to synchronization are solved using a DDC signal.
The preprocessor 20 in one system 100 on the host side 10 and further in the graphics chip 11 is provided with a synchronization control circuit 40, a read / write control 45, and the like. The synchronization control circuit 40 includes an offset register 41, an adder 42, a multiplexer 43, and a vertical synchronization counter 44. On the other hand, the post processor 70 of the panel control chip 51 on the panel side 50 includes a synchronization control circuit 111, a DDC handler 115, and a job (JOB) number controller 116. The synchronization control circuit 111 includes a vertical synchronization counter 112, an offset register 113, and an adder 114. The job number controller 116 includes a job number input register 117, a job number output register 118, a comparator 119, an internal bus controller 120, and an internal bus 121.

  On the panel side 50, there is a vertical synchronization counter 112 having position information for screen refresh. All the chips have the same value by two internal synchronization signals (INT_VSYNC and INT_HSYNC) in synchronization with the refresh of the panel 55 (however, This is not necessary when there is one panel control chip 51). This is normalized so that the output from the offset register 113 is added to the adder 114 for each internal INT_HSYNC and is not affected by the number of vertical lines of the panel 55. This value is read by the DDC and written to the vertical synchronization counter 44 in the graphics chip 11 on the system 100 side. The output from the vertical synchronization counter 44 is also added by the adder 42 together with the output from the offset register 41 in order to normalize.

  FIG. 13 is a diagram showing a process flow in the present embodiment. The left side shows the flow of processing on the application or device driver side of the system 100. The right side shows the flow of processing in the panel control chip 51 on the panel side 50. In the present embodiment, the work from each system 100 is managed by a job, and it is configured to be able to share how much can be written among multiple systems by a plurality of systems 100. Here, a job (task) is a division unit such as which polygon (triangle in 3D) is written in a moving image, for example, and a job (task) number is a sequence number obtained by dividing image processing into arbitrary units. It is. The unit of the image processing can be arbitrarily selected, and the processing within one frame is divided. Therefore, there is no problem if the unit is several tens or more in one frame.

First, the application calculates the maximum job number of a process that can be executed in the next frame at a certain timing (step 401). Further, in order to execute job synchronization, the job number of the master PC that becomes the master in the plurality of systems 100 is set to 0 (or the minimum), and the operation is stopped (step 402). The calculated maximum job number is transferred to the panel control chip 51 on the panel side 50 via the DDC. Here, the image processing is premised on division into specific units and numbering in the order of processing.
The panel control chip 51 sequentially passes the respective job numbers to the internal bus (INT_BUS) 121 on the panel side 50 (step 404). In each panel control chip 51, the comparator 119 compares the job number value on the bus with the smaller job number and reads it into the job number output register 118 (step 405).

  In each system 100, the job number is read via the DDC, and the job number is read from the job number output register 118 of the panel control chip 51 or the already read job number input register 34 (step 406). Each system 100 executes jobs up to this number as processing in the next frame based on the read job number (step 407). In the present embodiment, the master PC sets the job number to 0 to stop the start of the entire operation, and when the master PC starts to move, the operation starts, so that the number of the job processed by the application is assigned to each system 100. Can be obtained. By executing these series of processes until the correct job number is set in the master PC, the jobs in the plurality of systems 100 are synchronized. In other words, this processing flow makes it possible to synchronize with the slowest system 100 in the plurality of systems 100.

Next, the correct job number is set in the master PC (step 408). This starts the job. Each system 100 calculates the maximum job number that can be processed in the next frame (step 409). In the same manner as described above, a job number is set for the panel 55 via the DDC (step 410).
On the other hand, the panel control chip 51 sequentially passes the respective job numbers to the internal bus (INT_BUS) 121 on the panel side 50 (step 411). In each panel control chip 51, the comparator 119 compares with the job number value on the bus, reads the smaller job number, and writes it in the job number output register 118 (step 412).
On the system 100 side, the job number is read via the DDC, and the job number is read from the job number output register 118 of the panel control chip 51 or the already read job number input register 34 (step 413). Each system 100 executes jobs up to this number as processing in the next frame based on the read job number (step 414). Then, the process returns to step 409.

  FIG. 14 is a timing chart for further explaining the synchronization processing operation by the multi-system described in the above flowchart. The panel vertical counter (Panel V-CNTR) becomes zero every vertical synchronization (V-SYNC), and the vertical synchronization counter 112 is counted. At some point, this register is read and written to the vertical synchronization counter 44 on the system side. As shown in the timing of System V-CNTR in FIG. 14, the writing to the vertical synchronization counter 44 is configured to cause a slight delay. The system 100 can recognize the synchronization after waiting for this delay.

  In the timing chart of FIG. 14, the vertical synchronization counter 44 of the system 100 uses a timing close to the maximum value, and each of them starts calculating the job number. That is, in order to start the job calculation after the reading operation, the vertical counter (VCNTR) starts processing after N + X time has elapsed. At the same time, data transfer is started from the double buffer (not shown) on the system side to the panel side 50. Then, the value is written in the job number input register 117 on the panel side 50. On the panel side 50, the value of each panel control chip 51 is placed on the internal bus 121 at an appropriate timing. Each panel control chip 51 reads the value from the internal bus controller 120. Then, the self value of the job number input register 117 and the value written in the job number output register 118 are compared, and the smallest value is obtained from the comparator 119 and is written in the job number output register 118 again. Thus, when reading from the system 100, the minimum job number of each system 100 is read. The system 100 that has read this value executes the process up to that number in the next process, and at the same time, sets the vertical counter (V-CNTR). That is, the system 100 reads the job number and the value of the vertical counter (V-CNTR) via the DDC, determines the job number for the next frame processing, and simultaneously sets the vertical counter (V-CNTR).

  As described above, according to the present embodiment, even when the system side power is insufficient, for example, in the case of 3D display, for example, display can be performed by dividing the display part into four parts. It becomes possible. That is, for example, if each divided part is driven by four systems, a large screen of about SXGA (1280 × 1024 dots), which is a quadruple screen, and a super high definition display of 10 ”UXGA (200 dpi) can be obtained. According to this embodiment, when viewed from the user, only the 3D window is supported with high performance while displaying the entire screen from one system. In other words, the PCs with completely different OSs can display the screens or display them in cooperation.

[Embodiment 3]
In the third embodiment, an image display method for supporting a display color composed of multiple bits with an increased number of expression colors will be described.
Conventionally, support for display colors of 24 bits or more has been limited to high-end (high-end) workstations. One reason for this is that, in order to support a display color of 24 bits or more, the processing speed of each part increases and the system becomes expensive. In this embodiment, by executing distributed processing on the host side and the system side, it is possible to slow down the system processing speed, and it becomes easy to support display colors of 24 bits or more.
In addition, the same code | symbol is attached | subjected about the structure similar to each above-mentioned embodiment, The detailed description is abbreviate | omitted here.

  FIG. 15 shows a state where a color image and a monochrome image are mixed and displayed on the screen in the present embodiment. On the display screen 57 of the panel 55, a window 58 of a 3D moving image screen and a window 130 of a monochrome image are displayed in addition to a window 59 formed of a normal text screen. Here, the window 58 of the 3D moving image screen is 30-bit color, and the window 130 of the monochrome image is a 14-bit single color screen. It is possible to display such different types of mixed images on the panel 55 described in the first and second embodiments.

FIG. 16 is an explanatory diagram showing a block configuration and a control flow for executing processing in the present embodiment. In the figure, the panel control chip 51 has an FRC / dither circuit 131 for increasing gradation expression. Further, the post processor 70 is provided with a conversion circuit 132 that performs gamma adjustment and color matching processing, and a FIFO buffer 133 for taking a read / write timing with the panel memory 52.
First, a 30-bit color process will be described. Image data sent in 32 bits from a system application is input to the graphics chip 11 via the system bus 13. This image data is processed by the graphics chip 11 and sent to the panel control chip 51 via the digital I / F line 49. The digital I / F line 49 is 24 bits and is transferred using a data format described later. The sent image data is converted back to 30 bits by the post processor 70 and written into the panel memory 52. The format of the image data at this time is 10 bits each for R / G / B as shown in the memory data format of FIG. The image data read by the FRC / dither circuit 131 is converted into 8-bit data for each of R / G / B and transferred from the panel data output 54 to an X-driver (not shown) of the panel 55. The FRC / dither circuit 131 functions to increase the gradation expression by temporal distribution and spatial distribution for each of R / G / B.

  FIGS. 17A and 17B show examples of the data format of the digital I / F line 49. FIG. FIG. 17A shows TMDS (Transition Minimized Differential Signaling) data transfer. FIG. 17B shows 30-bit color bit assignment using TMDS. The three TMDS0 to TMDS2 in FIG. 17A correspond to three signals other than the clock, and each R / G / B is coded from 8 bits to 10 bits for data transfer. For convenience, each dot is drawn vertically, but the coded data is actually transferred serially. Coding is performed for error recovery and DC balance when inserting a synchronization signal, and only 8 bits of R / G / B can be used as actual data. In the case of 24-bit color, R / G / B 8-bit data is used as it is.

  Here, in the case of 30-bit color, 32 bits (8 bits × 4) are used as one dot data by sequentially shifting as shown in FIG. Therefore, even if the content can be sent by 4 dots by 24-bit transfer, it is reduced to 3 dots by 30-bit transfer. In this method, the data transfer mode can be specified in the header of the packet, and data is processed in accordance with the specified transfer mode. In practice, 2 bits of control bits are added to each dot in 30-bit transfer, and these 2 bits are dynamically assigned in the data transfer mode. For example, it is used as a write-per-bit (a mode for writing only when the bit is ON) or a vertical parity bit to enhance data error checking. Thus, since the transfer mode can be set freely, 48-bit color and 64-bit color can be easily supported on the protocol.

Next, a 14-bit monochrome display and a method of mixing these will be described. In FIG. 16, when processing is performed with 16 bits on the application side, for example, the data is transferred to the system bus 13 with 16 bits. In the digital I / F line 49 output from the graphics chip 11, the data is transferred by being put into normal 24 bits. However, it is necessary to set the data transfer mode to 16-bit monochrome transfer at this time. The 16-bit data is converted into 30 + 1 bit data by the conversion circuit 132 in the post processor 70 in the panel control chip 51. The conversion circuit 132 performs gamma adjustment and color matching processing as described above. In this 30-bit configuration, the upper 6 bits of monochrome are common to R / G / B, and the lower 8 bits are assigned to gamma adjustment and color matching for each R / G / B (8 bits x 3), for a total of 30 bits It is said. One bit is added to the identification bit, and 31 bits are written in the panel memory 52. When the identification bit is ON, monochrome processing is performed, and when it is OFF, normal color processing is performed.
FIG. 16 shows examples of these memory data formats. R / G / B is 8-bit color, 10-bit color, and 14-bit monochrome. In the 14-bit monochrome, 6 bits out of the 14 bits of G are used as the common bits.
In order to indicate to the panel side 50 whether it is monochrome or color, prior to the data transfer, for example, in the packet video data format shown in FIG. For example, 1 bit specifies monochrome or color.

In the present embodiment, the subsequent processing is changed according to the identification bit written in the panel memory 52 in this way. The image data read from the panel memory 52 is discriminated whether it is monochrome or not by the identification bit. In the case of monochrome, the lower 6 bits are added to the upper 6 bits common to R / G / B, and 6 bits Is converted into 8 bits for each of R / G / B by the FRC / dither circuit 131 and transferred to the X-driver of the panel 55.
This identification bit can be used for processing such as gamma adjustment, color matching, and scaling.

As described above, according to the present embodiment, the number of expression colors is increased, the transfer speed of image data is free, and the transfer format of image data is free, so that gamma adjustment and color matching can be performed. The processing can be performed without any problem on either the system side or the panel side. For example, it is possible to perform processing on the system side and transfer the data in the 30-bit color mode. In addition, the panel side has a conversion table, and the data transferred in the 24-bit color mode is selected. It is also possible to convert to 30-bit color.
Furthermore, since an identification bit for determining whether the color is monochrome or not is used, it is freed from separately processing R / G / B in the case of monochrome. As a result, it is possible to display a monochrome image composed of multiple bits such as 14 bits, and for example, it can be applied to an X-ray display that requires a multi-tone monochrome.

  Further, as an application example in the present embodiment, there is one that partially displays a DVD (Digital Versatile Disc) screen. Original DVD data has been compressed, and conventionally it has been necessary to uncompress the data using a system and a graphics chip. On the contrary, if the decompressed part is divided and the data in a compressed state can be transferred, the transfer amount is greatly reduced. In the case of a high-definition panel, since the amount of data transferred between the host side 10 and the panel side 50 is large, if the data is compressed, for example, the bandwidth (number of cables) using a 1/10 cable is improved. Further, as described above, for example, the user wants to display a still image with an increased number of colors of 10 bits each for R / G / B, while the OS controls the remaining window portion with 8 bits for R / G / B. May have. Even in such a case, since it can be divided and processed, it can be easily supported. Further, conversion of color adjustment such as gamma can be similarly controlled for each window. According to this embodiment, even for copyrighted data such as a DVD that is expected to become a problem in the future, it can be applied to encrypting and transferring only the display portion. is there.

As described above, the first to third embodiments have been described in detail. However, according to these embodiments, even when outputting ultra-high definition in which dots cannot be seen, the capacity is insufficient or the processing speed is delayed. It is possible to display without degrading the performance of the entire system.
In addition, even when the definition is further advanced, it is not necessary to change the physical interface every time, and the practicality and the economy are excellent.

1 is a block diagram showing an embodiment of an image display system to which the present invention is applied. It is a figure for demonstrating the graphics system by the side of the host demonstrated in FIG. It is a block diagram which shows the internal structure of a preprocessor. It is a block diagram which shows schematic structure of the display circuit in the panel side. 2 is a block diagram showing an internal configuration of a post processor 70. FIG. 4 is a flowchart showing processing performed by a preprocessor 20 on a host side 10 and a post processor 70 on a panel side 50. (a), (b), (c) is explanatory drawing which showed the comparison and data format of the data transfer of a prior art and this Embodiment. It is explanatory drawing for demonstrating the structure of the display screen in this Embodiment. (a), (b) is explanatory drawing for demonstrating the process for every data, and its processing amount. It is explanatory drawing for demonstrating the transfer system of the image data using the packet used in this Embodiment. It is a block diagram for demonstrating the system structure in the multi-system in this Embodiment. It is explanatory drawing which shows the structure of the synchronous process of the host side 10 and the panel side 50 in this Embodiment. It is a figure which shows the process flow in this Embodiment. It is a timing chart for demonstrating the synchronous processing operation by a multi-system. It is the figure which showed the state where the color image and the monochrome image were mixed and displayed on the screen. It is explanatory drawing which shows the block configuration and control flow which perform the process in Embodiment 3. FIG. (a), (b) is the figure which showed the data format example of the digital I / F line 49. FIG. It is a system block diagram which showed one means for eliminating the power shortage of the graphics chip in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Host side, 11 ... Graphics chip, 12 ... Graphics memory, 13 ... System bus, 14 ... Graphics memory bus, 15 ... Interface (I / F) transceiver, 16 ... DAC, 17 ... Address generator 20 ... Preprocessor, 21 ... Input latch, 26 ... Prehandler, 33 ... Job (JOB) number output register, 34 ... Job (JOB) number input register, 35 ... Syncback register, 36 ... Error status register, 37 ... DDC Handler 38. Multiplexer 40 Synchronous control circuit 49 Digital interface (I / F) line 50 Panel side 51 Panel control chip 52 Panel memory 53 Interface (I / F) receiver 54 ... Panel data output, 55 ... Panel, 61 ... Input FI FO, 62 ... output FIFO, 63 ... input address register, 64 ... output address register, 65 ... H counter, 66 ... V counter, 68 ... external data bus, 69 ... in-panel data bus, 70 ... post processor, 71 ... input Latch, 78 ... Post handler, 86 ... DDC controller, 87 ... Scaling circuit, 88 ... FIFO memory, 90 ... Synchronization control circuit, 91 ... Job (JOB) number register, 100 ... System, 111 ... Synchronization control circuit, 115 ... DDC Handler 116, job (JOB) number controller, 117, job (JOB) number input register, 118, job (JOB) number output register, 119, comparator, 120, internal bus controller, 121, internal bus

Claims (2)

A host display characteristics and the amount of data required to perform a plurality of different applications, a display for displaying images, and a digital interface for transferring image data before expansion comprising a plurality of from the host with respect to the display An image display system comprising:
The host includes a preprocessor for preprocessing image data before development,
The display is
A panel divided into a plurality of sub-panels;
A plurality of post-processors that expand the acquired plurality of image data before expansion and control the sub-panel;
A plurality of panel memories connected to each of the plurality of post processors and storing the developed image data,
The digital interface transfers image data before development from the host side to the display side, and changes a transfer format according to an application among a plurality of applications executed by the host. system. The digital interface transfers the image data before development by a packet and designates the data transfer mode in the packet to transfer the image data before development ,
2. The image display system according to claim 1, wherein image data before expansion is expanded based on the designated data transfer mode.

Images