JPH11149283A - Synchronizing system of multidisplay - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multidisplay image without flicker by simultaneously collectively indicating a changeover of double buffers from a host PC to all display control devices so as to synchronize a plurality of the display control device among them. SOLUTION: A host PC 100 controls the frame completed command ready bits 116, 135 of all display control device in detail. For judging completion of plotting processes in all the display control devices, the logical product of all the frame completion command ready bits is obtained in the host PC 100, and when the plotting process are judged to be completed, all frame completion command execution approval bits 115, 134 are simultaneously set to allow the changeover process of double buffers 112, 132. Hereby, the display control devices are synchronized with each other by simple hardware to make display possible, and the multidisplay image without flicker can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device having a multi-display configuration capable of displaying drawing information over a plurality of screens at high speed without flickering.

[0002]

2. Description of the Related Art A general example of a multi-display will be described with reference to FIG. The drawing application running on the host PC has a drawing area 500 of the application itself, and performs a drawing process on primitives existing in this area. The drawing data in the drawing area is connected to the connected display control devices 501 to 5.
03 and subjected to drawing processing. The display control device has drawing areas 510 to 512 assigned to them, and performs drawing processing of drawing data transferred from the host PC corresponding to the drawing areas. The processed drawing data is subjected to drawing processing by drawing processing units 504 to 506, respectively, and displayed on display devices 507 to 509. This realizes a multi-display composed of a plurality of display devices.

As a conventional multi-display synchronization method, Japanese Patent Laid-Open No. 9-204164 discloses a display processing unit connected to a plurality of displays and a display control unit for controlling the display processing unit. In the multi-display display control device, the display control unit is configured to perform drawing processing performance measuring means for measuring the drawing processing performance of the display processing unit, and to perform drawing in accordance with the display processing unit having the slowest drawing processing performance measured by the drawing processing performance measuring unit. A drawing data amount changing unit that changes the data amount; and a drawing data generating unit that generates drawing data with the changed drawing data amount based on an instruction from the drawing data amount changing unit. By synchronizing the amount of drawing data, synchronization between multiple displays such that one frame is completed on all screens within a certain period of time Expression has been described.

[0004]

Generally, in a display control device having a multi-display configuration, drawing data subjected to clipping processing corresponding to a drawing area assigned to each display control device is transferred to a drawing processing unit and subjected to drawing processing. . Here, if there is a particular time difference between the drawing data transferred to each display control device and a difference in the data amount of the drawing data subjected to the clipping processing to a certain extent or more, the drawing between the respective display control devices is performed. There is a problem in that the processing is varied, and the drawing data to be displayed in one frame is displayed out of the vertical synchronization between the respective displays, causing flickering. In the conventional multi-display, in order to solve this problem, the display control devices are synchronized in the manner described above. However, when trying to display data created by a drawing application which becomes complicated in recent years such as three-dimensional graphics, This method has a problem that it takes an enormous amount of time to process data. Further, when the amount of data is reduced at the time of processing, there is a problem that the quality of multi-display display deteriorates.

It is an object of the present invention to provide a flicker-free multi-display image by synchronizing display control devices with simple hardware.

[0006]

An object of the present invention is to provide a frame memory having a double buffer structure for storing an output result of a drawing processing section, and to determine that writing of drawing data for one frame has been completed, and then to switch the double buffer. In a display control device having a device for switching and outputting to a display device in synchronization with a Vsync signal, the drawing processing status of each display control device is monitored by, for example, a host PC. This is achieved by the host PC instructing all the display control devices to switch the double buffer after the host PC determines that the drawing processing has been completed.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and shows a hardware configuration of a display control device having a two-screen configuration. In FIG. 1, a display control device 101 is a bus 15 that transfers drawing data sent from an upper processing system to a drawing processing unit 111.
1, a drawing processing unit 111 that performs drawing processing of the received drawing data, a frame memory 112 having a double buffer configuration that stores drawing processing results, and a double buffer switching instruction from the display synchronization control unit 110 and a double synchronization in synchronization with a Vsync signal. A selector 113 for switching the buffer 112; a display synchronization control unit 110 for controlling the selector 113; a signal 120 for notifying the display synchronization control unit 110 that one frame of drawing processing has been completed in the drawing processing pipeline of the drawing processing unit 111; From the display synchronization control unit 110 to the selector 113
12 instructing the switching of the double buffer 112 to
1, a Vsync generation unit 114 for generating a Vsync signal, and a Vsync synchronization signal 15 for synchronizing the Vsync signal between the display control devices.
It consists of 0.

The display synchronization control unit 110 further includes a frame end command ready bit 11 set when the drawing processing unit 111 completes the drawing process for one frame.
6. It has a frame end command execution permission bit 115 which is set by the host PC 100 when the drawing processing is completed in all display control devices. Also, a frame end command ready bit state signal 154, 155 and a double buffer 1 for causing the host PC 100 to monitor the drawing processing status of the two display control devices 101 and 102, respectively.
The display control device and the host P are controlled by a frame end command execution permission signal
C is connected.

The overall operation will be described below with reference to FIGS. 2, 3 and 4 and with reference to FIG. Drawing data 15 input to the two display control devices 101 and 102, respectively
Reference numeral 1 152 includes drawing data for one frame and a frame end command indicating the end of drawing processing for one frame attached to the end of the drawing data by the display driver as shown in FIG. Each drawing data is transferred to the drawing processing units 111 and 131 and processed by the drawing processing pipeline (step 2a in FIG. 2).
), And the processing results are stored in the frame memories 112 and 132 each having a double buffer structure. Here, the usage of the double buffer is publicly known and the description thereof is omitted.

FIG. 4B is a drawing processing section 1 shown in FIG.
11 shows how the drawing data is displayed in the drawing processing pipelines 11 and 131. The original picture data 401 is transferred to the drawing processing unit as polygon data. The rendering processing unit renders the pixel data of the polygon data in the frame memory (402) and performs rendering processing, and performs rendering development until a frame end command is transferred to one frame memory (403). After that, the selector switches the frame memory of the double buffer configuration, and the original picture is displayed on the display device (4).
04).

As shown in FIG. 6, the output of the selector 602 is output to a display through a DAC (digital-to-analog converter) 601. In fact, host P
There are two types of drawing data output from C (drawing application): normal drawing data and mouse cursor data. The normal drawing data is drawn by the drawing processing unit and input to the DAC 601. The host PC is used only for a display control device having a drawing area where a mouse cursor exists because there is no need to perform drawing processing.
Directly from the DAC 601 without passing through the drawing processing unit.
And output to the display.

When the rendering processing for one frame is completed, a frame end command (End Frame instruction in FIG. 4A) is provided at the last stage of the rendering processing pipeline in the rendering processing units 111 and 131.
Arrives, the drawing processing unit 111,
131 sets the corresponding frame end command ready bits 116 and 135 (step 2 in FIG. 2).
b). The host PC 100 monitors the frame end command ready bits 116 and 135 of all the display control devices one by one (see step 3a in FIG. 3). In the PC 100, the logical AND of all the frame end command ready bits is taken, and if it is determined that the drawing processing has been completed, all the frame end command execution permission bits 115 and 134 are simultaneously set to switch the double buffer. (Step 3b in FIG. 3).

Although this processing is described in the form of ANDing with hardware in FIG. 1, the determination and the setting of the frame end command execution permission bits 115 and 134 are realized by software on the host PC. It can be easily analogized that this is also possible. In the display synchronization control units 110 and 130 permitted to perform the processing, the selector 1 is synchronized with the Vsync signal.
13 and 133 are instructed to switch the double buffers 112 and 132, and the double buffer switching process is executed (step 2c in FIG. 2).

At the same time, the frame end command ready bits 116 and 135 and the frame end command execution permission bits 115 and 134 are reset, and the drawing processing unit 11
1, the frame end command held at the last stage of the drawing processing pipeline is deleted, drawing processing of drawing data of the next frame is started, and the processing result is stored in the other frame memory of the double buffer configuration. Starts to be written (step 2d in FIG. 2).

As described above, a plurality of display control devices can be synchronized with a simple hardware configuration, and a high-speed, flicker-free multi-display can be realized.

[0016]

According to the present invention, in a display control device having a multi-display configuration, it is possible to perform display with synchronization between the display control devices with simple hardware, and to configure a flicker-free multi-display. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a hardware configuration according to an embodiment of the present invention.

FIG. 2 is a diagram showing a processing flow of a display synchronization control unit in the display control device.

FIG. 3 is a view showing a drawing process monitoring flow of a host PC.

FIG. 4 is a view showing an example of drawing data transferred to a drawing processing unit and a flow of the processing;

FIG. 5 is a diagram showing a configuration of a general multi-display.

FIG. 6 is a diagram showing a flow of mouse cursor data when the data is transferred.

[Explanation of symbols]

100: Host PC, 101, 102: Display control device,
110, 130: display synchronization control unit, 111, 131: drawing processing unit, 112, 132: double buffer, 113,
133 ... selector, 114 ... Vsync generator, 115,1
34 ... frame end command execution permission bit, 116,
135 ... Frame end command ready bit.

Claims (1)

[Claims] An apparatus for performing drawing processing of drawing data transferred from a host processing apparatus, a frame memory having a double buffer structure for storing output results of the processing apparatus, and writing of drawing data for one frame are completed. The double buffer is switched in synchronization with a Vsync (vertical synchronization) signal, and a plurality of display control devices having a multi-display configuration having a device for outputting to a display device, a drawing processing status of each of the display control devices. Is monitored by the upper host PC, and after the host PC determines that the drawing processing is completed in all the display control devices, the host PC instructs all the display control devices to switch the double buffer simultaneously to all the display control devices. A multi-display synchronization method characterized in that a plurality of display control devices are synchronized with each other.