JPH075834A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To enable the parallel display driving of divided screens by a buffer memory with the capacity of one divided screen related to a liquid crystal display device bisecting a liquid crystal screen and display-driving them in parallel. CONSTITUTION:The buffer memory 24 provided with the storage capacity of one of divided screens 26, 28 is provided, and the display data of the divided screens 26, 28 are outputted alternately from a display data output means 34. By a display control means 42, the display data from the display data output means 34 are displayed on an upper screen 26, and the display data stored previously in the buffer memory 24 are read out, and are displayed on a lower screen 28 through a latch means 36 while matching timing with the display data from the display means 34. Then, the display data from the display data output means 34 are stored in the same area of the buffer memory 24. When the output of the display data of one divided screen end, the outputs from the display data output means 34 and from the latch means 36 for the divided screens 26, 28 are switched over each other so as to be mutually replaced by a switch means 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used in a small notebook computer or the like, and more particularly to a liquid crystal display device in which a liquid crystal display screen is divided into two and driven in parallel.

[0002]

2. Description of the Related Art Conventionally, in a portable notebook type personal computer, a liquid crystal display is used in order to reduce its size and weight. For example, if the liquid crystal pixels are 640 horizontal dots x 480 vertical dots, then a total of 30
This is 7,200 dots. In such a large-screen liquid crystal display, when the display drive is performed similarly to the CRT display, it takes time to display one screen because the operation speed of each liquid crystal element is slow, and the display quality is poor.

Therefore, in a large-screen liquid crystal display, for example, it is divided into upper and lower parts and the divided screens are driven in parallel to improve display speed and display quality. In the liquid crystal display device having such a screen division, as shown in FIG. 14, the liquid crystal of the liquid crystal display 102 having the two screens of the upper screen 104 and the lower screen 106 is converted from the data of the one screen output by the CRT control circuit 100. When converting to display data, two buffer memories 108 and 110 corresponding to each split screen are required.

Specifically, as shown in FIG. 14A, C
When the RT control circuit 100 outputs the display data A of a certain area of the upper screen 104, the data A is displayed at the corresponding display position of the upper screen 104, and the upper screen buffer memory 1
It is stored in 08. At the same time, the lower screen buffer memory 110
The data B in the same area of the lower screen, which has already been stored in, is read and displayed on the lower screen 106.

Upper screen 104 from CRT control circuit 100
When the output of the display data for is completed, the state is switched to the state of FIG. In this case, the CRT control circuit 100 outputs the display data B in a certain area of the lower screen 106, displays the data B at the corresponding display position on the lower screen 106, and stores it in the lower screen buffer memory 110. At the same time, the data A in the same area of the upper screen which is already stored in the upper screen buffer memory 108 is read and displayed on the upper screen 104.

FIG. 15 is a timing chart showing the display operation of the conventional liquid crystal display device. Data at a certain address in the upper screen buffer memory 108 and corresponding data at a certain address in the lower screen buffer memory 110. Input / output of is shown on the time axis.

[0007]

However, in such a conventional liquid crystal display device, there is a problem that the memory capacity increases because two buffer memories corresponding to the divided upper and lower screens are required. For example, in the case of horizontal 640 dots × vertical 480 dots, the memory capacity required for the buffer memory in the conventional apparatus is 640 × 480 = 307,200 bits when one pixel is 1 bit in black and white. In reality, one 256 Kbit memory is not enough, so it is necessary to use two 256 Kbit memories or one 1 Mbit memory.

Further, as is apparent from the time chart of FIG. 15, it can be seen that the buffer memories are alternately used at the corresponding upper and lower addresses. That is, there is a problem that the upper and lower buffer memories are effectively used only for half the period and the memory utilization efficiency is low. The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a liquid crystal display device capable of parallel display driving of divided screens with a buffer memory having a capacity of one divided screen.

[0009]

FIG. 1 is a diagram for explaining the principle of the present invention. First, the present invention is directed to a liquid crystal display device that controls the display of divided screens 26 and 28 that are equally divided into two simultaneously (in parallel). In the present invention for such a liquid crystal display device, a buffer memory 24 having a storage capacity for one of the split screens 26 and 28 is provided, and the split screen 26 is output from the display data output means 34 such as a CRT display control circuit. , 28
The display data of is output alternately. Further, the display control means 42
According to the display data output means 34, one of the divided screens 26 and 28 corresponding to the display data, for example, FIG.
Is displayed on the upper screen 26 and the display data previously stored in the buffer memory 24 is read to display the display data from the display data output means 34 on the other split screen, for example, the lower screen 28. indicate. At the same time, the display data from the display data output means 34 is stored in the same area of the buffer memory 24.

Here, the display data output means 34 divides the display data for one divided screen into word data in which a predetermined number of display pixels n is one unit and sequentially outputs the data, and the buffer memory 24 outputs the data in word units. Read and write. The display control means 42 reads the word data stored earlier from the same area of the buffer memory 24 and holds it in the latch means 36 prior to the output of the word data from the display data output means 34, and the display data output means 34. The output of the read data latched by the latch means 36 in synchronization with the output of the word data from and is displayed on the corresponding divided screen is repeated. Further, the display data output means 34
When the output of the display data for the split screens is completed, the display data output means 3 for the split screens 26 and 28 is displayed by the switching means 50 as shown in FIGS. 1 (a) and 1 (b).
4 and the output of the latch means 36 are switched so as to be exchanged. The latch means 36 has a data width for holding one word data.

The display data output means 34 sequentially outputs the display data for two divided screens at every predetermined vertical scanning period T _V , and the display control means 42 outputs the display data for one divided screen within the vertical scanning period. The display data output means 34 for the divided screens 26 and 28 is output by the switching means 50 each time the output is completed.
And the output of the latch means 36 are switched so as to be exchanged.

[0012]

The liquid crystal display device of the present invention as described above has the following actions. First, the buffer memory 24 is set to one, and at the timing when the display data output means (CRT control circuit) 34 sends the data corresponding to the upper screen 26 of the liquid crystal display 22, as shown in FIG. Has switched to the straight connection shown in the figure, and the previously stored data is read from the buffer memory 24 and displayed on the lower screen 28. At this time, the display data for the upper screen 26 is stored in the read area of the buffer 24.

Display data output means 3 for the upper screen 26
When the output of the display data from 4 is completed, the switching means 50 switches to the cross connection as shown in FIG. At the timing when the display data output means 34 sends the data corresponding to the lower screen 28 of the liquid crystal display 22, the data stored in FIG. 1A is read from the buffer memory 24 and displayed on the upper screen 26.

At this time, the display data for the lower screen 28 is stored in the read area of the buffer 24. The data read from the buffer memory 24 is temporarily latched in order to align the timing of data output to the liquid crystal display 22 by the reading of the buffer memory 24 with the data from the display data output means 34. By repeating a series of these operations, the buffer memory 24 can be shared by the upper and lower screens.

[0015]

FIG. 2 shows the hardware configuration of the present invention, and shows an example in which the liquid crystal display device of the present invention is applied to a notebook personal computer. In FIG. 2, 10 is CP
U is connected to the internal bus 12 from the CPU 10 to the ROM 14 and the DRAM 16 in which programs are fixedly stored. For the internal bus 12, the video RAM 1
8 is connected, and the display data created under the control of the CPU 10 is stored in screen units.

The video RAM 18 functions as a frame memory, and since this embodiment takes monochrome display as an example,
It has a depth of 1 bit per pixel. Of course, for color display, a frame memory is provided for each of the R, G, and B components, and the depth of data for each pixel is, for example, 8 bits. Further, a display control circuit 20 is provided on the internal bus 12 of the CPU 10, and the display control circuit 20 reads the display data of the video RAM 18 based on the command from the CPU 10,
It is displayed on the liquid crystal display 22. Liquid crystal display 2
Reference numeral 2 is composed of an upper screen and a lower screen divided into upper and lower equal areas, and the display drive of the two divided screens is performed in parallel.

The display control circuit 20 is provided with a buffer memory 24 used for driving the parallel display of the liquid crystal display 22 divided into an upper screen and a lower screen. The buffer memory 24 has a memory capacity corresponding to one pixel of the divided screen of the liquid crystal display 22, and the memory capacity is half that of the conventional device shown in FIG. FIG. 3 shows the details of the display control circuit 20 of FIG.
Shown with. In FIG. 3, reference numeral 30 denotes a CRT display control circuit, which reads the display data for one screen stored in the video RAM 18 at a predetermined horizontal and vertical scanning cycle to display C.
Output as RT display data. In the CRT display control circuit 30, the relationship between the upper screen 26 and the lower screen 28 obtained by dividing the liquid crystal display 22 is not taken into consideration.

The CR from the CRT display control circuit 30
The T display data is serial data that is a one-dimensional bit stream, and is input to the shifter circuit 32 to be converted into parallel data having a predetermined length n. A latch circuit 30 is provided subsequent to the shifter 32, and every time the shifter 32 shifts by n bits, the latch circuit 34 latches the parallel output from the shifter circuit 32.

The outputs of the latch circuit 34 are selectors 38, 4
Given to 0. The selector 38 is the liquid crystal display 22.
The display data for the upper screen 26 is selected and output. The selector 40 selectively outputs display data for the lower screen 28 of the liquid crystal display 22. In this embodiment, the case where the liquid crystal display 22 is composed of 640 dots horizontally × 480 dots vertically 307,200 pixels is taken as an example.
When the liquid crystal display 22 is vertically equally divided into two, the upper screen 26 and the lower screen 28 are each a divided screen of 153,600 pixels of horizontal 640 dots × vertical 240 dots.

On the other hand, a buffer memory 24 is provided following the latch circuit 34. The buffer memory 24 has a memory capacity corresponding to 153,600 dots which is the number of display pixels of the upper screen 26 and the lower screen 28 of the liquid crystal display 22. In this embodiment, since a monochrome display is taken as an example, one dot corresponds to one bit, so that the memory capacity required for the buffer memory 24 is 153,600 bits.

Therefore, one 256K-bit DRAM may be used for mounting. Buffer memory 24
The display data is written from the latch circuit 34 with respect to. The read data from the buffer memory 24 is held in the latch circuit 36. The display data held in the latch circuit 36 is output to the selectors 38 and 40, and selected by either one of the selectors to select either the upper screen 26 or the lower screen 28.
Is displayed in.

The latch circuit 36 is provided for timing the output of the read data read from the buffer memory 24 to the liquid crystal display 22 and the display data directly output from the latch circuit 34. Selector 3
8 and 40, the selector 38 connects between ac and the selector 40 connects between bc at the timing when the display data is output from the latch circuit 34 to the upper screen 26. Then, from the latch circuit 34 to the lower screen 28
When it comes to the output timing of the display data for, the selector circuit 38 is switched to the connection between bc and the selector circuit 40 is switched to the connection between ab.

The control of each circuit portion from the CRT display control circuit 30 to the liquid crystal display 22 is performed by a control signal shown by a broken line from the LCD display control circuit 42 functioning as a display control means. That is, the LCD display control circuit 42 inputs the synchronizing signal and the display clock from the CRT display control circuit 30, and based on this input signal, a latch output signal for holding the latch circuits 34 and 36 and an address for the buffer memory 24. And read command or write command, and further selector circuit 3
The select signals for 8 and 40 are generated.

The display data handled by the display control of the present invention is determined by the number n of dots displayed on the liquid crystal display 22 at one time. For example, the liquid crystal display 22
When displaying 8 dots at a time, the n = 8-bit data is used as one display data for reading / writing and transfer display to / from the buffer memory 24. This n-bit display data will be described as 1-word display data in the following description. That is, in the following description, display data means display data for one word of n = 8 bits.

Next, the basic operation of the display control of the present invention will be described with reference to FIGS. FIG. 4 shows a state in which the first display data A1 for the upper screen 26 is held in the latch circuit 34 while the buffer memory 24 stores the display data B1 to Bn previously used for displaying the lower screen 28. . That is, the latch circuit 34 reads the buffer memory 24 before latching the first display data A1 with respect to the upper screen 26, reads the first display data B1 of the lower screen 28 that has already been stored, and holds it in the latch circuit 36. . When the display data B1 is held in the latch circuit 36, the latch circuit 34 latches new display data A1 in the upper screen 26.

Next, as shown in FIG. 5, the display data A1 of the latch circuit 34 is displayed at the head position of the upper screen 26, and at the same time, the display data B1 of the latch circuit 36 is displayed at the head position of the lower screen 28. Upper screen 2 for data A1
Simultaneously with the display to 6, the new display data A1 is added to the area of the display data B1 of the buffer memory 24 which has already been read.
Write as. The read operation and the write operation for the buffer memory 24 in FIGS. 4 and 5 are performed under the designation of the same address.

Next, as shown in FIG. 6, the buffer memory 2
The next display data B2 is read from 4 and the latch circuit 36
Next, the next display data A2 for the upper screen 26 is stored.
Are held in the latch circuit 34. Subsequently, as shown in FIG. 7, the display data A2 and the latch circuit 3 of the latch circuit 34 are displayed.
The display data B2 of No. 6 are displayed at the corresponding positions on the upper screen 26 and the lower screen 28, respectively. At the same time, the latch circuit 3
The display data A2 of No. 4 is written in the same area as the already read display data B2.

FIG. 8 shows the display for the upper screen 26 and the lower screen 28 of the final display data An and Bn, and the display data A for the upper screen 26 for the liquid crystal display 22 is thereby displayed.
The output of 1 to An ends. Next, as shown in FIG. 9, the first display data B1 for the lower screen 28 of the liquid crystal display 22 is latched in the latch circuit 34. When switching from FIG. 8 to FIG. 9, the selector circuits 38 and 40 shown in FIG.
Output of the lower screen 28, the output of the latch circuit 36 the upper screen 2
The connection can be switched to a cross connection of 6.

Further, prior to holding the first display data B1 for the lower screen 28 in FIG. 9 in the latch circuit 34, the upper screen 26 stored in the buffer memory 24.
The first display data A1 of the latch circuit 36 is read.
Held in. Then, as shown in FIG. 10, the display data B1 of the latch circuit 34 is displayed at the head position of the lower screen 28, and at the same time, the display data A1 of the latch circuit 36 is displayed on the upper screen 2
It is displayed at the first display position of 6. The display data B1 from the latch circuit 34 is simultaneously stored in the buffer memory 24.
Will be written in the same area as the display data A1 that has been read. The processing shown in FIGS. 9 and 10 is similarly repeated for the remaining display data B1 to Bn and A2 to An.

FIG. 11 is a timing chart showing the overall operation of the display control in the embodiment of FIG. First, the vertical synchronizing signal is repeatedly generated at every vertical scanning cycle T _V. The select signal is inverted with a delay of T1 with respect to the fall of the vertical synchronizing signal. The select signal connects the acs of the selector circuit 38 and the bc of the selector circuit 40 at the L level.

When the select signal goes high, the selector circuits 38 and bc are connected to each other, and the selector circuit 40 is connected.
Connect between AC. C from the CRT display control circuit 30
The RT display data is performed in synchronization with the select signal, the display data for the upper screen is output during the L level period of the select signal, and the display data for the lower screen is output during the latter half H level period.

Here, the display data output in the latter half of the entire cycle is indicated by A, the display data output in the first half of the currently focused cycle is indicated by B, and the display data output in the latter half is indicated by C. Focusing on the period from time t1 to t2, the CRT output during the L level period of the select signal T1 time after time t1.
The display data B is supplied as write data to the buffer memory 24 at the same timing and is written therein.

At the same time, the CRT display data B is supplied to the liquid crystal display 22 as upper screen display data. On the other hand, the display data A written in the buffer memory 24 in the latter half of the entire cycle is read as the read data of the buffer memory 24 in parallel with the output of the CRT display data B, and this read data is used as the lower screen display data in the liquid crystal display. 22 is displayed.

Next, the next CRT display data C, which is output by inverting the select signal to the H level, is similarly written as write data for the buffer memory 24, and simultaneously displayed on the liquid crystal display as lower screen display data. . Further, the display data B written in the buffer memory 24 last time is read out as the buffer memory read data, and this read data B is supplied to the liquid crystal display as the upper screen display data.

Although FIG. 11 shows data units for divided screens, in actuality, processing is performed in word units of n = 8 bits. FIG. 12 is a flowchart showing the details of FIG. 11, and shows a timing chart of display data unit of 1 word of n = 8 bits. First, as shown in CRT display data input from the CRT display control circuit 30, serial data is input to the latch circuit 34 as a bit stream. 8 latch circuits 34
The latch stroke signal is received every time bit data is input, and the display data for one word is output in parallel.

For example, the input data from time t1 to t2 is latched and output as 8-bit display data D1. The output data D1 of the latch circuit 34 is directly supplied to the upper screen 26 and displayed. On the other hand, prior to the latch output of the display data D1, data reading from the buffer memory 24 of the corresponding address stored in the previous cycle is performed.

That is, the display data D from the latch circuit 34
Prior to the output of 1, the address A of the buffer memory 24
The buffer memory 2 in which DR1 is generated and is simultaneously indicated by negative logic
A read command for 4 is generated. Therefore, from the buffer memory 24, the address A stored in the previous cycle is
Read data D0 from DR1 is read and held in the latch circuit 36.

Then, the display data D from the latch circuit 34
The read data D0 held in the latch circuit 36 is output to the lower screen in synchronization with the output of 1 to the upper screen. The same address ADR1 is set for reading the display data D0 from the buffer memory 24 and writing the display data D1 to the next buffer memory 24. Similar processing is repeated for the CRT display data D2 input at the next time t2 to t3.

FIG. 13 is a timing chart showing the details of the read operation and the write operation in the generation period of the address ADR1 of the buffer memory 24 of FIG. That is, the read operation of the buffer memory 24 by the read command is performed prior to the output of the output data D1 from the latch circuit 34, and the previous display data D0 already stored in the buffer memory 24 is read and held in the latch circuit 36. To do.

When the read operation is completed at time t1, the display data D1 is output from the latch circuit 34, and at the same time, the read display data D0 is output from the latch circuit 36,
Display data D1 and D0 in parallel for the upper screen and the lower screen
Is displayed. At the same time, a write command is generated, the display data D1 output from the latch circuit 34 is written to the same address in the buffer memory 24, and the writing is completed at t1 ′. Therefore, after the time t1 ′, the stored data at the address ADR1 in the buffer memory 24 is updated to the display data D1 output from the latch circuit 34.

In the above embodiment, the processing operation in which n = 8 bits was used as a data unit of one word was taken as an example, but the bit number n of one word can be appropriately determined as necessary. it can. In the above embodiment, the case where the display control circuit is configured by hardware is taken as an example.
It goes without saying that the display control may be performed by the program control by.

[0042]

As described above, according to the present invention, it is possible to share one buffer memory between two divided screens when driving two equally divided screens in parallel. , Significantly reduce the buffer memory capacity,
The utilization efficiency of the memory can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a hardware configuration diagram of the present invention

FIG. 3 is a configuration diagram of an embodiment of the present invention showing details of the display control circuit of FIG.

FIG. 4 is an explanatory diagram of a display operation of the present invention.

FIG. 5 is an explanatory diagram of a display operation of the present invention (continued)

FIG. 6 is an explanatory diagram of a display operation of the present invention (continued)

FIG. 7 is an explanatory diagram of a display operation of the present invention (continued)

FIG. 8 is an explanatory diagram of a display operation of the present invention (continued)

FIG. 9 is an explanatory diagram of the display operation of the present invention (continued)

FIG. 10 is an explanatory diagram of a display operation of the present invention (continued)

FIG. 11 is a timing chart showing the display operation of the present invention.

FIG. 12 is a timing chart showing details of FIG. 11.

FIG. 13 is a timing chart showing details of reading and writing with one address in FIG.

FIG. 14 is an explanatory diagram of a conventional device.

FIG. 15 is a timing chart showing a display operation of a conventional device.

[Explanation of symbols]

 10: CPU 12: Internal bus 14: ROM 16: DRAM 18: Video RAM 20: Display control circuit 22: Liquid crystal display (LCD) 24: Buffer memory 26: Upper screen 28: Lower screen 30: CRT display control circuit 32: Shifter Circuit 34: Latch circuit (display data output means) 36: Latch circuit 38, 40: Selector circuit 42: LCD display control circuit (display control means) 50: Switching means

Claims (5)

[Claims] 1. A split screen (26, 2) that is equally split into two.
In a liquid crystal display device for simultaneously controlling the display of 8), a buffer memory (24) having a storage capacity for one of the divided screens (26, 28) and display data of the divided screens (26, 28) are displayed. The display data output means (34) for alternately outputting and the display data from the display data output means (34) are displayed on one of the corresponding divided screens (26, 28) and are displayed in the buffer memory (24). The display data output means (34) for reading the display data previously stored and reading the display data.
Split screen (26, 2) that does not display the display data from
8) and the display data output means (3)
And a display control means (42) for storing the display data from 4) in the same area of the buffer memory (24). 2. The liquid crystal display device according to claim 1, wherein the display data output means (34) converts display data for one divided screen into word data in which a predetermined number of display pixels is set as one unit. Separately and sequentially output, the buffer memory (2
4) is a liquid crystal display device characterized in that data is read and written in word units. 3. The liquid crystal display device according to claim 2, wherein the display control means (42) stores the word data in the buffer memory (24) prior to outputting the word data from the display data output means (34). The previously stored word data is read from the same area, held in the latch means (36), and latched in the latch means (36) in synchronization with the output of the word data from the display data output means (34). The output of the read data and the display on the corresponding divided surface are repeated, and when the output of the display data for one divided screen by the display data output means (34) is completed,
A liquid crystal display device, characterized in that the switching means (50) switches the output of the display data output means (34) and the latch means (36) for the divided screens (26, 28). 4. A liquid crystal display device according to claim 3, wherein said latch means (34) has a data width for holding one of said word data. 5. A liquid crystal display device according to claim 3, wherein the display data output means has a predetermined vertical scanning period (T _V ).
The display data for two split screens are sequentially output for each time, and the display control means (42) switches the display means (5) every time the output of the display data for one split screen is completed within the vertical scanning period.
0) The liquid crystal display device is characterized in that the outputs of the display data output means (34) and the latch means (36) for the divided screens (26, 28) are switched so as to be switched.