JPH0731482B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) The present invention relates to an image display device suitable for a liquid crystal television.

(B) Conventional technology A conventional liquid crystal display device is divided into upper and lower parts, and pixel information is input and displayed for each of the divided parts.
83892, JP-A-58-193588, JP-A-59-281
No. 92, JP-A-59-176985, etc. are available, both of which can be used for television images and the like. However, as the number of pixels of the liquid crystal display increases, not only the responsiveness of the liquid crystal display but also the poor responsiveness including the driving element surface,
For example, in the case of a television video signal or the like which is transmitted as serial data at a predetermined speed, if this is directly transmitted to the driving element, an image with a rough and fluctuating screen is likely to be formed. Therefore, the screen memory is used to temporarily store the received video signal, and the read / write speed of the memory is changed by reading with a gap in the write timing, or the screen memory for two screens is alternately provided. It was used for writing and reading, and the video signals were regularly selected and sent to the driving element. However, these methods are not preferable because they require complicated timing control means and a large-capacity memory, or deteriorate image quality (particularly display roughness). Furthermore, in these screen display devices, the number of rows is almost determined by the number of scanning lines, but the number of columns depends on the liquid crystal display or its driver, and can perform a roughness of about 2 pixels to a CRT-like display exceeding 900 pixels. However, if the number of pixels is increased, not only the memory capacity must be increased, but also the handling of the video signal itself must be changed, resulting in lack of applicability.

C) Problems to be Solved by the Invention The present invention has been made to improve the above-mentioned points, has a relatively simple configuration, has good image quality, and is easy to respond to changes in the liquid crystal display. A device is provided.

D) Means for Solving Problems The present invention has a screen memory for one screen and a clock generating means for alternately writing and reading the screen memory,
Timing means for performing control such that writing of the screen memory-upper screen reading-writing-lower screen reading in one cycle is performed by using a timing delayed by an integer number of clocks of the clock generating means from the display timing indicating the effective display area. It is provided with a control means.

E) Operation As a result, even if the number of columns is changed, it can be dealt with by simply changing the screen memory capacity and the oscillation frequency of the clock generation means, and the transfer rate to the liquid crystal display side can be slowed, resulting in excellent image quality. ing.

F) Embodiment FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention.
FIG. 2 is a timing chart of the main part thereof.

In FIG. 1, (1) is a twisted nematic liquid crystal display, the electrodes of which are arranged in a matrix, and the screen (or electrode group) is divided into two parts that can be independently driven, and each has 256 x 256 dots. (512 x 256 dots on the entire screen)
Have pixels. (2) is a driver for the liquid crystal display (1), which consists of Hitachi HD44100H, etc. for the upper screen,
Receive the image signal that is serially transferred independently for the lower screen,
Timing, applying bias, liquid crystal display (1)
To drive.

(3) (3) is a screen memory that can store one screen of pixel information corresponding to dots of the liquid crystal display (1).
It consists of two 92-byte (65536-bit) statically driven random access memories (equivalent to 131072 bits). For simplification of description, the data per dot is 1 bit (white or black binarization information) as an example, but the data is not limited to this. (4) and (5) are the first and second address counters, both of which are selectors (6
a) (6b) (eg multiplexer integrated circuit, product number 7)
The screen memory (3) (3) is addressed via the 4HC244 or the like. The first address counter (4) ignores the output stepped by one address through the selector (6a) at the time of writing and ignores the lower 1 bit at the time of reading the upper screen to select the selectors (6b) and (6a). Through the output, a stepwise output at a speed half that of the step at the time of writing is output. The address designation of the first and second address counters (4) and (5) will be described later. (7) and (7) are presetting means for giving the start address to the first and second address counters (4) and (5). Now screen memory (3) (3) address
Hexadecimal number display (The display corresponding to the decimal number is 0,1-9, 0,1
~ 9 and 10 to 15 are A to F), and if the addresses are 0000 to 1FFF (for the upper screen) and 2000 to 3FFF (for the lower screen), the preset means (7) and (7) are 0000 respectively. 2000 is set or stored.

Although (8) is an image processing circuit that serially outputs a video signal including a tuner, an intermediate frequency amplifier, etc., it may be configured only with a buffer or the like for receiving a video signal from a video, a personal computer, a magnetic image file device or the like. Good.
(9) is a timing means for receiving an image control signal from the image processing circuit (8) and generating a basic timing signal and a control signal for allowing the entire apparatus to work smoothly.
A clock generating means (10) is provided. The clock (CL) which is the output of the clock generating means (10) is for alternately writing and reading the screen memories (3) and (3) within one clock as described later. The image control signal that the timing means (9) receives from the image processing circuit (8) is a display indicating an effective display area of the vertical blanking signal (V), the horizontal blanking signal (H), and the pixel information sequentially sent. It is a display signal (D) that gives timing. The timing means (9) outputs an initial signal (IS) by the display signal (D) after the vertical retrace signal (V), and synchronizes the clock edge of the clock generation means (10) with the display signal (D).
A first timing signal (D ₁ ) delayed by 1 clock from the display signal (D) and a second timing signal (D ₂ ) delayed by 3 clocks from the display signal (D) are output.

(11a) and (11b) are the first and second timing signals (D ₁ )
The gate means (11a) receives the (D ₂ ) and outputs a control signal according to the clock (CL), and the gate means (11a) is of the write mode (W) and the read mode (R) of the screen memories (3) and (3). It outputs a mode signal (R / W) for designating a memory mode and a step-up signal (CA ₁ ) (CA ₂ ) at the count-up timing of the first and second address counters (4) and (5) ( Reference numerals 12a) and (12b) are gates made up of toggle flip-flops and the like which are appropriately provided to obtain the half frequency. On the other hand, the gate means (11b) is an image memory (3).
The transfer timing (CT) for transferring the video signal read from (3) to the driver (2) of the liquid crystal display (1) is output. Reference numeral (13) is a converter for converting the video signal serially transferred from the image processing circuit (8) into serial-parallel conversion of 8 bits, and has a synchronous Schmitt buffer at the input stage and is binary for analog signals. It has the ability to convert, and is given a timing signal for serial-parallel conversion by the gate (14). (15) and (15) are inverse converters that serial-convert the parallel-converted video signals, and (16) and (17) are latch circuits for timing the video signals. Here, selectors (6a) (6b), gate means (11a) (11b), gates (12a) (12b), inverse converters (15) (15), latch circuits (16) (17) are screen memories ( 3) Constituting control means (18) for controlling the write / read operation of (3), among which the gate means (11b) and the inverse converters (15) (15) read from the screen memory (3) (3). LCD control means (1
9).

The operation of the above configuration will be described with reference to FIG. First, the image processing circuit (8) receives a vertical blanking signal (V) and a horizontal blanking signal (H) from a received radio wave or a transmitted video signal, and a display signal (D) indicating a range including effective pixel information. ) Is output to the timing means (9) and an analog video signal is output to the converter (13) while the display signal (D) is present. This video signal is binarized in the converter (13) and converted into a parallel signal of 8 bits each in synchronization with the timing of the gate (14), stored in the latch circuit (16), and stored in the mode signal (R / W) write timing. Further, the timing means (9) outputs the initial signal (IS) by the display signal (D) after the vertical retrace signal (V), whereby the first and second address counters (4) and (5) are preset means. (7) Take in the contents of (7).

In the screen memories (3) and (3), the memory mode of the write mode (W) and the read mode (R) is designated by the level of the mode signal (R / W).
The memory mode is alternately switched by the clock (CL) of 0), which is the timing means (9) and the gate means (11).
1st delayed by 1 clock from the display signal (D) by a)
It is started by the timing signal (D ₁ ). This one
The clock is delayed because the converter (13) can finish the conversion process in the meantime, which is a feature of the present invention.
This is to make the cycle of upper screen read-write-lower screen read smooth and not to be influenced by the number of pixels in the column direction.

That is, in the present application, when the writing for one screen is finished, the reading for one screen is also finished (described later). However, the number of dots of pixel information to be taken out within one horizontal scan depends on how many clocks (CL) described above. This corresponds to the one-to-one correspondence with the pulse sent. Therefore, assuming that the pulse width of the horizontal blanking signal (H) is 64 μsec and the pulse width of the display signal (D) is 40 μsec, if there are n dots in the horizontal direction (n = 256 in this example), a clock of (40 / n) μsec ( CL) may be used.

With such a clock (CL), the addresses of the screen memories (3) and (3) to be written or read are selectively given by the first and second address counters (4) and (5). The first address counter (4) is stepped up by the gate means (11a) every read mode (R), and the output is guided through the selector (6a) in the write mode (W), so that the designated address is Starting with the address "0000", one address is incremented each time in the writing mode (W). The data is output through the selectors (6b) and (6a) every other time in the read mode (W), but the least significant bit is ignored, so that the read address is advanced at half the speed of the write / read mode. On the other hand, the second address counter (5) is provided with gate means (11
a), the gate (12b) steps into the write mode (W) at a half cycle of the write mode (W), and the read mode (R)
Every other time, the output is guided to the screen memory (3) through the selectors (6b) and (6a).

Taking the first frame as an example, the first address counter (4) has “0000” and the second address counter (5) has “20”.
After 00 "is stored, the first timing signal (D ₁₎ by the mode signal (R / W) is started out, write mode (mode signal" H ") at the first timing (t ₁₎ is designated It As a result, the video signal is sent from the latch circuit (16) to the image memories (3) and (3), and the address designation at this time is the address "0000" by the first address counter (4). Clock (CL) at the next timing (t ₂ ).
Becomes the read mode (mode signal “L”), and “000
The contents of the address "0" are read and stored in the latch circuit (17). At the next timing (t ₃ ), the write mode (W) is set again, but since the first address counter (4) is stepping forward, the video signal is displayed in the screen memory (3) (3). It is stored in the address "0001".

At the fourth timing (t ₄ ), since the output of the second address cow (5) is guided to the screen memories (3) and (3) in the read mode (R) via the selectors (6b) and (6a). The address "2000" is designated. (Immediately after the power is turned on, no video signal is stored in this address,
The image in front of the screen is stored. ) The contents of the address "2000" are sent to the inverse converter (15), but since the second timing signal (D ₂ ) causes the gate means (11b) to start operating, the inverse converter (15) is It suffices to perform parallel-serial conversion and then complete the transfer before the trigger signal is applied to the converter (15). Therefore, the mode signal (R / W) 2
A transfer timing signal (CT) of double frequency is given.
At this time, if the latch circuit (17) also allows output at the same time, "00
The contents of the address "00" and the contents of the address "2000" are simultaneously converted into a serial signal and transferred to the driver (2).

In the same manner, writing and reading are alternately performed, but writing is sequentially performed one by one starting from the address "0000", and reading is started from the address "0000" and the upper screen pixel information and "2000". The lower screen pixel information starting from the address is alternately read, and the transfer to the driver (2) is performed simultaneously with the upper and lower screens when the lower screen pixel information is read, but independently.

Therefore, the writing of the 1st screen is completed (the last address is 3FFF address)
The video signal of the upper screen (address is 1F
FF) is read, and the video signal (address is 3FFF) of the lower screen is read at the timing immediately after. That is, the writing time and the reading time for one screen become equal, and in reading, the video signal of the screen currently being written is read for the upper screen, and the video signal of the previous screen is read for the lower screen. Become.

As a result, the image signal input to the driver (2) is half the writing speed to the screen memories (3) and (3) (that is, the serial clock frequency of the converter (13) = the inverse converter (15). )
(15) serial clock frequency x 2) and the continuity of the video signal is maintained on the upper and lower screens (since the video signal is serial data, the latter half of the (n-1) th screen and the nth screen).
Since the first half of the screen is continuous), in the display of the n-th screen, at the i-th row timing, the n-th screen data is on the upper i-th row and the n-1th screen data is on the lower i-th row. Although the nth screen data is displayed on the upper screen and the n-1th screen data is displayed on the lower screen, the display of the previous lower screen data and the next upper screen data is data within a very short continuous time. Further, practically, when the last line of the upper screen is displayed, the last line of the lower screen is displayed, and at the timing of the next line, the first line of the lower screen is displayed as the nth screen data. Therefore, the viewer does not feel discomfort as if the display is distorted.

In the above description, if the converter (14) includes an AD converter, the image of 2 bits (4 gradations), 4 bits (8 gradations), 8 bits (16 gradations), etc. per pixel As information, gradation display can be performed by the same procedure. Further, color signals can be used instead of gradations, or color display can be performed by having a screen memory for three screens corresponding to the color signals and following the same procedure for each color.

The display signal (D) as the display timing indicating the effective display area of the pixel information is formed after counting the horizontal retrace signal (H) to be invalidated based on the vertical retrace signal (V). However, it is easy to use a blanking signal, and a device such as a personal computer that directly outputs digitally processed pixel information outputs a display timing signal in the same manner. Good. However, the blanking signal and the display timing signal often have a timing shift, and the original center of the image often does not coincide with the center of the screen of the liquid crystal display (1). In this case, in the present invention, the display signal (D) is used as the reference of the memory and the transfer timing, so that the display signal (D) may be shifted. FIG. 3 is a block diagram of an essential part at that time, and an image processing circuit (8).
A counter (20) for generating a delay signal is connected in series to the display signal line between the display means (9) and the timing means (9), and the display signal (D) has an output delayed by j clocks from the blanking signal (B) (or the display timing signal). ')And it is sufficient. This j is practically useful between 0 and 8.

G) Effect of the Invention As described above, the present invention has two upper and lower sides from the viewpoint of the display signal.
When the divided dot matrix display is driven by using a screen memory having a storage capacity equal to the number of pixels, one cycle is used for writing, upper screen reading, writing,
Since the lower screen reading is performed and the timing of using the memory is based on the timing signal delayed by the write / read clock from the display timing indicating the effective display area, neither the capacity of the screen memory nor its peripheral circuits It is relatively small, and the display information can be transferred at a speed half the writing speed of the memory, so that images do not flicker, and the density of the screen in the horizontal direction can be immediately dealt with, thus providing versatility.

[Brief description of drawings]

FIG. 1 is a block diagram of an image display device according to an embodiment of the present invention, FIG. 2 is a timing chart of the main part thereof, and FIG. 3 is a block diagram of the main part of another embodiment of the present invention. (1) …… Liquid crystal display, (2) …… Driver, (3)
(3) ... screen memory, (4) (5) ... address counter, (6a) (6b) ... selector, (7) (7) ... presetting means, (8) ... image processing circuit, ( 9) ... timing means, (10) ... clock generating means, (11a)
(11b) …… Gate means, (12a) (12b) …… Gate,
(13) …… Transducer, (14) …… Gate, (15) (15)…
Inverse converter, (16) (17) …… Latch circuit, (18) ……
Control means, (19) ... Liquid crystal control means.

Claims (2)

[Claims] 1. A liquid crystal display consisting of a vertically divided dot matrix, a screen memory capable of storing pixel information corresponding to dots of the liquid crystal display for one screen, and writing and reading of the screen memory alternated. The clock generation means for performing the above, the timing means for generating the timing delayed by the integer number of clocks of the clock generation means from the display timing showing the effective display area of the pixel information sent sequentially, and the timing delayed from the display timing. An image display device comprising: a control unit for controlling a writing / reading operation of a screen memory. 2. The timing means generates a first timing signal delayed by an integer number of clocks from a display timing and a second timing signal delayed by an integer number of clocks from the first timing signal, and the control means. Further comprises a liquid crystal control means for controlling the writing / reading operation of the screen memory by the first timing signal and further transferring the pixel information read from the screen memory by the second timing signal to the liquid crystal display side. The image display device according to claim 1, wherein the image display device is characterized in that.