JP2548018B2 - Double speed converter - Google Patents

Description

TECHNICAL FIELD The present invention relates to a double speed conversion device for realizing non-interlaced scanning in television display.

[Outline of Invention]

Recently, new media and devices such as sanitary broadcasts, teletexts, video discs, and large-scale television devices have become widespread, and attempts are being made to improve the quality of television images in order to take advantage of the features of these media. As a means for improving the image quality of an image, an attempt has been made to reduce interference such as flicker by performing non-interlaced scanning using a field memory or a line memory.

The present invention, in a double speed conversion device for realizing non-interlaced scanning using a memory, is a single field for inputting and outputting data by a first-in first-out (“FIFO”) method. By using the memory and one line memory, the data is read out within the one horizontal scanning period by first reading the data in the field memory, thereby realizing the double speed conversion device required for non-interlaced scanning with a simple memory configuration. Is.

[Conventional technology]

As shown in FIG. 6, the conventional double-speed conversion device switches the input and output of two field memories alternately for each field, and performs data reading at a speed twice as fast as the writing speed to perform non-interlaced scanning. Had been realized.

Also, by using three field memories, the data is alternately read from the other two field memories at a double speed at the time of writing the data in one field memory,
It realized non-interlaced scanning.

[Problems to be solved by the invention]

However, in the above-described conventional technology, the memory cost is high because the memory capacity is large, and it is necessary to separately provide an address generation circuit and an input / output switching circuit using a dynamic RAM for the memory configuration. However, there is a problem that the burden is heavy.

Therefore, the present invention solves such a problem,
An object of the invention is to provide a double speed conversion device required for non-interlaced scanning with a simple memory structure. Another object of the present invention is to provide a device capable of reducing interference such as flicker by performing non-interlaced scanning using a field memory or a line memory as a means for improving the image quality of an image.

[Means for solving problems]

The double speed conversion device of the present invention is the i-th (i = 1, 2, 3, ...) Dividing the j-th (j = 1, 2, 3, ...) Period TF (j). Data DH (i, j) is sequentially input at the first frequency during the period TH (i, j) of the above, and is output at the second frequency that is twice the first frequency to be converted into double speed data. In the double speed conversion device, a predetermined number of the data DH (i,
j) is written at the first frequency and is read at the second frequency, and the data DH (i, j) is stored in the first storage means during the period TH (i, j).
Write at the second frequency and read at the second frequency
And the data D in each period TH (i, j) of the period TF (j).
H (i, j-1) is read from the predetermined address of the first storage means at the second frequency in synchronization with the start of the period TH (i, j), and the data DH (i, j) is read. Writing to the predetermined address of the first storage means at the first frequency, and the data DH (i, j) during the period TH (i, j)
In synchronization with the start of TH (i, j), the data is written in the second storage means at the first frequency, and a predetermined number of the data DH (i, j) are written.
After the reading of (j-1) from the first storage means is completed, the data DH (i, j) in the second storage means is read during the period T.
Means for reading at the second frequency by the time H (i, j) ends, and read data DH (i, j− from the first storage means
1) and read data DH (i, i from the second storage means
and j) are alternately output within the period TH (i, j) to perform conversion into the double speed data.

Also, the double speed conversion device of the present invention inputs video data of frequency φHz, and outputs the video data
In a double speed conversion device for converting double speed video data having a frequency of 2φHz, the data for one field of the video data is converted to the φHz.
A field memory for writing at the frequency of 2φHz and data for one horizontal scanning period of the video data
A line memory for writing at a frequency of 2φHz for writing at a frequency of Hz, and a reading of data for one horizontal scanning period at a frequency of 2φHz from the field memory in synchronization with a horizontal synchronizing signal, and the start of the reading. Writing the video data to the field memory at the φHz in synchronization with the timing of writing the video data to the line memory at the φHz in synchronization with the start of writing the video data to the field memory. Means for starting and reading the data for the one horizontal scanning period from the field memory and ending the reading at the 2φHz from the line memory, and ending the reading by the end of the horizontal scanning period. , Read data from the field memory and read data from the line memory Are alternately output to perform conversion into the double-speed video data.

[Action]

The principle of the double speed conversion device of the present invention will be described with reference to FIG.

As shown in the figure, the j-th (j = 1, 2, 3, ...
.) Period TF (j) is divided into i-th (i = 1,
Data DH (i, j) is sequentially input at the first frequency during the period TH (i, j) of 2, 3, ... Then, the first storage means, during the period TF (j), the number of data DH (i,
j) has a writable storage capacity and is the first to write
At a frequency of 2, the reading is done at a second frequency.
The second storage means stores data DH (i, j) in the period TH (i, j),
That is, it has a capacity for storing one piece of data and performs writing at the first frequency and reading at the second frequency.

In the period TF (j), the immediately preceding period TF (i-1)
Data DH already written in the first storage means
(I, j-1) is read from a predetermined address at the second frequency in synchronization with the start of the period TH (i, j), and the current data DH (i, j) is read at the first frequency. Write to the predetermined address of the first storage means. Also, during this period TH (i, j), the data DH (i, j) is written in the second storage means at the first frequency in synchronization with the start of the period TH (i, j), and the previous one is written. A predetermined number of data DH (i, j−
After the reading of 1) from the first storage means is completed, the data DH (i, j) of the second storage means is read during the period TH.
Reading is performed at the second frequency until (i, j) is completed.

That is, in the period TH (i, j), the data DH of TH (i, j-1) in the immediately preceding period TF (j-1) is approximately in the first half of the period.
(I, j-1) is read from the first storage means at a double speed, and in the latter half of the period, the data DH (i, j) of TH (i, j) of the current period TF (j) is transferred to the second period. Since the data is read from the storage means at double speed, these data can be alternately output within the period TH (i, j) to perform conversion into the double speed data.

This will be described with a more specific example. Period TF is 1
The field period and the period TH are one horizontal scanning period, and the first storage means and the second storage means are a field memory and a line memory, respectively. Then, the operation of the circuit according to the present invention is as follows: (a) All the data of the first field is written from the head address of the field memory (1).

(B) The data of the second field is written from the head addresses of the field memory (1) and the line memory (2), but the data is read at the same speed at double speed.

(C) That is, in one horizontal scanning period, the same data is written in the field memory (1) and the line memory (2), but (d) the data in the first field of the field memory (1) is , At the same time that the data of the second field is written, the reading is started at a speed which is slightly faster than the writing of the second field, and the reading is finished at a time of about 1/2 of one horizontal scanning period (a period of about the first half of one horizontal scanning). (E) The data of the line memory (2) starts to be read after the reading of the field memory (1) is finished and before the end of one horizontal scanning period (that is, a period of the latter half of one horizontal scanning period).
The reading ends.

Since the above operation is repeated, the field memory (1)
In (1), the data in the second field is written after reading the data in the first field, and in the line memory (2), the written data in the second field is read in the latter half of one horizontal scanning period.

Therefore, I / O of data is performed by FIFO1
With the simple memory configuration of only one field memory (1) and one line memory (2), a double speed conversion device can be realized, and non-interlaced scanning using video data of the previous field as interpolation data becomes possible. .

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a double speed conversion device. The double-speed conversion device of the present invention comprises one field memory (1) and one line memory (2), input data (3) is written by a write clock φ (5) of frequency φHz, and output data ( 4) is output by the read clock 2φ (6) of 2φHz which is twice the frequency of φ.

Other control signals include an input address reset signal RSTWA (8) that sets the address counter inside the field memory at the start address, and an output address reset signal RSTRA.
(12), Input address reset signal RSTWB (9) that sets the address counter inside the line memory to the first address,
Output address reset signal RSTWB (13), write signal WE (7) that controls writing, read signal REA (10) that controls reading of field memory, read signal REB (11) that controls reading of line memory, and output There is a selection signal SEL (14).

Since the writing to the memory is always performed, the writing signal WE (7) is always in the active state. If the memory output has a 3-state structure, the output selection signal SEL (1
4) can be omitted.

FIG. 2 is an internal configuration diagram of the field memory IC. The field memory (1) and the line memory (2) have the same internal configuration, but the capacity of the memory array (16) is different. That is, it is sufficient for the line memory (2) to have a memory capacity capable of storing data for one line, that is, data for one horizontal scanning period. On the other hand, in the field memory (1), one field (for example, when handling an NTSC signal, 26
2.5 lines), that is, the capacity for one vertical scanning period or more is required, and the memory capacity is 263 times or more that of the line memory (2).

Each data is φHz from memory address 0
It is written by the write clock φ (5).

Data is read out in the field memory (1) at a speed of 2φHz at the same time as or immediately before the writing of data in one horizontal scanning period of the current field is started, and as a result, in the first half of one horizontal scanning period. When the data writing is completed, the data reading for one horizontal scanning period (one line) of the previous field is completed. Simultaneously with or immediately before the writing of data in the next horizontal scanning period, data reading for the next horizontal scanning period of the next line is started, and the same operation is repeated for the number of horizontal scanning lines. That is, the operation of reading the data in the horizontal scanning period one field before the writing of the data in the horizontal scanning period of the current field is repeated.

In the line memory, after the writing of data in one horizontal scanning period is started, the reading is started when the writing of half the data in one horizontal scanning period is finished, and the writing of data in one horizontal scanning period is finished at the same time. The reading ends with a slight delay.

In this way, the data of one horizontal scanning period before one field is read from the field memory (1) at a speed of 2φHz, and the data of one horizontal scanning period of the current field of 2φHz is read from the line memory (2). Since the data is read at a speed, the data of one field before is read in the first half of one horizontal scanning period, and the data of the current field is read at a double speed in the second half. Therefore, the data of the first field and the data of the second field are alternately read within the time of one horizontal scanning period, and the double speed conversion device is configured.

Returning to FIG. 2, the input data (3) in FIG. 2 is temporarily stored in the input register (15),
The output data (4) is stored at the address indicated by the input address counter (18), and the data of the address indicated by the output address counter (19) is stored in the output register (17) and output.

The input address counter (18) is set at address 0 by the input address reset signal RSTWA (8), and counts up by 1 address in synchronization with the write clock φ (5) of φHz to specify the write address. Similarly, the output address counter (19) also outputs the output address reset signal RSTRA (1
The address is set to 0 by 2), and the read address is specified by counting up by 1 address in synchronization with the 2φ Hz read clock 2φ (6).

The read signal REA (10) can control the operation of the output address counter (19). That is, if this signal is active, the output address counter (19) operates and data is output.

FIG. 3 is a timing chart of writing to the field memory in the vertical period. Input address reset signal RS
TWA (8) occurs in synchronization with the vertical blanking period (20) of the input data (3). Since the write signal WE (7) is always active, the operation of storing all the data of one field in the field memory (1) and then storing all the data of the next field is repeated.

FIG. 4 is a timing chart of the memory in the horizontal scanning period. If the first field data (22) is already written in the field memory (1), the second field data (23) rewrites the data in the field memory (1) and the horizontal synchronization signal (21 ), The writing is started from the head address of the line memory (2) by the input address reset signal RSTWB (9).

At this time, in the first field data (22) written in the field memory (1), the output address reset signal RSTRA (12) is the input address reset signal RSTWA.
It occurs in synchronization with the vertical blanking period (20) as in (8). When the read signal REA (10) becomes active, it is read at the double speed of the write clock φ (5), and one horizontal scan is performed. First field data in half the period (22)
The data for one horizontal scanning period is read out.

In addition, the second field data (23) written in the line memory (2) has the output address reset signal RSTRB (13) and the read signal REB after the data reading for one horizontal scanning period of the field memory (1) is completed. By (11), data is read from the start address at double speed. As a result, as the output data (4), the first field data (22) and the second field data (23) are alternately output at double speed, and the double speed conversion output required for non-interlaced scanning is obtained.

Regarding the reading order of the data of the field memory (1) and the line memory (2), the data of the field memory (1) must be read first. That is, the data for one specific horizontal scanning period of the first field data (22) one field before is read out first, and then the data for one horizontal scanning period of the second field data (23) of the current field. By reading out, the double speed conversion output necessary for non-interlaced scanning can be obtained.

FIG. 5 is a block diagram of a liquid crystal television, which is an example in which the double speed conversion device is used more specifically.

Even in liquid crystal televisions, non-interlaced driving is necessary to obtain high-definition display. This is because interlaced driving causes problems such as flicker being noticeable and a transmissive liquid crystal panel having a dark screen.

The video input signal (24) is processed by the video signal processing circuit (25) and then converted into a digital amount by the A / D conversion circuit (26) and enters the double speed conversion circuit. The output of the double speed conversion circuit is
The analog amount is converted by the D / A conversion circuit (27), converted into a form capable of driving the liquid crystal panel (31) by the video control circuit (28), and supplied to the display unit (30). Display unit (3
Reference numeral 0) includes a liquid crystal panel (31), a Y side driver (33) for selecting a row to be displayed on the liquid crystal panel (31), and an X side driver (32) for controlling display data. The control signal generation circuit (29) generates a control signal required by the display unit (30) and the double speed conversion device.

〔The invention's effect〕

As described above, according to the present invention, a double-speed conversion device required for non-interlaced scanning can be realized with a simple memory configuration having only one field memory and one line memory for inputting / outputting data by a FIFO. .

Since the configuration is simple, the load on the circuit is small, the circuit scale can be reduced, and the cost can be realized.
Moreover, non-interlaced scanning is performed using a field memory or a line memory as a means for improving the image quality of an image, and interference such as flicker can be reduced with a simple device.

[Brief description of drawings]

FIG. 1 is a block diagram of a double speed conversion device. Figure 2 shows the internal structure of the field memory IC. FIG. 3 is a timing chart of writing to the field memory in the vertical scanning period. FIG. 4 is a timing chart of the memory in the horizontal scanning period. Figure 5 is a block diagram of a liquid crystal television. FIG. 6 is a diagram of a conventional example. FIG. 7 is a principle diagram of the present invention. 1 …… Field memory 2 …… Line memory 20 …… Vertical blanking period

Claims (2)

(57) [Claims] 1. A j-th period (j = 1, 2, 3, ...)
The i-th (i = 1, 2, 3, ...) Dividing the inside of TF (j)
..) Data DH (i, j) is sequentially input in the period TH (i, j) at the first frequency, and is output at the second frequency that is twice the first frequency to double the speed. In the double speed conversion device for converting into data, a predetermined number of the data DH (i, j) in the period TF (j).
Is written at the first frequency and is read at the second frequency, and the data DH (i, j) is written at the first frequency in the period TH (i, j). Second storage means for reading at a second frequency, and the data DH in each period TH (i, j) of the period TF (j).
(I, j-1) is read from the predetermined address of the first storage means at the second frequency in synchronization with the start of the period TH (i, j) and the data DH (i, j) is read. Write at the predetermined address of the first storage means at a first frequency, and in the period TH (i, j), the data DH (i, j)
The second frequency at the first frequency is synchronized with the start of (i, j).
Of the data (DH (i,
After the reading of (j-1) from the first storage means is completed, the data DH (i, j) in the second storage means is read during the period T.
Means for reading at the second frequency by the time H (i, j) ends, and read data DH (i, j− from the first storage means
1) and read data DH (i, i from the second storage means
j) is alternately output during the period TH (i, j) to perform conversion into the double speed data. 2. A double speed conversion device for inputting video data of frequency φHz and converting the video data into double speed video data of double frequency 2φHz, wherein data of one field of the video data is converted into frequency of φHz. A field memory for writing and reading at a frequency of 2φHz, and data for one horizontal scanning period of the video data are stored in the φHz.
A line memory for writing at the frequency of 2φHz and a data reading for one horizontal scanning period at the frequency of 2φHz from the field memory in synchronization with a horizontal synchronizing signal. The writing of the video data to the field memory at the φHz is started in synchronization with the timing, and the writing of the video data to the line memory at the φHz is started in synchronization with the start of the writing of the video data to the field memory. And a means for starting reading from the line memory at the 2φHz after reading the data for the one horizontal scanning period from the field memory and ending the reading by the end of the horizontal scanning period, Read data from the field memory and read data from the line memory DOO rate conversion device characterized by forming the conversion is output alternately to the speed video data.