JPH03207177A - Reduced picture display device - Google Patents

Abstract

PURPOSE:To prevent reading operation from outpacing writing operation even when the read speed is faster than the write speed and to prevent a picture from deviating even if a body in motion is reduced and displayed by writing data with delay behind the reading operation. CONSTITUTION:A writing means which starts writing data at the write speed slower than the read speed is provided for a memory which is being read between 1st and 2nd memories 10 and 12. Therefore, even if the read speed is slower than the read speed, the writing operation is never outpaced by the reading operation. Further, the 2nd memory 12 is read after the 1st memory 10 is read, so if a video signal of a 2nd field is stored in the 1st memory 10 and a video signal of a 1st field is stored in the 2nd memory 12, the upper-lower correlation between the 1st and 2nd fields is lost. For the purpose, scanning lines in the 2nd field stored in the 1st memory are shifted by as many as thinned-out scanning lines to maintain the correlation between the 1st and 2nd fields.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for displaying images on a reduced screen on a television monitor. [Prior art] For example, as shown in FIG.
When displaying the screen 4 that has been reduced to F1-1, Fl-3. The image signal of the scanning line of the second field shown by the dotted line in FIG. 6 is stored in the memory 6 every other tree as shown by Fl-5...F2-5 in FIG. 7(b). 1, F2-3, and F2-5, every other line is stored in the memory 8, first each stored value in the memory 6 is sequentially read out, and then each stored value in the memory 8 is sequentially read out. 7 Display the reduced screen as shown in Figure (c). Note that the video signals are stored in each of the memories 6 and 8 after being sampled and A/D converted, and the sampling interval is twice the interval at which the video signals are sampled. [Problem to be Solved by the Invention IIF However, when the screen is reduced in this way, reading from each memory 6 and 8 is performed at the same speed as the normal screen scanning speed, whereas writing is performed at the same speed as the normal screen scanning speed. Because every other scanning line is stored in memory, the reading speed is twice as slow as the reading speed. Therefore, even if the start of reading is later than the start of writing, reading will overtake writing, and the image of the field written one field before the currently written field will be read from the middle. This is especially a problem for moving images. That is, for example, in FIG.
) When the moving object is moving from right to left as shown in Figure (b), when reading overtakes writing at the position shown by the virtual line in Figure (b), the screen below the temporary line is currently being written. Since this field is written one field before the other field, a shift occurs in the image with the virtual line as the boundary.

The object of this invention is to provide a reduced screen display device that solves the above problems. [A Thousand Steps to Solve the Problem] In order to achieve the above object, the present invention scans a predetermined number of video signals of one of the first and second fields among the video signals subjected to interlaced scanning. a first memory that sequentially stores the video signals of the scanning lines spread out by the predetermined number of the other video signals of the first and second fields; After sequentially reading out the stored values of the first memory at a predetermined reading speed, the second memory
reading means for repeatedly reading the stored values of the memories in sequence at the reading speed; and writing to the memory from which the reading is being performed at a writing speed slower than the reading speed of the first and second memories. and a writing means for starting.

Also, when the second field is stored in the first memory,
It is desirable to provide means for shifting the first scanning line of the second field stored in the first memory backward by the predetermined number of lines. [Operation] According to the present invention, writing to the first and second memories is performed as follows.
Each is started after reading starts, so even if the reading speed is faster than the writing speed, the writing will not be overtaken by the reading. Also, after reading the first memory, li! Since the memory of f2 is being read, if w
If the video signal of the second field is stored in the 4l memory and the video signal of the first field is stored in the second memory, the vertical correlation between the first and second fields will collapse when read. Therefore,! ! J! The scanning lines of the second field stored in the memory are shifted by the number of lines that are scattered, thereby compensating the correlation between the first and second fields.

[Embodiment] In this embodiment, a reduced screen 4 is displayed on the upper left of the monitor screen 2 in a CCTV, as shown in FIG. Therefore, as shown in the first [N], memories 10 and 12 are provided. When the read memory selection signal 16 generated by the timing generation circuit 14 is at a low level as shown in FIG. 2, the memory 10 selects each stored field according to the read address signal 17 generated by the timing generation circuit 14. sequentially read out the video signals. In addition, the memory 12
When the read memory selection signal 16 is at a high level as shown in FIG. 2, the video signals of the stored fields are sequentially read out according to the read address signal. The timing generation circuit 14 generates a read memory selection signal 16 and a read address signal 17 based on a vertical synchronization signal, a horizontal synchronization signal, etc. from the read synchronization signal generation circuit 15. Each memory 10, 12 consists of rows and columns, and each column of each row has l
It samples the video signal on the scanning line and stores the digitized version. Therefore, the read address signal 17 includes a vertical address signal specifying a row or scan line;
ie, a horizontal address signal that specifies each sampling point on the corresponding scanning line.

Further, writing to the memory 10 is performed when the write memory selection signal I8 is at a low level, and writing to the memory 12 is performed when the write selection signal 18 is at a high level.
The write selection signal 18 becomes low level after a predetermined period of time has elapsed since the read selection signal 16 became low level, and similarly, the write selection signal 18 becomes high level when the read selection signal 16 becomes low level. This is after a predetermined period of time has elapsed since the signal l6 became high level. The write address includes a horizontal address signal a from the address counter 20 that counts the write control master clock signal, and a vertical address signal a from the address counter 24 that counts the horizontal synchronization signal separated by the synchronization separation circuit 22 from the video signal from the imaging device. address signal b. The address counter 20 is reset each time a horizontal synchronization signal is supplied from the synchronization separation circuit 22, and the address counter 24 is reset each time a vertical synchronization signal is input from the synchronization separation circuit 22. +4+NowΦMomo 447 The dress counter 20 is actually reset by inputting the horizontal synchronization signal from the synchronization separation circuit 22 to its load terminal. That is, since no preset data is given to the address counter 20, even if a signal is supplied to the load terminal, the preset data becomes O and is reset. The reset of the atre counter 24 is also performed by supplying a vertical synchronization signal from the synchronization separation circuit 22 to its load terminal. That is, when a vertical synchronizing signal is supplied to the load terminal, if the data selector 36 (described later) does not provide preset data, the preset data is
and will be reset. A vertical address signal from the address counter 24 designates a scanning line, and in order to designate every other scanning line, a count value excluding the least significant bit of the counter 24 is supplied as a vertical address signal. That is, as soon as the horizontal synchronizing signal is supplied, the address counter 24 outputs "0...
・000", "O...001J, "O...Ol
"O", "O...OIIJ", "O...100",
It changes like "O...l01", but if you remove the least significant bit, "O...OOJ (decimal 0)", "0...OOJ (decimal 0 ), “0...
...OIJ (decimal number 1), "0...OIJ (1
decimal number l), “0...IOJ (decimal number 2),
"0...IOJ (decimal number 2). Therefore, the scanning lines l, 3... It is also supplied as an A/D conversion command signal to the A/D converter 26 that performs A/D conversion for storage. As described above, the vertical address signal of the read address signal is the vertical address of the write address signal. 2 than the traffic light
Although it is twice as fast, since the write selection signal 18 lags behind the read memory selection signal l6, the writing will not be overtaken by the reading. As this write selection signal 18, a delay signal 28 generated by the timing generation circuit 14 by delaying the read memory selection signal 16 by a predetermined time is supplied to the input terminal of the D-type flip-flop 30, and is synchronized with the clock input terminal of this. By inputting the vertical synchronization signal from the separation circuit 22, the delay signal 28 is synchronized with the vertical synchronization signal from the synchronization separation circuit 22. By the way, as shown in FIG. 3(a), there is a second memory in the memory 10.
First scanning line F2-1 and third scanning line F2-3 of the field
, fifth scanning line F2-5... are stored, and as shown in FIG.
), the first field of the first field is stored in the second memory 12.
Scanning line Fl-1, third scanning line Fl-3, fifth scanning line F1
-5... may be stored. In such a case, the first memory 10 is read as it is, and then the second
When read from the memory 12, it is displayed as shown in FIG. 3(c), and as is clear from the comparison between this and FIG. 7(c), the correlation between the first field and the second field,
In other words, the vertical relationship of the scanning lines is disrupted. Therefore, when storing the video signal of the second field in the memory 10, the second scanning line F2-2 and the fourth scanning line F2 of the second field are shifted one by one as shown in FIG. 4(a). -4,
The sixth scanning line F2-6... is stored. If this is done, the correlation between the upper and lower scanning lines will not collapse, as shown in FIG.

In order to do this, field determination is performed to determine whether the video signal from the imaging device is currently in the first field or the second field based on the horizontal synchronization signal and vertical synchronization signal from the synchronization separation circuit 22. A circuit 32 is provided. This determination circuit 32 generates a high level output signal in the case of the first field, and generates a low level output signal in the case of the second field. This output signal is supplied to an AND circuit 34, and the memory selection signal 18 is also supplied to this AND circuit 34. Since the memory selection signal is at a high level when writing to the memory 10 as described above, when writing the second field to the memory 10,
The output of the AND circuit 34 becomes high level. The output of the AND circuit 34 is supplied to a data selector 36, and the data selector 36 supplies l as reset data to the address counter 24 when the output of the AND circuit 36 is at a high level. This preset data is loaded when the vertical synchronization signal is supplied from the synchronization separation circuit 22. Therefore, the address counter 24 starts counting from 1, and if the least significant bit is ignored, the second, fourth,
The 6th... scanning line is specified. In the above embodiment, the reduced screen is displayed at the top left of the monitor screen, but it can also be displayed at the top right, bottom left, or bottom right. Furthermore, although the screen was reduced to 1/4 in the above embodiment, it can also be reduced to any size by changing the number of diagonal scanning lines. [Effects of the Invention] As described above, according to the present invention, writing is performed later than reading, so even if the reading speed is faster than the writing speed, reading will not overtake writing. Even when a moving object is displayed in a reduced size, the screen does not shift. Furthermore, when the second field video signal is stored in the first memory (memory 10 in the embodiment), since the shifted video signal is stored, the first field stored in the second memory is The correlation between the top and bottom will not collapse.

[Brief explanation of drawings]

Figure 1 is a block diagram of an embodiment of the reduced screen display device according to the present invention, Figure 2 is a timing diagram of the embodiment, and Figure 3 is an explanatory diagram of the deviation in the vertical correlation in the embodiment. , FIG. 4 is an explanatory diagram of preventing deviations in the vertical correlation in the same embodiment, FIG. 5 is a diagram showing a reduced screen, FIG. 6 is an explanatory diagram of interlaced scanning, and FIG. 7 is a conventional reduced screen display. An explanatory diagram of the device, FIG. 8 is an explanatory diagram of the deviation in the conventional reduced screen display system. 10, 12...Memory, 14...Timing generation circuit (reading means) 20, 24...Address counter (writing means).

Claims (2)

[Claims] (1) A first memory that sequentially stores a video signal of a predetermined number of scanning lines of one of the first and second fields of the interlaced video signal; a second field for sequentially storing the video signals of the scanning lines spread by the predetermined number of the other video signals of the two fields;
a memory, a reading means for sequentially reading out the stored values of the first memory at a predetermined reading speed and then sequentially reading out the stored values of the second memory at the reading speed; and first and second memories. A reduced screen display device comprising: writing means for starting writing to the memory from which the reading is being performed at a writing speed slower than the reading speed. (2) In the reduced screen display device according to claim 1, the first
A reduced screen display device comprising means for shifting the first scanning line of the second field stored in the first memory backward by the predetermined number when the second field is stored in the memory.