JPS6468188A - Double speed conversion circuit - Google Patents

Double speed conversion circuit

Info

Publication number
JPS6468188A
JPS6468188A JP62225725A JP22572587A JPS6468188A JP S6468188 A JPS6468188 A JP S6468188A JP 62225725 A JP62225725 A JP 62225725A JP 22572587 A JP22572587 A JP 22572587A JP S6468188 A JPS6468188 A JP S6468188A
Authority
JP
Japan
Prior art keywords
data
field
memory
double speed
readout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62225725A
Other languages
Japanese (ja)
Other versions
JP2548018B2 (en
Inventor
Takeshi Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62225725A priority Critical patent/JP2548018B2/en
Publication of JPS6468188A publication Critical patent/JPS6468188A/en
Application granted granted Critical
Publication of JP2548018B2 publication Critical patent/JP2548018B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To realize a double speed conversion circuit with simple memory constitution by providing a field memory applying input/output of a data by a FIFO and a line memory and reading the data in the field memory earlier within one horizontal scanning period. CONSTITUTION:All data of the 1st field are written from the head address of the field memory 1. The data of the 2nd field is written from the head address of the field memory 1 and the frame memory 2, and the data is read at the double speed simultaneously. That is, the same data are written in the field memory 1 and the line memory 2 in a horizontal period, and the data of the 1st field of the field memory 1 is read out at the double speed simultaneously or slightly faster when the 2nd field data is written and the readout is finished in a time a half the one horizontal period, the data of the line memory 2 starts the readout after the readout of the field memory 1 is finished and the readout is finished before the end of one horizontal period. The operation above is repeated.
JP62225725A 1987-09-09 1987-09-09 Double speed converter Expired - Lifetime JP2548018B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62225725A JP2548018B2 (en) 1987-09-09 1987-09-09 Double speed converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62225725A JP2548018B2 (en) 1987-09-09 1987-09-09 Double speed converter

Publications (2)

Publication Number Publication Date
JPS6468188A true JPS6468188A (en) 1989-03-14
JP2548018B2 JP2548018B2 (en) 1996-10-30

Family

ID=16833840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62225725A Expired - Lifetime JP2548018B2 (en) 1987-09-09 1987-09-09 Double speed converter

Country Status (1)

Country Link
JP (1) JP2548018B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157180A (en) * 1987-12-14 1989-06-20 Iizeru:Kk Scan converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157180A (en) * 1987-12-14 1989-06-20 Iizeru:Kk Scan converter

Also Published As

Publication number Publication date
JP2548018B2 (en) 1996-10-30

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