JPS57127982A - Memory address system - Google Patents

Memory address system

Info

Publication number
JPS57127982A
JPS57127982A JP959581A JP959581A JPS57127982A JP S57127982 A JPS57127982 A JP S57127982A JP 959581 A JP959581 A JP 959581A JP 959581 A JP959581 A JP 959581A JP S57127982 A JPS57127982 A JP S57127982A
Authority
JP
Japan
Prior art keywords
data
address
signal
parallel
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP959581A
Other languages
Japanese (ja)
Inventor
Tomoyuki Iwami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP959581A priority Critical patent/JPS57127982A/en
Publication of JPS57127982A publication Critical patent/JPS57127982A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To achieve simultaneous output of data in parallel n-bit as data of parallel 2n-bit, by taking one memory address of two sets of parallel n-bit data as the address added with a specified value to another memory address.
CONSTITUTION: In writing two sets of data in parallel n-bit to a memory 2 with a CRT display controller 1, character data selects 4 an address signal A' adding a specified address value K to an address signal A at the 1st hold of one period of a clock CK, and also modified data selects 4 the address signal A at the latter half of one period of the signal CK respectively. and both data are written in (A+K) and A addres in time division. At readout, a signal adding 3 the specified address value to the address signal A at the 1st half of one period of the signal CK and the address signal A at the latter half of one period of the signal CK are given to a memory 2 via a selector 4 respectively and read out in time division, allowing to output two sets of data as the data in parallel 2n-bit data at the next data readout cycle.
COPYRIGHT: (C)1982,JPO&Japio
JP959581A 1981-01-27 1981-01-27 Memory address system Pending JPS57127982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP959581A JPS57127982A (en) 1981-01-27 1981-01-27 Memory address system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP959581A JPS57127982A (en) 1981-01-27 1981-01-27 Memory address system

Publications (1)

Publication Number Publication Date
JPS57127982A true JPS57127982A (en) 1982-08-09

Family

ID=11724675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP959581A Pending JPS57127982A (en) 1981-01-27 1981-01-27 Memory address system

Country Status (1)

Country Link
JP (1) JPS57127982A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117286A (en) * 1983-11-29 1985-06-24 三菱電機株式会社 Video display controller
EP0572904A2 (en) * 1992-05-29 1993-12-08 Sony Corporation Moving picture encoding apparatus and method
EP0652676A1 (en) * 1993-11-08 1995-05-10 Sony Corporation Apparatus and method for compressing a digital motion picture signal
US5461423A (en) * 1992-05-29 1995-10-24 Sony Corporation Apparatus for generating a motion vector with half-pixel precision for use in compressing a digital motion picture signal

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117286A (en) * 1983-11-29 1985-06-24 三菱電機株式会社 Video display controller
EP0572904A2 (en) * 1992-05-29 1993-12-08 Sony Corporation Moving picture encoding apparatus and method
EP0572904A3 (en) * 1992-05-29 1994-08-17 Sony Corp Moving picture encoding apparatus and method
US5408269A (en) * 1992-05-29 1995-04-18 Sony Corporation Moving picture encoding apparatus and method
US5461423A (en) * 1992-05-29 1995-10-24 Sony Corporation Apparatus for generating a motion vector with half-pixel precision for use in compressing a digital motion picture signal
EP0652676A1 (en) * 1993-11-08 1995-05-10 Sony Corporation Apparatus and method for compressing a digital motion picture signal

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