JPS57147183A - Shift register - Google Patents

Shift register

Info

Publication number
JPS57147183A
JPS57147183A JP56031468A JP3146881A JPS57147183A JP S57147183 A JPS57147183 A JP S57147183A JP 56031468 A JP56031468 A JP 56031468A JP 3146881 A JP3146881 A JP 3146881A JP S57147183 A JPS57147183 A JP S57147183A
Authority
JP
Japan
Prior art keywords
ram1
recorded
data
address
access memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56031468A
Other languages
Japanese (ja)
Inventor
Ryuzo Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56031468A priority Critical patent/JPS57147183A/en
Publication of JPS57147183A publication Critical patent/JPS57147183A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To obtain long and random delay time by using a random access memory RAM. CONSTITUTION:The entitled apparatus is provided with a random access memory (RAM) 1 in/from which data are recorded/read on the basis of addresses and an output data storing means to which output data from the RAM1 are set. An address counter 3 generating addresses with which the RAM1 is accessed and a delay means 5 connected with the write signal application terminal of RAM1 are also installed. After reading data from the area recorded in an address transmitted from the address counter, new data are recorded in the address.
JP56031468A 1981-03-05 1981-03-05 Shift register Pending JPS57147183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56031468A JPS57147183A (en) 1981-03-05 1981-03-05 Shift register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56031468A JPS57147183A (en) 1981-03-05 1981-03-05 Shift register

Publications (1)

Publication Number Publication Date
JPS57147183A true JPS57147183A (en) 1982-09-10

Family

ID=12332085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56031468A Pending JPS57147183A (en) 1981-03-05 1981-03-05 Shift register

Country Status (1)

Country Link
JP (1) JPS57147183A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6228993A (en) * 1985-07-30 1987-02-06 Toshiba Corp Memory device
JPS63175294A (en) * 1987-01-14 1988-07-19 Texas Instr Japan Ltd Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5515682U (en) * 1978-07-18 1980-01-31
JPS5515682B2 (en) * 1972-11-25 1980-04-25

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5515682B2 (en) * 1972-11-25 1980-04-25
JPS5515682U (en) * 1978-07-18 1980-01-31

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6228993A (en) * 1985-07-30 1987-02-06 Toshiba Corp Memory device
JPS63175294A (en) * 1987-01-14 1988-07-19 Texas Instr Japan Ltd Semiconductor device

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