JPS57172589A - Memory access circuit - Google Patents

Memory access circuit

Info

Publication number
JPS57172589A
JPS57172589A JP5553381A JP5553381A JPS57172589A JP S57172589 A JPS57172589 A JP S57172589A JP 5553381 A JP5553381 A JP 5553381A JP 5553381 A JP5553381 A JP 5553381A JP S57172589 A JPS57172589 A JP S57172589A
Authority
JP
Japan
Prior art keywords
memory
signals
inputted
order digit
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5553381A
Other languages
Japanese (ja)
Other versions
JPS6143791B2 (en
Inventor
Akihito Yonehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5553381A priority Critical patent/JPS57172589A/en
Publication of JPS57172589A publication Critical patent/JPS57172589A/en
Publication of JPS6143791B2 publication Critical patent/JPS6143791B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To write and read data correctly by applying to a chip selection terminal a signal obtained by AND of a memory selection signal and a synchronizing signal synchronized with machine cycles. CONSTITUTION:In a memory access circuit, the low-order digit signals of address signals outputted from a microprocessor 1 are connected to inputs of addresses 4 and 5 of an address latch type memory 3, and the high-order digit signals are inputted to a decoder which converts the high-order digit signals into corresponding memory selection signals to the memory 3; and the memory selection signals outputted by the decoder and a machine synchronizing signal outputted by the microprocessor 1 are inputted to an AND circuit, whose output is inputted to the chip selection terminal of the address latch type memory 3.
JP5553381A 1981-04-15 1981-04-15 Memory access circuit Granted JPS57172589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5553381A JPS57172589A (en) 1981-04-15 1981-04-15 Memory access circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5553381A JPS57172589A (en) 1981-04-15 1981-04-15 Memory access circuit

Publications (2)

Publication Number Publication Date
JPS57172589A true JPS57172589A (en) 1982-10-23
JPS6143791B2 JPS6143791B2 (en) 1986-09-30

Family

ID=13001359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5553381A Granted JPS57172589A (en) 1981-04-15 1981-04-15 Memory access circuit

Country Status (1)

Country Link
JP (1) JPS57172589A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925699U (en) * 1982-08-10 1984-02-17 三洋電機株式会社 electronic equipment
JPH01100240U (en) * 1987-12-22 1989-07-05

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925699U (en) * 1982-08-10 1984-02-17 三洋電機株式会社 electronic equipment
JPS633038Y2 (en) * 1982-08-10 1988-01-25
JPH01100240U (en) * 1987-12-22 1989-07-05
JPH0435957Y2 (en) * 1987-12-22 1992-08-25

Also Published As

Publication number Publication date
JPS6143791B2 (en) 1986-09-30

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