JPS5587357A - Memory circuit device - Google Patents

Memory circuit device

Info

Publication number
JPS5587357A
JPS5587357A JP16070878A JP16070878A JPS5587357A JP S5587357 A JPS5587357 A JP S5587357A JP 16070878 A JP16070878 A JP 16070878A JP 16070878 A JP16070878 A JP 16070878A JP S5587357 A JPS5587357 A JP S5587357A
Authority
JP
Japan
Prior art keywords
memory circuit
parallel
same address
circuit device
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16070878A
Other languages
Japanese (ja)
Inventor
Sumitoshi Shirasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16070878A priority Critical patent/JPS5587357A/en
Publication of JPS5587357A publication Critical patent/JPS5587357A/en
Priority to US06/346,145 priority patent/US4450538A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Abstract

PURPOSE:To obtain a memory circuit device featuring a short cycle time with a simple constitution by supplying the same address information in parallel to the plural units of the memory circuit and then giving the time division to the parallel information read out for the serial output. CONSTITUTION:Both RAM31 and 32 receive the access with the same address and via the same address information delivered from address decoder 4. And then the different information memorized in the same address of RAM31 and 32 are read out in parallel. These parallel data are converted into the serial data which received the time division via data multiplexer 7 which is controlled by data selection signal RS. In such constitution, the reading is secured through several sets of RAM's in one access, thus reducing the process cycle time for the memory circuit device.
JP16070878A 1978-12-23 1978-12-23 Memory circuit device Pending JPS5587357A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP16070878A JPS5587357A (en) 1978-12-23 1978-12-23 Memory circuit device
US06/346,145 US4450538A (en) 1978-12-23 1982-02-05 Address accessed memory device having parallel to serial conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16070878A JPS5587357A (en) 1978-12-23 1978-12-23 Memory circuit device

Publications (1)

Publication Number Publication Date
JPS5587357A true JPS5587357A (en) 1980-07-02

Family

ID=15720741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16070878A Pending JPS5587357A (en) 1978-12-23 1978-12-23 Memory circuit device

Country Status (1)

Country Link
JP (1) JPS5587357A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5956277A (en) * 1982-09-22 1984-03-31 Toshiba Corp Memory device
JPS6472218A (en) * 1986-09-02 1989-03-17 Us Energy Digital type programmable signal generator and signal generation therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984539A (en) * 1972-12-20 1974-08-14
JPS5191636A (en) * 1974-10-08 1976-08-11 Adoresushiteiho deetaseiseiho ronrijunikenshutsuho randamuakusesukiokusochi oyobi sonokokujishingohatsuseikairo oyobi sensuzofukuki
JPS52124825A (en) * 1976-04-12 1977-10-20 Mitsubishi Electric Corp High performance memory circuit
JPS5314525A (en) * 1976-07-26 1978-02-09 Nec Corp Memory circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984539A (en) * 1972-12-20 1974-08-14
JPS5191636A (en) * 1974-10-08 1976-08-11 Adoresushiteiho deetaseiseiho ronrijunikenshutsuho randamuakusesukiokusochi oyobi sonokokujishingohatsuseikairo oyobi sensuzofukuki
JPS52124825A (en) * 1976-04-12 1977-10-20 Mitsubishi Electric Corp High performance memory circuit
JPS5314525A (en) * 1976-07-26 1978-02-09 Nec Corp Memory circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5956277A (en) * 1982-09-22 1984-03-31 Toshiba Corp Memory device
JPH0471222B2 (en) * 1982-09-22 1992-11-13 Tokyo Shibaura Electric Co
JPS6472218A (en) * 1986-09-02 1989-03-17 Us Energy Digital type programmable signal generator and signal generation therefor

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