JPS5442944A - Refresh address control system for memory - Google Patents

Refresh address control system for memory

Info

Publication number
JPS5442944A
JPS5442944A JP9664077A JP9664077A JPS5442944A JP S5442944 A JPS5442944 A JP S5442944A JP 9664077 A JP9664077 A JP 9664077A JP 9664077 A JP9664077 A JP 9664077A JP S5442944 A JPS5442944 A JP S5442944A
Authority
JP
Japan
Prior art keywords
memory
control system
address control
refresh address
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9664077A
Other languages
Japanese (ja)
Other versions
JPS5758759B2 (en
Inventor
Hide Miyasaka
Koichi Aida
Ryuichi Usami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9664077A priority Critical patent/JPS5442944A/en
Publication of JPS5442944A publication Critical patent/JPS5442944A/en
Publication of JPS5758759B2 publication Critical patent/JPS5758759B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Abstract

PURPOSE:To prevent effectively the destruction of the memory information through multiple selection of the raw address regardless of variation of the CPU address under the refresh, by giving the final control to the raw address via the signal meaning that the refresh cycle is in mid course.
JP9664077A 1977-08-12 1977-08-12 Refresh address control system for memory Granted JPS5442944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9664077A JPS5442944A (en) 1977-08-12 1977-08-12 Refresh address control system for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9664077A JPS5442944A (en) 1977-08-12 1977-08-12 Refresh address control system for memory

Publications (2)

Publication Number Publication Date
JPS5442944A true JPS5442944A (en) 1979-04-05
JPS5758759B2 JPS5758759B2 (en) 1982-12-10

Family

ID=14170417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9664077A Granted JPS5442944A (en) 1977-08-12 1977-08-12 Refresh address control system for memory

Country Status (1)

Country Link
JP (1) JPS5442944A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151893A (en) * 1984-01-18 1985-08-09 Nec Corp Semiconductor memory circuit
JPS63140490A (en) * 1986-12-03 1988-06-13 Sharp Corp Dynamic ram

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151893A (en) * 1984-01-18 1985-08-09 Nec Corp Semiconductor memory circuit
JPS63140490A (en) * 1986-12-03 1988-06-13 Sharp Corp Dynamic ram

Also Published As

Publication number Publication date
JPS5758759B2 (en) 1982-12-10

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