JPS5956277A - Memory device - Google Patents

Abstract

PURPOSE:To make possible the access of a desired address by accessing a memory group with an effective address to convert the same memory address to addresses matched to states required to respective picture memories. CONSTITUTION:A single memory address is outputtd from a memory controller 1 and is given as a common memory address to memories 3a, 3b, and 3c. In memories 3a-3c, the given memory address is modified with preliminarily set modification values as required by address converting circuits provided in memories 3a-3c and is converted to effective addresses which memories 3a-3c require, and these effective addresses are used for respective access of memories 3a-3c. In address converting circuits of memories 3a-3c, the output value of a selector 21 is preliminarily set to zero in case of the memory 3a and is set to (n) in case of the memory 3b and is set to N in case of the memory 3c.

Description

DETAILED DESCRIPTION OF THE INVENTION [One non-technical aspect of the invention] The present invention relates to an improvement of a image capture device used as a single-image memory or the like.

[Technical Background of the Invention 1; t) In recent years, the capacity of IC memory (semiconductor memory) has become larger and the price has been reduced. Image memory (frame memory), which can store exactly the same image, has become widely used.

Then, there is one that has a plurality of image memories, and is configured to read and write song data to the image memory of the image memory in lines 'a-, 11α,
In this case, the memory controller that generates memory addresses for image memory access must generate all memory addresses for each image memory according to each state. , the equipment becomes more complex.

In addition, since all TV images are targeted, the images are of a standard size of 30 frames per second, so the TV image f'! r! The data must be transmitted at full speed, and it is displayed at the same time.] 5) In addition, full screen display, partial image display, partially enlarged display, 1. Due to the diversification, there are cases where each image requires a completely different address for reading and accessing the memory. The burden on the memory controller that must be generated each time is increasing.

Therefore, it is desirable to have a device that can access multiple image memories by simply giving them the same memory address by converting it into an address that matches the requested state. The present invention has been made in view of the above circumstances, and provides a memory device that can convert addresses that match the state required for each image memory by simply giving all the same memory addresses, and allows access to all desired addresses. The purpose is to provide.

[Summary of the invention]

That is, in order to achieve the above objects, the present invention has various aspects.
A plurality of independent memories facing each other, a memory controller that sequentially generates common memory addresses, and each of the memories 7! A memory group is provided corresponding to 'Ii, so that a desired correction amount can be set, and the memory address to be given is modified by this correction amount as an effective address. It is composed of an address converting means for applying a common memory address outputted from the memory controller area to the address converting means of each memory controller, and each address converting means applies the corrections given to this memory address. By modifying the address to obtain an effective address and accessing the memory using this effective address, the memory controller is simplified.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the device of the present invention, in which 1 is a memory controller that sequentially generates a single memory address, 2 is an arithmetic circuit for performing image processing, etc.
3a, 3b, and 3c are each -frame contents/I
'A: (x: Memory that has. The device of the present invention has a main configuration of a memory controller 1 and memories 3ar3b and 3cvr.

Each memory s * y s b v 3 c 't operates by receiving the same memory address output from the memory controller 1, but each memory can be accessed from a different address. r
JbgJc is provided with an address conversion circuit as shown in FIG.

That is, in FIG. 2, 211l-J: number 1 used for correction
It is a selector that makes four choices (direct output), and its input side is connected to the positive potential Vec via the n pull-up resistor nl-R4k.
A plurality of support switches SW for setting data are connected to each other, and one end is connected to the pull-up switch SW for data setting. It is possible to set the digital value correction IE value.Also, the shift 1 which is applied to the control means (1 to 1) not shown in the figure; 7) J:'). 22 is the memory address output by the memory controller 21 and the selector 2.
In addition to inputting all the data output by C, a signal of logic level "0" or "1" which is applied to a control means (not shown) is added and subtracted to the carry input terminal C as a select signal.
This is an adder that adds and subtracts the output data of the selector 21 to and from the input memory address input to IN, and outputs the result of the operation λy as an effective address.

Each of the memories 3m, 3b, and 3c has an address translation circuit configured as described above, and is accessed using the effective address output from this address translation circuit as an address.

Next, the operation of this apparatus having the above configuration will be explained. This device has one memory controller, outputs a single memory address sequentially, and uses this n as a common memory address for each memory 3m and 3b.

Give some relief to 3C. Each memory s a , s h
.

In 3c, the address conversion circuit provided in each memory address is modified as necessary using a correction value set in advance for the given memory address, and each memory 3m, 3b, 3
Then, convert the address into a necessary effective address and use this effective address for each access.

For example, now consider reading out and adding 7t image data stored at address aI of memory 3m and address al-4-n of memory 3b, and storing the JJII n data at address a1 of memory 3c.

Addition processing of image data is performed in the arithmetic circuit 2, and here the processing time of the arithmetic circuit 2 is T.

Assuming that it takes time and that the memory address from the controller 21 changes N during that time, if
If the memory 9a and JbeJc are not provided with an address conversion circuit, the memory controller l sends the memory 3a to the address ai, memory ? All three types of memory addresses must be generated: address al+n for b and branch at-N for memory 3C.

However, in this device, each memory 3alt? b.

Regarding the address conversion circuit in 3C, its selector 2
The output value of the selector 2 is set to zero in the memory 3a, the output value of the memory 3b is set to n, and the output value of the memory 3c is set to N by the switch SW of the memory 3a. The memory write address 11 output from the memory controller 1 is given to each selector 22, and a shift selection signal Rk is given to each selector 2, c and a switch S.
WK, J: Output the set values respectively, add η, and unit 2.
Give 2 and note at the same time'),? a l,? Addition and subtraction between the output of the selector 21 and the memory address ai is performed by applying the addition select signal to the carry input terminal CIN of the IJII multiplier 22 by applying the addition select signal to the memory 3c and the subtraction select signal li to the memory 3a.
i, al-1-n in the memory 3b, and ajN in the memory 3c are each accessed from the adder 22, and these are used as effective addresses for access.

Therefore, when the memory address is ai, the data stored at the address al is read out from the memory 3a, and the data stored at the address al+n is read out from the memory 3b and given to the arithmetic circuit 2. However, the result of the addition is not provided to the memory 3C after a time Tp.

At the time T4 time has elapsed, the memory address output by the memory controller 1 is ij a 1 @-N, but the effective address output by the address conversion circuit in the memory 3c is aI-1-N minus N. Since it is a value, the result of the operation will be stored at address 81 of the memory 3C.

In this way, each memory is provided with an address conversion circuit, and by adding a predetermined value to the memory address output by the memory controller, the address conversion circuit adds the correction EE to the memory address output from the memory controller to address the truly necessary effective address 'fg:? ! Since the memory controller 1 is designed to have a single standard memory address, the memory controller 1 only needs to generate a single reference memory address sequentially.
The configuration becomes simple.

In addition, this device 4 has a configuration in which all of the switches SW can be controlled externally, and when the switch SW is pressed, the addition/subtraction select signal and the shift select signal are externally controlled, and the C9 can control whether or not to modify the effective address. g + 3
The necessary addresses for each of b, , 1 and c can be specified arbitrarily1, and the memory address output by the memory controller 1 is used for reference, so each memory has t By fully controlling the number of corrections to the memory address and the timing of the correction, it is possible to obtain the necessary effective address in accordance with the operating speed of the parts to which image data is exchanged.

It should be noted that the present invention (1) is not limited to the embodiments described above and shown in (1) drawings, but can be implemented with appropriate modifications within the scope of the gist thereof; for example, address modification [1 (
Shift 11)) A storage means for storing the meeting is provided, and this i1. (5 means) [Rear address correction data may be read out and added to the adder VC. In this case, the storage means is 1ζOM (read only memory), RAM (random access memory) or Since the correction amount data kz can be arbitrarily rewritten and changed in the RAM or latch, θ can be made higher than the river (jl k).

〔Effect of the invention〕

As described above in detail, the present invention includes a memory of 7'L-111, which has a predetermined capacity, and a memory of 111.
Memory address TCJIB-, + memory controller to be generated next, i'jfl in each memory group i'L
11, and the desired correction settings are set and given to the above memory address.
j Shiko (lji correct; address conversion means that corrects the sorting and gives it to the memory group as an effective address, and an address conversion means, and sends a common memory address output from the memory controller to each address conversion means, and each address conversion means. The address conversion means corrects the given address by modifying this memory address to obtain the entire effective address of 9. Since the memory group is accessed using this effective address, the memory controller can use one memory.・After all address signals are generated, each address conversion means converts them into the effective addresses required by each memory group, so in the past, a variety of address signals were generated in one memory controller. The configuration is simpler than that of the conventional method, and it also provides a memory device with features such as being able to arbitrarily set the four essential addresses of each memory group to one (1) for the above-mentioned modification control method. 7).

4. Description of Drawings 17n 11' - γ Explanation FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of an address changing circuit.

1...Memory controller, 2...Arithmetic circuit, 3a
r, 9 b, ,? c: memory, 2I: selector, 22: addition γN path, f: W: switch.

Substitute for application Patent attorney Suzue Takehikotts1

Claims (4)

[Claims] (1) It is desired that a plurality of independent memory groups each having a predetermined appearance, a memory controller that sequentially generates a common memory address, and a memory controller that is provided correspondingly to each of the memory groups. The amount of correction Qf can be set and the correction amount Qf
A memory device characterized by comprising address conversion means for giving an effective address to a corresponding memory group. (2) The memory device according to claim 1, characterized in that the address conversion means is modified by using a setting means for setting 11α using a switch;
4゜ (3) Ill +h 'i in address conversion means
ii, 'Setting is performed by using a memory device in which correction amount data is stored, and the desired correction 1F → data read out from this memory device is used as the end.Patent 1 to 1. Memory device as described. (4) The memory device according to claim 3, wherein the storage means is capable of changing all correction amount data.