JPS60124785A - Picture processing unit - Google Patents

Abstract

PURPOSE:To attain arithmetic of a window function in high speed by using an address of a specific bit and an address of an adder circuit to access respectively a memory unit. CONSTITUTION:The window consists of 2X2-bit to a picture memory. Then memory units 9, 10-12 being of the same number as the bit number in the window are provided. Moreover, registers 3, 4 and 5 storing the difference between an address of the specific bit in the window and an address of other bits are provided. Adder circuits 6, 7 and 8 adding specific bits at write/read of the memory units are provided. Then the memory units 9-12 are accessed respectively by using the address of the specific bit and the address of the adder circuits 6-8. Thus, all bits in the window of the picture memory are read by one accessing and the result is outputted via a ROM13.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an image processing apparatus, and particularly to window operations (eg, i!
! ! The present invention relates to an image processing device that can perform processing such as thinning lines of an I image by performing calculations based on the states of bits surrounding a bit to be processed at high speed.

(b) Prior Art and Problems The image data stored in the image memory may be processed to, for example, make the lines of characters thinner, or to smooth out the unevenness of the image. In this case, it is determined whether a certain bit to be processed is made black or white based on the focus state around the bit. At this time, for example, 3×3
An area on the image memory such as a hint or 2×2 bit is used as a window, and the window is moved to perform calculations. FIG. 1 is a diagram illustrating a 2×2 window. For example, if the target to be processed in the image memory 1 is ■, the surrounding bits are ■, ■.

■It is. Based on the hit states of ■ to ■, it is calculated and determined whether the bit of ■ is to be black or white.

Window 2 is composed of 4 bits from ■ to ■.

Conventionally, when reading and calculating the bits within the window, the image memory 1 is accessed four times, and a shift register is used.

However, the former requires accessing four times to read one window 2, which increases the image processing time, and the latter is effective when the windows 2 move sequentially on the image memory 1, but the window 2'
It has the disadvantage that it is not suitable for complex processing using a processor that moves fc randomly.

(C,) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks by providing the same number of memory units as the number of focal points within the window, and when writing or reading from the memory unit, the address of the peripheral bit for the bit to be processed is An object of the present invention is to provide an image processing device that can read out all bits within a window in - times of access by providing the difference between the two times.

(d) Configuration of the Invention 1 The configuration of the present invention is an image processing device that performs an nxn bit window operation on a certain bit of bitmap-like image data, wherein the memory number i is the same as the number of pins in the window.
- means for storing a difference between the address of a specific bit and the address of other bits within the window, and means for adding the difference to the address of the specific bit when writing or reading from the memory unit; Each of the memory units is accessed using the address of the specific bit and the address of the adding means.

(e) Embodiments of the Invention The present invention uses a plurality of memory units to read data within a window in - times, allowing complex window function calculations to be performed at high speed. be.

FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention. This embodiment shows the case of a window consisting of 4 bits such as 2x2 bits or 4x1 bits.

Therefore, four memory units, 9.10 and 11.12, are used. If there are 3 x 3 bins from 1 onwards, use 9 units. Data to be written into memory units 9 to 12 is input from terminal DI. The address of a specific pin I (for example, ■ in FIG. 1) to be processed within the window is input from the terminal DA. The difference between the address (2) and the address (2) in FIG. 1 is input to the terminal and stored in the register 3. Also, the difference between the addresses of ■ and ■ is entered and stored in the register 7. Furthermore, the difference between the addresses of ■ and ■ is entered and stored in the register 8.

Since these differences are determined by the configurations of the memory units 9 to 12, they may be calculated and stored in advance. Terminal C
, TI- input signals to control the outputs of registers 3 to 5. For example, when θ111 child CTL is “B”, registers 3 to 5 are input.
The outputs of 5 are sent to adders 6, 7.8, respectively, and when it is "0", 0 is sent out. When writing data input from terminal DI to memory units 1 to 9 to 12, set terminal CTL to “
0'', the output of adders 6-8 is the same as the address of terminal DA, so this data is stored in memory units 9-12.
are respectively written to the same address. Memory unit 9~
When data is not read from terminal 12, when terminal CT L is set to "1", the differential address of register 3 is added to the specified node address input from terminal DA by adder 6, enters memory node 1-10, and is stored in register 4. The differential address of the register 5 is added by the adder 7 to the address of a specific bit input from the terminal DA and enters the memory unit node 11, and the differential address of the register 5 is added by the adder 8 to the address of a specific bit input from the terminal DA and input to the memory unit Enter y l・12. (The address of ■ shown in Figure 1 is terminal DA.
If input from , the data of ■ is successively output from the memory unit 1-9, the data of ■ is output from the memory unit 10, the data of ■ is output from the memory unit 11, and the data of ■ is output from the memory unit 12, respectively, and the output DO1, 1)02° DO3, DO
4, respectively. Therefore, it is possible to avoid reading out the four pixels ① to ① at the same time.

The ROM 13 stores a table, and the above D01 to D
It is used when processing the output of O4 by referring to a table. That is, when processing is performed using a table, the processing speed can be further improved.

In the above operation, the terminal CTL is set to "0" when writing and set to "'l" when reading, but the same is true if the terminal CTL is set to "1" when writing and "0" when reading. By changing the values, 4X1 etc. can be implemented in the same way as 1ijJ.

(f) As described in detail, the present invention can read all the bits within the window on the image memory in one access, and therefore can perform window function calculations at high speed.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining a 2×2 window, and FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention. 1 is image memory, 2 is window, 3, 4.5 is register, 6,
7.8 is an adder, and 9, 10, 11.12 are memory nodes 1-113 are ROMs. '5J 18

Claims (1)

[Claims] n for focus with bitmap image data
X An image processing device that performs an n-bit window operation, which stores the same number of memory units as the number of focuses within the window, and the difference between the atrus of a specific focus within the window and the addresses of other pins. and means for adding the difference to the address of the specific bit when writing or reading from the memory unit, and each of the memory units is accessed using the address of the specific bit and the address of the adding means. Characteristic image processing device.