JPH0120514B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to an improvement in a memory write circuit that writes a predetermined level or its inverted level only to specified bits of multiple bits of data stored in a memory. It is.

(2) Prior art and problems Conventionally, for example, a certain figure is stored in a screen memory as binary data of "1" and "0" for each scanning line, and a figure that partially overlaps with the figure is stored in an input register. When storing binary data and writing it to screen memory, the latter "1" is newly written to the pixel where the former "1" and the latter "1" overlap, and the former "0" position. There are pixels that

In any case, for each bit of binary data in the screen memory, only the bit corresponding to "1" of the binary data in the input register needs to be rewritten.
On the other hand, if you want to make a predetermined part of a figure in the screen memory blank (delete it) and write characters, etc., invert the binary data "1" that indicates the figure corresponding to the blank background, and then write 2 in the screen memory. All you have to do is rewrite the corresponding bit of the value data.

FIGS. 1a to 1c show the writing method in such a case using data examples.

Figure a shows data 2 for each line shown in the screen memory 1, into which data 3 of the input register is written.

The figures from b to b in the same figure show the case of the above-mentioned duplicate writing, and in order to duplicate the data in the input register with the data in the memory, only the bit in the memory corresponding to “1” in the input register is rewritten to “1”.
The memory bit corresponding to “0” is left as is,
The rewrite memory data can be obtained.

On the other hand, c to c in the same figure show the case of creating a blank map shape, and in order to create a blank background based on the input register data in the memory data of The inverted bit is rewritten to "0" and the bit in the memory corresponding to "0" is left as is to obtain data in the rewritten memory.

Conventionally, the method of realizing the above writing is to perform processing by a program in a processing unit (CPU), transfer addresses and data between this and memory and registers, perform reading and writing, and process. However, the disadvantage is that the procedure is complicated and the processing time is too long.

(3) Purpose of the Invention The purpose of the present invention is to write a predetermined level or an inverted level only to designated bits of multiple bits of data stored in a memory, and particularly to provide a memory writing circuit with simplified configuration and procedure. That's true.

(4) Structure of the Invention In order to achieve the above object, the memory write circuit of the present invention includes an input register that holds data of a plurality of bits to which a memory storage position is assigned corresponding to each bit position, and A memory write circuit that writes only data at a bit position that holds data at a predetermined level among the bit positions to a storage location in a memory allocated to the bit position at the predetermined level or its inverted level, Means for providing a write permission signal to a storage location in a memory allocated corresponding to a bit location that holds data at a predetermined level among the data in the input register; an exclusive OR circuit which is provided as an input circuit and receives the data at the relevant bit position as one input, and whose output is input to a memory storage location corresponding to each bit position, and the other exclusive OR circuit. When data of a predetermined level of the input register is written to the memory in duplicate, a signal of an inverted level of the predetermined level is applied to the memory, and the data of the predetermined level of the input register is connected to the memory. The present invention is characterized by comprising a signal line to which the signal of the predetermined level is applied when data is inverted and written.

(5) Embodiments of the Invention The present invention allows parallel input from an input register to a memory through one input of an EOR circuit, gives a level of "0" or "1" to the other common input, and uses a write enable signal. It writes to the specified bit.

FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention.
In the figure, for example, eight EOR circuits 12 are connected in parallel from each bit of an 8-bit input register 11.
A common function selection (FSLCT) signal "0" is input to each bit of the memory 10 through one input of the EOR circuit 12.
Or give “1”. In addition, the input register 11
The outputs of each multiplexer 13 are input to one input of eight AND circuits 14, and the output of each multiplexer 13 is input to one input of eight AND circuits 14. A write enable (WE) signal is input to the input, and the output of these AND circuits 14 is sent to the memory 10.
into each bit. When the multiplexer selection (MSLCT) signal is set to "0" for the multiplexer 13 in this case, the signal passes through the multiplexer 13 as is and accesses the memory 10 in the normal mode using the WE signal.

MSLCT signal of multiplexer 13 is “1”
When the input FSLCT signal of the EOR circuit 12 is "0", the multiplexer 13,
The WE signal is applied to the memory 10 via the AND circuit 14, and "1" is output only in response to the input "1" of the EOR circuit 12, thereby rewriting the corresponding bit in the memory 10. Input “0” of EOR circuit 12
For, multiplexer 13, AND circuit 1
4 does not give the WE signal to the memory 10, so rewriting is not performed [see Figure 1b] The MSLCT signal of the multiplexer 13 is "1"
When the input FSLCT signal of the EOR circuit 12 is "1", the multiplexer 13,
The WE signal is applied to the memory 10 via the AND circuit 14, and "0" is output only to the input "1" of the EOR circuit 12, thereby rewriting the corresponding bit in the memory 10. Input “0” of EOR circuit 12
For, multiplexer 13, AND circuit 1
4, the WE signal is not applied to the memory 10, so no rewriting is performed. [See Figure 1c] (6) Effects of the Invention As explained above, according to the present invention, a write enable signal is given to a bit of a predetermined level of data in an input register, and each bit of the data is Each bit of memory data is input through one input of the EOR circuit, and the other input is used in common to switch between binary levels. By providing hard logic between the memory and the input register in this way, it is possible to duplicate or delete the contents of the input register with respect to the memory contents at high speed with a simple configuration and procedure. It is.

[Brief explanation of drawings]

1A to 1C are general explanatory diagrams of a memory writing method, and FIG. 2 is an explanatory diagram of a configuration of an embodiment of the present invention, in which 10 is a memory, 11 is an input register,
12 is an EOR circuit, 13 is a multiplexer, 14
indicates an AND circuit.

Claims (1)

[Claims] 1. A memory 10 corresponding to each bit position.
The input register 11 is provided with an input register 11 that holds data of a plurality of bits to which storage positions are allocated, and of the data, only the data of the bit position holding data of a predetermined level is stored in the memory allocated corresponding to the bit position. A memory write circuit that writes the predetermined level or its inverted level to a storage location, the memory storage location being allocated corresponding to a bit position that holds data of the predetermined level among the data in the input register. means 13 and 14 for giving a write permission signal to the input register; and means 13 and 14 provided corresponding to each bit of the input register, the data at the bit position being given as one input, and the output corresponding to each bit position. an exclusive OR circuit 12 that is input to a storage location of the memory; and an exclusive OR circuit 12 that is commonly connected to the other input of the exclusive OR circuit, and is configured to duplicate data of a predetermined level of the input register in the memory. a signal line (FSLCT) to which a signal at an inverted level of the predetermined level is applied when writing, and to which a signal at the predetermined level is applied when data at the predetermined level of the input register is inverted and written to the memory; A memory writing circuit characterized by comprising: