JPH04195563A - Controller for memory system - Google Patents

Abstract

PURPOSE:To rewrite only changed data in each unit less than a cache block by storing whether each data unit smaller than the cache block is changed or not and controlling rewriting in a main storage based upon a decoded result. CONSTITUTION:Respective storage means 4, 11 store information indicating data state in accordance with subblocks divided as data units smaller than the cache block. A constituting means 35 reads out the data of corresponding subblocks and the tag information of the subblocks based upon the data state information stored in the storage means 4, 11 in accordance with a write request to a main storage device 14 and constitutes write data in the device 14. A control means 46 controls the transfer of the data constituted by the means 35. Consequently only the changed data out of data managed in each block unit can be rewritten in the main storage 14 in each unit smaller than the block.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control device in a storage system in which cache memory updates and main memory updates are managed by a store-in method.

[Prior art] Figures 6 to 8 are 1, for example, Nikkei Electronics "32
Bit MPU with built-in bus snoop function for multiprocessors (July 24, 1989 issue (No. 47)
8) p! 73 to p179) is the conventional cache memory control device shown in FIG. In the figure, (1) and (8
) is the central processing unit, (2) and (9) are the processor buses for the central processing units (1) and (8), respectively;
(3) and (io) are central processing units (1)° and (8)
Cache memory management unit for (5) and (1
2) is data of cache blocks managed by cache memory management units (3) and (10), each having a length of 4 words. (4) and (i, i) are state storage sections that store the states of data sections (6) and (13), respectively;
There are three states: "invalid", "shared", and "updated". The meanings of these states are as follows. "
"Invalid" is a state in which the data in the cache block is invalid, "Shared" is a state in which the data in the cache block and the corresponding main memory data match, and "Updated" is a state in which the data in the cache block has been updated and Indicates a state that does not match the corresponding main memory data.

(7) is the system bus, (14) is the main memory, (15
) is data for 4 words corresponding to data sections (6) and (13) in main memory (14), and (16) is 4 words worth of data corresponding to data sections (6) and (13) in main memory (14).
It represents an address for each word of one word of data (15).

Next, the operation when a cache miss occurs during reading in the cache memory management unit (3) will be explained.

In FIG. 6, cache memory management unit (3)
and (10) have 4-word cache blocks (6) and (13) starting from the PA address. In the initial state, cache block (6) is A.

It has data of B, C, D, its state storage unit (4) indicates an invalid state, and its cache block (13) has data of G, B,
Assume that data of C and D is included, and the state storage unit (11) thereof indicates a shared state.

FIG. 7 shows the cache memory management unit (3) and (l
Cache blocks (6) and (13) of O), state memory sections (4) and (11), and data (1) of main memory (14).
5), and the initial state in Figure 6 is in Figure 7.
This corresponds to (a) in the figure. From this initial state, Fig. 7(b)
As shown in the figure, if the central processing unit (8) rewrites the first word of the cache block (13) from G to H, the data (15) in the main memory is not changed and the cache block (13) only can be rewritten. At this time, the state storage section (11) of the cache block (13) indicates the updated state. Furthermore, the contents of the state storage section (4) of the cache block (6) remain unchanged.

It remains disabled. Next, the central processing unit (1
) attempts to read data B at address PA+4 of cache block (6), the state storage unit (4) indicates an invalid state, so the cache memory management unit (
3) outputs a wait signal to the central processing unit (1) and starts accessing the main memory (14) via the system bus (7). Cache memory management unit (lO
) compares the address of address PA+4 that the cache memory management unit (3) outputs to the system bus (7) with its own cache tag (12), and at this time, the cache block (13) is hit, but the cache block Since the status storage unit (113) in (13) indicates the updated status, a retry signal is output to prohibit the cache memory management unit (3) from fetching erroneous data.

The cache memory management unit (10) stores the cache block (13), that is, 4 words (16 bytes) of data H and B starting from address PA+4.

Transfer C and D to the main memory (14). Due to this transfer, the cache block (13) becomes the same as the data in the main memory (14) and is shared, so the state memory unit (13)
) becomes a shared state (FIG. 7(C)). Therefore, the cache memory management unit (3) has a cache block (
6) Correct data H, B, C, D from main memory (14)
The cache block (6) is transferred to the central processing unit (CPU), and the state storage section (4) of the cache block (6) becomes shared (FIG. 7(d)).

[Problems to be Solved by the Invention] The conventional cache memory control device is configured as described above, and since the write-back operation to the main memory is performed for all cache blocks, it is possible to write back data to the main memory for all cache blocks. This means that you are performing a wasteful operation of writing back all the way to . Therefore, there is a problem in that the amount of data transferred to the main memory of the central processing unit increases, and the processing speed of the central processing unit decreases. This invention was made to solve these problems, and it is a cache that can write back to main memory only the data that has been changed among the data managed in blocks. The purpose is to obtain a memory control device.

[Means for Solving the Problems] A control method for a cache memory device according to the present invention includes:
Storage means for storing information indicating the state of data corresponding to sub-blocks divided into data units smaller than the cache block; and the state of the data stored in the storage means in response to a write request to the main storage device. configuring means for reading corresponding sub-block data and sub-block tag information based on the information and configuring write data to the main storage device; and control means for controlling transfer of the data configured by the configuring means. Equipped with

[Operation] In this invention, a flag is set for each smaller data unit in a cache block to determine whether it has been updated, and depending on how the flag is set, the updated data unit is configured as data written back to the main memory. , write to main memory.

[Example] FIG. 1 is a diagram showing an embodiment of the present invention.

In the figure, (17) and (I8) are 4-bit flags that store word by word whether data in cache blocks (6) and (13) have been updated. Each bit of this update flag corresponds to four words of data in the corresponding cache block from left to right, and when a word is updated,
It is l only when the cache block is in an updated state, that is, the state storage unit is in an updated state, and is 0 in all other cases. (22) is a setting circuit for the update flag (17) (or (18)).

Moreover, FIG. 4(a) is a diagram showing the configuration of the setting circuit, and (
20) is a bus that takes in the data of the state storage unit (4) (or (ll)), (19) is a register that temporarily holds the lower 2 bits of the write address, and (21) is a bus that sets the lower 2 bits of the write address. The bus for inputting into the circuit (22), (23) to (26) are the setting circuit (2
The data determined in 2) are updated to update flags O to 3.
The bus (17) is an update flag for outputting the bit. In addition, the setting circuit (22) has a configuration shown in FIG.
It has a table as shown in (b), which determines the output data.

Returning to FIG. 1, (35) is the a data configuration circuit.

(40) is output data configured by the output data configuration circuit (35), and (44) is data representing the number of words of the output data, which is output from the output data configuration circuit (35).

FIG. 5 is a diagram showing details of the work number data of the output data configuration circuit (35) and its output data (40), where (6) (or (13)) is the data of the cache block, (27) - (30) are buses for inputting cache block data (6) (or (13)) to the output data configuration circuit (35), (171 (or (18)) is an update flag, (31) - ( 34) is a bus for inputting the update flag (17) (or (18)) to the data configuration circuit (35). The data configuration circuit (35) inputs the data (6) (
or (13) '), only the word whose corresponding update flag (17) (or (18)) bit is 1 is transferred to the output bus without changing the order within the cache block. The data is output through (36) to (39) to the 49-word write data register (40) in a left-justified manner. At the same time, write register (40
) Outputs to the data register (44) the number of valid words counting from 0.

Returning to FIG. 1, (41) and (42) are buses for transferring the flag (17) or (18) of the sub-block to the main memory, and are hereinafter referred to as flag buses. (45) is a write transfer device which transfers the update flag (17) or (18) to the main memory (14) via the flag bus (41) or (42).
) is transferred to the write control device (46), and the valid data in the output data (40) is transferred to the word count data (
The data up to the word indicated by 44) is transferred to the write control device (46) via the system bus (7). The write control device (46) writes valid data in the sent output data to the main memory based on the update flag (17) (or (18)).

Next, based on FIG. 1, a control method when a cache miss occurs at the time of reading in the cache memory control device will be explained.

In FIG. 1, cache memory management unit (3)
and the cache memory management unit (IO).

It has 4-word cache blocks (6) and (13) starting from address PA. In the initial state, cache blocks (6) are A, B, and C.

It has data of D, its state storage unit (4) shows an invalid state, and its cache block (13) has data of G and B.

It is assumed that the state storage section 1) has data C and D, and that the state storage section 1) indicates a shared state. Cache block (6)
, update flags (17), (18) for (13)
) are both 0000. At this time, if the central processing unit (8) rewrites the data (13) at address PA+4 from G to H as shown in FIG. 4, the data in the main memory (14) will not be changed and the cache block Only (13) is rewritten. At this time, the state storage unit (11) of the Cagini block (13) is in the updated state, and the update flag (18) has the bit for the first word set to 1.
It becomes 1000. Also.

The cache block (6) remains unchanged, its state storage section (4) continues to indicate an invalid state, and its update flag (17) is also 0000. In such a state, the central processing unit (1) uses the address PA of the cache block (6).
When attempting to read the data at address +4, the cache memory management unit (3) will read the data at address +4 because its state storage unit (4) indicates an invalid state.

Central processing unit (1) via processor bus (2)
It outputs a wait signal to the main memory (14) and starts accessing the main memory (14) via the system bus (7).

The cache memory management unit (10) compares the address output by the cache memory management unit (3) to the system bus (7) with its own cache tag (12), and at this time, the cache block (13) is hit. Since the state storage section (11) of the cache block (13) indicates the updated state, a retry signal is output to prohibit the cache memory management unit (3) from fetching incorrect contents. and.

The cache memory management unit (3) outputs only the 4-word data starting from the address PA, that is, the H of the first word indicated by the update flag (18) of the cache block (13), to the output data configuration circuit (35). is set in the write data register (40) in a left-justified manner, and OO is set in the register (44), indicating that only the first word of the write data register (40) is valid. Furthermore, the write data transfer device (45) in the 1B cache memory management unit (lO) has an update flag (18) and a write data register (40).
) is transferred to the write controller (46) in the main memory (14).

The write control device (46) writes the sent l word into the main memory (14) according to the update flag (18). In other words, G at address PA is rewritten to H. Then, the cache block (13) is transferred to the main memory (14).
) will be shared with data (15) in (
shared state), the update flag (18) is reset to 0000. Therefore, cache memory management unit (3)
reads the correct data from the main memory (14) into the cache block (6), passes the data at address PA+4 of the cache block (6) to the central processing unit (1), and the cache block (6) becomes shared. . (
Figure 6). At this time, the update flag (17) of the cache block (6) remains at 0000.

[Effects of the Invention] As described above, according to the present invention, in addition to the change bit that stores whether or not data has been changed for each cache block, it is also possible to determine whether or not data has been changed for each smaller unit of data in the cache block. Since the cache block is configured to include a storage means for storing the data and a means for recognizing the storage means and decoding it, and to control writing back to the main memory based on the decoding result, the cache block can be managed in units of cache blocks. Only the data that has changed among the data in
It becomes possible to write back to the main memory in units smaller than one cache block, thereby reducing the amount of data transferred to the main memory of the central processing unit and improving the processing speed of the central processing unit.

[Brief explanation of the drawing]

1 to 3 are block diagrams showing one embodiment of the present invention, FIG. 4 is a detailed diagram of an update flag setting circuit, FIG. 5 is a detailed diagram of an output data configuration circuit, and FIG. 6 is a conventional cache FIG. 7 is a block diagram showing the memory control method, and is a diagram explaining the relationship between the state storage section and data. (1), (8)... central processing unit, (3)
, (10) -- Cache memory management unit,
(4), (11)...state storage unit, (7)
...System bus, (14)...Main memory. f22)--update flag setting circuit, (17), (
1, 8)... Update flag, (35)... Output data configuration circuit, (45)... Write data transfer device, (46)... Write control circuit. A considerable portion is shown.

Claims (1)

[Scope of Claims] Controls a memory system consisting of a main storage device and a plurality of cache memory devices connected to the main storage device and each of which stores part of the data stored in the main storage device in block units and operates independently. A control device comprising: storage means for storing information indicating the state of data corresponding to sub-blocks obtained by dividing the block into smaller data units; and storage means for storing information in the storage means in response to a write request to the main storage device. write data configuring means for configuring data to be written to the main storage device by reading corresponding sub-block data and sub-block tag information based on state information of the data; and output data of the write data configuring means. A control device for a memory system, comprising: a control means for controlling transfer of data to a main storage device; and a control device for a memory system.