JPH04330541A - Common data transfer system - Google Patents

Abstract

PURPOSE:To prevent the load of a CPU from being increased by monitoring a system bus by devices other than two devices to write data of a read/write common table on the bus in their own common tables. CONSTITUTION:The above system consists of three or more devices such as a current CPU board 1, a standby CPU board 2, and a communication adapter 3 which are connected to a system bus 9. Each of these devices is provided with a CPU 4 and a common table 6 where information common to devices is stored, and two prescribed devices, namely, the current CPU board 1 and the communication adapter 3 out of these devices always read and write data in common tables 6 of each other through the system bus 9. In this case, the device other than two devices, namely, the standby CPU board 2 writes a direction signal and data of common tables on the system bus 9 in its own table when decoding the address signal to common tables 6 on the system bus 9 through an address decoder based on setting to a switch.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a system consisting of three or more devices each having a common table for storing common data and connected to a system bus, in which a predetermined one of the devices is always connected to a system bus. Even if two devices mutually read and write the common table and update its contents, another device can read and write the common table mutually and update its contents.
The present invention relates to a common data transfer system that allows two devices to share updated contents of a common table without increasing the burden on one device. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

0002

2. Description of the Related Art FIG. 1 is a system configuration diagram as an embodiment of the present invention, and the conventional technology will be explained below using this diagram. In the same figure, 1 is the active system C as a host.
PU board 2 is a standby CPU board also serving as a host, 3 is a communication adapter, and 9 is a system bus that connects the boards 1 to 3. Here each board 1-3
The board has a processor 4 and a memory 5, accesses internal memory and registers via a processor bus 8, and serves as a master or slave for other boards via a bus control circuit 7. Note that CB is a communication cable for this system to communicate with the outside, and this communication cable is coupled to the system bus 8 via the communication interface circuit IF in the communication adapter 3. In this system, the active CPU 1 normally communicates with the outside via the communication adapter 3 and the communication cable CB, but if any abnormality occurs in the active CPU board 1,
The operation of the board 1 is stopped, the standby CPU board 2 is newly switched to the active system, and communication with the outside is continued. The communication adapter 3 not only performs communication control in such cases, but also performs operations such as writing data to be shared by the active CPU board 1 and the standby CPU board 2 into both boards 1 and 2. The common table 6 in FIG. 1 is an area allocated to the memory 5 in the three boards 1, 2, and 3.
It is assumed that this is an area in which data to be shared by these three boards 1 to 3, such as data necessary for controlling communication with the outside, is stored.

By the way, the following method can be considered as a method for the standby CPU board 2 to always recognize the information converted between the active CPU board 1 and the communication adapter 3 via the common table 6. (1) When the CPU 4 of the active CPU board 1 changes the exchange information with the communication adapter 3 in the common table 6 of the active system, the common table 6 of the standby CPU board 2
Also rewrite. (2) The standby CPU 4 monitors the active common table 6 at regular intervals, and when the active CPU 4 rewrites the common table 6, the standby CPU 4 rewrites the common table 4 in the standby system. Ru. (3) The CPU 4 in the communication adapter 3 reads the common table 6 of the active CPU board 1, and also rewrites the common table 6 of the standby CPU board 2 if there is a change in its contents.

0004

[Problem to be Solved by the Invention] However, when managing the common table in the standby system using the methods (1) to (3) described in the prior art, it is necessary to control with the standby system in mind, making the management complicated. becomes. In addition, in a system with multiple standby common tables, all of the standby common tables must be rewritten, which may increase the CPU load or interfere with information exchange between the original host (CPU board) and communication adapter. Apart from this, the overall system performance is affected due to the increased number of bus accesses. Furthermore, the conventional method has the problem that even if information is exchanged between the host and the communication adapter, the common table on the standby system may not be rewritten. Therefore, it is an object of the present invention to provide a common data transfer system that can solve the above-mentioned problems.

[0005]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the common data transfer system of claim 1 provides ``three or more devices (such as 9) each connected to a system bus (9, etc.).
(active CPU board 1, standby CPU board 2, communication adapter 3, etc.), and each device has a CPU (4, etc.) and a common table (6, etc.) for storing information common to each device. A system in which predetermined two of the devices (such as the active CPU board 1 and the communication adapter 3) read and write data in a mutual common table via the system bus, wherein: Other devices (such as the standby CPU board 2) other than the two devices monitor the system bus and write the data of the common table that is read and written on the bus into its own common table, Also

In the common data transfer system according to claim 2,
In the common data transfer system according to claim 1,
The other device decodes (via the address decoder 20, etc.) the address signal (14, etc.) for the common table on the system bus based on the setting (on the switch 30, etc.) indicating that the other device is another device. When this happens, the writing is performed via a means (such as the standby system common table/write pulse control circuit 23) that converts the direction signal (such as 15) on the system bus into a write signal (such as the write pulse 18). "do".

[0007]

[Operation] Monitors the address signal 14 on the system bus 9, decodes access to the common table between the active CPU board 1 and the communication adapter 3, and writes the direction signal (read/write signal) 15 on the system bus. At least the standby CPU board 2 is equipped with means for converting the data into signal pulses 18 and fetching the data on the system bus 9, and updates its own common table 6, so that the active CPU board 1 or the communication adapter 3 Reduces the load on the CPU.

[0008]

Embodiments An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. In FIG. 1, the flow of data transfer related to the present invention is indicated by dashed arrows. In the present invention, the contents of the common table 6 of each board 1 to 3 are ultimately shared by each CPU 4 in the active CPU board 1 and the communication adapter 3.
It will be managed by. When the communication adapter 3 writes to the common table 6 in the active CPU board 1,
By mapping the address of the common table 6 so that it looks like the same area for the standby CPU board 2, the communication adapter 3 writes the same data to the common table 6 in each of the active and standby CPU boards 1 and 2. It's crowded. Conversely, when the communication adapter 3 reads the common table 6 in the active CPU board 1, the CPU in the communication adapter 3 reads the data in the same way as usual, as indicated by the broken line arrow in FIG.
At the same time, the standby CPU board 2 writes this data into its own common table 6.

FIG. 2 shows a circuit for controlling access to each common table 6 in the active CPU board 1 and the standby CPU board 2. Each CPU board 1 for active system and standby system,
2 inputs the address signal 14 from the system bus 9, and a common table select signal 27 indicating that the area of the common table 6 has been accessed by the address decoder 20.
Output. Based on this common table select signal 27 and the direction signal (read/write signal) 15 on the system bus 9, a write pulse 18 creates a timing for transferring external data to the common table 6, and data is transferred from the common table 6 to the system bus 9. A read pulse 19 is generated to create the timing for transfer. The setting of whether the CPU board in question is active CPU board 1 or standby CPU board 2 is identified by switch 30 (in this example, 'H'
' is the active system, and 'L' is the standby system), and either the active common table read/write pulse control circuit 22 or the standby common table write pulse control circuit 23 is selected. The common table read/write pulse control circuit 22 of the operating system correctly generates the read pulse 19 and the write pulse 18 in response to the read and write of the direction signal 15 from the system bus 9, respectively.
The standby common table write pulse control circuit 23 outputs read pulse 1 even when the direction signal is in the read direction.
9 is not output, but a write pulse 19 is generated.

FIG. 3 shows the timing of main signals when the communication adapter 3 reads the common table 6 in the active CPU board 1. Active system common table/read/write pulse control circuit 22 and standby system common table/
Since the write pulse control circuit 23 writes to the common table 6 of the standby CPU board 2 at the timing of reading the common table 6 of the active CPU board 1, the timing at which the write of the standby system ends is determined in the active system. The read pulse 19 (active 'L') taken into account is output, and the standby system outputs the write pulse 18 (active 'L') after the data from the active system is output to the bus and determined. The data buffer controllers 25 and 26 for the common table of the active system and the standby system control the direction and timing of the data of the active system or the standby system using the common table select signal 27 (active 'L') and the read and write pulses 18 and 19. is used to control the data 16.

[0011]

According to the present invention, three or more devices (operating system CPU board 1
, a standby CPU board 2, a communication adapter 3, etc.), and each device is equipped with a CPU 4 and a common table 6 for storing information common to each device, and a predetermined two of the devices is always A system in which two (active CPU board 1 and communication adapter 3) mutually read and write data in a common table 6 via the system bus 9,
Among the devices, other devices (standby CPU board 2) other than the two devices have a switch 3 indicating that they are other devices.
When the address signal 14 for the common table 6 on the system bus 9 is decoded via the address decoder 20 based on the setting to 0, there is a wait for converting the direction signal 15 on the system bus 9 into a write pulse 18. Since the data of the common table that is read and written on the system bus is written to the own common table through the system common table write pulse control circuit 23, the communication adapter can be easily controlled by using a simple circuit. Even when reading the active system's common table, the data is written to the standby system's common table, and the standby system CPU board is kept in mind when exchanging information between the active system CPU board and the communication adapter via the common table. It becomes possible for the standby CPU board to always recognize exchange information of common table data via the system bus without any control. Even in a system where there are multiple standby common tables, all the standby common tables are rewritten by a read from the communication adapter, so there is no performance impact on the communication adapter.

[Brief explanation of drawings]

[Fig. 1] System configuration diagram as an embodiment of the present invention

[Figure 2] Configuration diagram of the access control circuit for the common table

[Figure 3] Time chart for explaining the operation in Figure 2

[Explanation of symbols]

1 Active CPU board 2 Standby CPU board 3 Communication adapter 4 CPU 5 Memory 6 Common table 7 Bus control circuit 8 Processor bus 9 System bus 14 Address signal 15 Direction signal 16 Data 17 Active/standby identification signal 18 Write pulse 19 Read pulse 20 Address decoder 22 Active system common table/read/write pulse control circuit 23 Standby system common table/write pulse control circuit 30 Switch

Claims (2)

[Claims] Claim 1: Consisting of three or more devices each connected to a system bus, each device is equipped with a CPU and a common table for storing information common to each device, and one of the devices is always connected to a system bus. A system in which two predetermined devices read and write data in a mutual common table via the system bus, and other devices other than the two devices monitor the system bus and read and write data in a mutual common table via the system bus. A common data transmission system characterized in that data of the common table that is read and written is written to the own common table. 2. The common data transfer system according to claim 1, when the other device decodes an address signal for the common table on the system bus based on a setting indicating that the other device is another device. The common data transfer system is characterized in that the writing is performed via means for converting a direction signal on the system bus into a write signal.