JPH1027004A - Standby redundant system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an access cycle time for tracking short and to lighten a tracking load by writing control information of an in-operation system in a common memory when the bus right of the tracking bus of a standby system is obtained. SOLUTION: A tracking bus right arbitrating circuit 31 arbitrates the bus right of the in-operation system tracking bus 102 and the bus right of the standby system tracking bus 202 and also manages the presence of the bus right of the in-operation system tracking bus 102 and the bus right of the standby system tracking bus 202 at one place with flags respectively. Further, a stand-by common memory 26 is stored with the control bus 102 of the in-operation system. Then when this bus right managing means obtains the bus rights of the tracking bus 102 of operating system and the bus right of the tracking bus 202 of the standby system, control information writing means 10-15 and 23-25 writes the control information of the operating system in the common memory 26 of the standby system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a standby redundancy system.

[0002]

2. Description of the Related Art Conventionally, in a controller of an industrial control device such as a plant management system, the reliability of the entire system has been improved by using a standby redundant system.

This standby redundant system is an operating system (MASTER) that actually performs monitoring control of a plant or the like.
And a standby system (SLAVE) that takes over the monitoring and control operation of the active system when a failure occurs in the active system, thereby improving the reliability of the system.

[0004] As described above, in order for the standby system to take over the monitoring and control operation of the active system when a failure occurs in the active system,
It is necessary for the standby system to take over the control information of the active system. The operation of periodically transmitting the control information of the active system to the standby system from the time of normal operation in order to surely perform such handover without delay is called a tracking operation.

FIG. 4 is a diagram showing the configuration of such a conventional standby redundancy system. In the standby redundant system shown in FIG. 1, the operation meter processor 10 periodically writes control information in the shared memory 26 of the standby system, and the standby system reads the contents of the memory when it is promoted to the active system and continues the processing. .

Hereinafter, the tracking operation will be described. First, an address signal indicating the address of the active tracking bus arbiter 12 is output from the active processor 10 to the active address decoder 11. The address decoder 11 decodes the address signal to obtain an address, and outputs a chip select signal to a chip corresponding to the address.

Here, the chip select signal is output to the active system tracking bus right arbitration circuit 12. When receiving the chip select signal, the active system tracking bus right arbitration circuit 12 outputs a request signal to the standby system tracking bus right arbitration circuit 22 in order to obtain the bus right of the standby system tracking bus 202.

The standby tracking bus right arbitration circuit 22
When the request signal is inputted, the bus right of the standby tracking bus 202 is arbitrated, and when the bus right is obtained, the active tracking bus right arbitration circuit 12 is notified that the bus right has been acquired.

[0009] Next, the standby tracking bus right arbitration circuit 22 sends the active system to the standby buffer memory control circuit 23.
Indicates the write mode of the standby system. The standby-system buffer memory control circuit 23 closes the buffer 24 and opens the buffer 25 when the standby-mode tracking bus right arbitration circuit 22 instructs the write mode of the active system to the standby system.

The active tracking bus right arbitration circuit 12 instructs the buffer memory control circuit 13 in a write mode from the active system to the standby system. The active system buffer memory control circuit 13 includes the active system tracking bus right arbitration circuit 12
When the write mode from the operation system to the standby system is instructed, the buffers 14 and 15 are opened.

Thus, the control data output from the active processor 10 is transferred to the active main bus 101, the bus buffer 14, the active tracking bus 102, the bus buffer 15, the active-standby bus buffer 301, and the standby system. Bus buffer 25, standby tracking bus 202
, It is possible to write to the shared memory 26 of the standby system.

Next, when the writing of the control information to the shared memory 26 of the standby system is completed, the standby buffer memory control circuit 23 switches the tracking bus right arbitration circuit 12 to the active system.
To the end of writing.

The active tracking bus arbitration circuit 12 notifies the active processor 10 that the access cycle has been completed. The above operation is regarded as one cycle, and data is written to one address in one cycle. This operation is repeated by the size of the control data.

In the tracking operation when the standby processor 20 is promoted to the active system, the control information is transmitted to the standby main bus 201, the bus buffer 24, the standby tracking bus 202, and the bus buffer 2 in the same manner as described above.
5. The data is written to the shared memory 16 via the bus buffer 301 between the active system and the standby system, the bus buffer 15, and the active system tracking bus 102.

[0015]

As described above, in the conventional standby redundant system, the active system includes the active system tracking bus right arbitration circuit 12, and the standby system includes the standby system tracking bus right arbitration circuit 22. The active tracking bus 102 is connected to the active tracking bus right arbitration circuit 12.
However, the standby tracking bus right arbitration circuit 22 arbitrated the bus right for the standby tracking bus 202.

Accordingly, since the bus right must be obtained by the two arbitration circuits 12 and 22, the exchange between the active system and the standby system becomes complicated, and a considerable amount of time is required for performing the tracking operation. Was.

However, the tracking operation is not a control operation, and there is a problem that if the tracking process takes a long time, the original control process is hindered.

The present invention has been made in view of the above circumstances, and has as its object to provide a standby redundant system capable of shortening a tracking access cycle and reducing a tracking load.

[0019]

Therefore, to achieve the above object, according to the first aspect of the present invention, there is provided a standby shared memory connected to a standby tracking bus and storing control information of the active system. Arbitrating the bus right of the active tracking bus and the bus right of the standby tracking bus, and unifying the existence of the bus right of the active tracking bus and the bus right of the standby tracking bus. When the bus right management means and the bus right of the active tracking bus and the bus right of the standby tracking bus are obtained by the bus right management means,
Control information writing means for writing the control information of the active system into the shared memory of the standby system.

Further, the invention according to claim 2 is a standby shared memory which is connected to a standby tracking bus and stores control information of the active system, a bus right of the active tracking bus and the standby system. Bus right management means for managing the presence of the bus right of the tracking bus, and the tracking of the standby system when the bus right management means indicates that the bus right of the standby tracking bus exists. Arbitration means for arbitrating a bus; and self-diagnosis means for performing self-diagnosis of the shared memory of the standby system via the tracking bus of the standby system arbitrated by the arbitration means. .

Next, the operation of the claimed invention will be described. According to the first aspect of the present invention, the bus right management unit centrally manages the presence of the bus right of the active tracking bus and the bus right of the standby tracking bus. When the bus right managing unit obtains the bus right of the active tracking bus and the bus right of the standby tracking bus, the control information writing unit writes the active system control information to the standby shared memory. Therefore, the access cycle of tracking is shortened, and as a result, the reliability of the system is improved.

According to a second aspect of the present invention, the bus right management means manages the presence of the bus right of the active tracking bus and the presence of the bus right of the standby tracking bus. When the arbitration means indicates that the bus right of the standby tracking bus exists by the bus right management means, arbitration of the standby tracking bus is performed, and arbitration is performed by the arbitration means by the self-diagnosis means. Since the self-diagnosis of the shared memory of the standby system is performed via the tracking bus of the standby system, the self-diagnosis can be performed at high speed.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a diagram showing a configuration of a standby redundant system according to a first embodiment of the present invention. Note that the same parts as those in FIG.

As shown in FIG. 1, this standby redundant system comprises an active processor 10, an active address decoder 1
1, tracking bus right arbitration circuit 31, active buffer memory control circuit 13, bus buffers 14, 15, active shared memory 16, standby processor 20, standby address decoder 21, standby buffer memory control circuit 23,
A bus buffer 24, a bus buffer 25, and a standby shared memory 26 are provided.

The active processor 10 outputs control information to the active main bus 101. The active processor 10 outputs an address signal indicating an address to the active address decoder 11.

The active system address decoder 11 decodes an address signal output from the active system processor 10 and outputs a chip select signal to a chip corresponding to an address obtained as a result of the decoding.

The tracking bus right arbitration circuit 31 arbitrates the bus right of the active tracking bus 102 and the bus right of the standby tracking bus 202, and arbitrates the bus right of the active tracking bus 102 and the standby tracking bus 2
The presence of the 02 bus right is unifiedly managed by the respective flags.

The tracking bus arbitration circuit 31
Indicates that the buffer memory control circuit 1
3 is instructed from the operation mode to the standby mode. The active-system buffer memory control circuit 13 opens the buffers 14 and 15 when the active-to-standby write mode is instructed by the active tracking bus right arbitration circuit 12.

Further, the tracking bus right arbitration circuit 31
When the standby buffer memory control circuit 23 notifies that the writing of the control information to the shared memory 26 has been completed, it notifies the active processor 10 that the access cycle has been completed.

The active system shared memory 16 stores control information of the active system when the standby system is promoted to the active system. When the standby processor 20 is promoted to the active system, the standby processor 20 transmits control information to the standby main bus 20 in the same manner as the active processor 10.
1 or an address signal indicating an address to the standby system address decoder 21.

The standby buffer memory control circuit 23 closes the buffer 24 when the tracking bus right arbitration circuit 31 instructs the active mode to the standby system write mode.
The buffer 25 is opened.

The standby system buffer memory control circuit 23
Notifies the tracking bus right arbitration circuit 31 that the writing of the control information from the active processor 10 to the shared memory 26 has been completed.

The standby system shared memory 26 stores control information of the active system. Next, the tracking operation of such a standby redundant system will be described. First, an address signal indicating an address is output from the active processor 10 to the active address decoder 11. Address decoder 11
Decodes the address signal to obtain an address, and outputs a chip select signal to a chip corresponding to the address.

Here, the chip select signal is output to the tracking bus arbitration circuit 31. When the chip select signal is input, the tracking bus right arbitration circuit 31 determines the presence of the bus right of the active tracking bus 102 and the presence of the bus right of the standby tracking bus 202 based on the flag. It is determined whether or not the bus right for the standby tracking bus 202 can be acquired.

If the bus rights of the active tracking bus 102 and the standby tracking bus 202 can be acquired, the bus rights of both buses are acquired, and the active buffer memory control circuit 13 and the standby buffer memory control are acquired. The circuit 23 is notified of the write mode of the operating system → the standby system.

The operating system buffer memory control circuit 13 opens the operating system bus buffers 14 and 15 when notified of the write mode from the tracking bus right arbitration circuit 31. Further, upon receiving a write mode notification from the tracking bus right arbitration circuit 31, the standby buffer memory control circuit 23 turns the standby bus buffer 24 "closed" and the standby bus buffer 25 "open".

Thus, the control data output from the active processor 10 is transferred to the active main bus 101, the bus buffer 14, the active tracking bus 102, the bus buffer 15, the active-standby bus buffer 301, and the standby system. Bus buffer 25, standby tracking bus 202
, It is possible to write to the shared memory 26 of the standby system.

Next, when the writing of the control information to the standby shared memory 26 is completed, the standby buffer memory control circuit 23 notifies the tracking bus right arbitration circuit 31 that the writing has been completed.

Then, the tracking bus right arbitration circuit 31
Notifies the active processor 10 that the access cycle has ended. The above operation is regarded as one cycle, and data is written to one address in one cycle. This operation is repeated by the size of the control data.

In the tracking operation when the standby processor 20 is promoted to the active system, the control information is transmitted to the standby main bus 201, the bus buffer 24, the standby tracking bus 202, and the bus buffer 2 in the same manner as described above.
5. The data is written to the shared memory 16 via the active-standby bus buffer 301, the bus buffer 15, and the active tracking bus 102.

In performing self-diagnosis of the standby shared memory 26, when an address indicating the tracking bus right arbitration circuit 31 is output from the standby processor 20, the standby address decoder 21 decodes the address signal. Then, an address is obtained, and a chip select signal is output to the tracking bus right arbitration circuit 31.

When the chip select signal is input from the standby address decoder 21, the tracking bus arbitration circuit 31 determines whether or not the standby tracking bus 202 has a bus right.

When the bus right exists in the standby tracking bus 202, the self-diagnosis mode is notified to the standby buffer memory control circuit 23. When notified of the self-diagnosis mode by the standby tracking bus right arbitration circuit 22, the standby buffer memory control circuit 23 closes the standby bus buffer 25 and opens the standby bus buffer 24. To

As a result, the standby processor 20 is connected to the standby main bus 201 and the standby tracking bus 202.
, Self-diagnosis data can be written and read to and from the shared memory 26, and as a result, the self-diagnosis of the shared memory 26 can be performed.

Therefore, according to the standby redundancy system of the present embodiment, the tracking bus right arbitration circuit 31 centrally manages the bus right of the active tracking bus 102 and the bus right of the standby tracking bus 202. Since the exchange of signals between the operating system and the standby system is reduced, the tracking load can be reduced, and as a result, the tracking processing can be performed in a short time without affecting the original control processing. <Second Embodiment> FIG. 2 is a diagram showing a configuration of a standby redundant system according to a second embodiment of the present invention. Note that the same parts as those in FIG.

The difference between the standby redundant system of this embodiment and the standby redundant system of the above-described first embodiment is that the tracking bus right arbitration circuit integrally manages the states of the active and standby bus rights. Instead, a new arbitration right management circuit 17 is provided, and the arbitration right management circuit 17 manages the status of the bus rights of the active system and the standby system.

As shown in the figure, the standby redundant system comprises an active processor 10, an active address decoder 1
1. Arbitration right management circuit 17, active tracking bus right arbitration circuit 12, active buffer memory control circuit 13, bus buffers 14, 15, active shared memory 16, standby processor 20, standby address decoder 21, standby system A buffer memory control circuit 23, a bus buffer 24, a bus buffer 25, and a standby shared memory 26 are provided.

The active processor 10 outputs control information to the active main bus 101. The active processor 10 outputs an address signal indicating an address to the active address decoder 11.

The active address decoder 11 decodes an address signal output from the active processor 10 and outputs a chip select signal to a chip corresponding to an address obtained as a result of the decoding.

The arbitration right management circuit 17 includes a bus right for the active tracking bus 102 and a standby tracking bus 20.
2 arbitrates for the bus right and operates the tracking bus 10
The presence of the bus right of the second tracking bus 202 and the presence of the bus right of the standby tracking bus 202 are respectively managed in a unified manner by flags.

When the bus right has been acquired, the arbitration right management circuit 17 instructs the buffer memory control circuit 13 and the standby buffer memory control circuit 23 from the operation mode to the standby system write mode.

The active-system buffer memory control circuit 13 opens the buffers 14 and 15 when the arbitration right management circuit 17 instructs the active-to-standby write mode.
To

Operating system tracking bus right arbitration circuit 12
When the standby buffer memory control circuit 23 notifies that the writing of the control information to the shared memory 26 has been completed, it notifies the active processor 10 that the access cycle has been completed.

The active system shared memory 16 stores the active system control information when the standby system is promoted to the active system. When the standby processor 20 is promoted to the active system, the standby processor 20 transmits control information to the standby main bus 20 in the same manner as the active processor 10.
1 or an address signal indicating an address to the standby system address decoder 21.

When the arbitration right management circuit 17 instructs the write mode of the operation system to the standby system, the standby buffer memory control circuit 23 closes the buffer 24 and closes the buffer 25.
To open.

The standby buffer memory control circuit 23
When the writing of the control information from the active processor 10 to the shared memory 26 is completed, the active tracking bus right arbitration circuit 12 is notified that the writing has been completed.

The standby shared memory 26 stores control information of the active system. Next, the tracking operation of such a standby redundant system will be described. First, an address signal indicating the address of the arbitration right management circuit 17 is output from the active processor 10 to the active address decoder 11.
The address decoder 11 decodes the address signal to obtain an address, and outputs a chip select signal to a chip corresponding to the address.

Here, the chip select signal is output to the arbitration right management circuit 17. When the chip select signal is input, the arbitration right management circuit 17 receives the bus right of the active tracking bus 102 and the standby tracking bus 202.
Is determined based on the flag, and the active tracking bus 102 and the standby tracking bus 202 are determined.
It is determined whether or not the bus right can be acquired.

If the bus rights of the active tracking bus 102 and the standby tracking bus 202 can be acquired, the arbitration right management circuit 17 acquires the bus rights of both buses, and the active buffer memory control circuit. 13 and the standby-system buffer memory control circuit 23 are notified of the write mode from the active system to the standby system.

When the arbitration right management circuit 17 receives a write mode notification from the arbitration right management circuit 17,
The active bus buffers 14 and 15 are opened. Also,
Upon receiving the write mode notification from the arbitration right management circuit 17, the standby buffer memory control circuit 23 closes the standby bus buffer 24 and opens the standby bus buffer 25.
To

As a result, the control data output from the active processor 10 is transferred to the active main bus 101, the bus buffer 14, the active tracking bus 102, the bus buffer 15, the active-standby bus buffer 301, and the standby system. Bus buffer 25, standby tracking bus 202
, It is possible to write to the shared memory 26 of the standby system.

Next, when the writing of the control information to the shared memory 26 of the standby system is completed, the standby buffer memory control circuit 23 operates the tracking bus right arbitration circuit 12 of the active system.
To the end of writing.

Then, the active tracking bus arbitration circuit 12 notifies the active processor 10 that the access cycle has been completed. The above operation is regarded as one cycle, and data is written to one address in one cycle. This operation is repeated by the size of the control data.

In the tracking operation when the standby processor 20 is promoted to the active system, the control information is transferred to the standby main bus 201, the bus buffer 24, the standby tracking bus 202, and the bus buffer 2 in the same manner as described above.
5. The data is written to the shared memory 16 via the bus buffer 301 between the active system and the standby system, the bus buffer 15, and the active system tracking bus 102.

The tracking operation of the present embodiment is almost the same as that of the standby redundancy system of the first embodiment, except that the standby shared memory 26 is self-diagnosed by the standby processor. In that it can be performed at high speed.

Next, such a standby shared memory 26
Will be described with reference to FIG. When an address signal indicating the address of the standby tracking bus right arbitration circuit 22 is output from the standby processor 20 to the standby address decoder 21, the standby address decoder 21 decodes the address signal to obtain the address and obtains the chip select. The signal is sent to the standby tracking bus right arbitration circuit 22.
Output to

Since the arbitration right management circuit 17 manages the bus right of the standby tracking bus 202 as described above, the standby tracking bus right arbitration circuit 22
The arbitration right management circuit 17 determines whether the bus right of the standby tracking bus 202 exists based on the flag indicating the presence of the bus right of the standby tracking bus 202.

If the bus right of the standby tracking bus 202 exists, the standby buffer memory control circuit 23 is notified of the self-diagnosis mode. When notified of the self-diagnosis mode by the standby tracking bus right arbitration circuit 22, the standby buffer memory control circuit 23 closes the standby bus buffer 25 and opens the standby bus buffer 24. To

As a result, the standby processor 20 is connected to the standby main bus 201 and the standby tracking bus 202.
, Self-diagnosis data can be written and read to and from the shared memory 26, and as a result, the self-diagnosis of the shared memory 26 can be performed.

Therefore, according to the standby redundant system of the present embodiment, the standby tracking bus right arbitration circuit 22 determines the standby system based on the flag indicating the existence of the bus right of the standby tracking bus 202 of the arbitration right management circuit 17. Since it is possible to determine whether or not the bus right of the tracking bus 202 exists, the self-diagnosis time can be reduced as compared with the standby redundancy system of the above-described first embodiment.

[0071]

As described above in detail, according to the present invention,
It is possible to provide a standby redundant system capable of shortening the tracking access cycle and reducing the tracking load. In addition, self-diagnosis of the standby shared memory can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a standby redundant system according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a standby redundant system according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a standby redundant system according to the second embodiment.

FIG. 4 is a diagram showing a configuration of a conventional standby redundant system.

[Explanation of symbols]

 Reference numeral 10: active processor, 11: active address decoder, 12: active tracking bus right arbitration circuit, 13: buffer memory control circuit, 14: bus buffer, 15: bus buffer, 16: shared memory, 17: arbitration right management Circuits: 20 Standby processor, 21 Standby address decoder, 22 Tracking bus arbitration circuit, 23 Standby buffer memory control circuit, 24 Bus buffer, 25 Bus buffer, 26 Shared memory, 31 ... Tracking bus right arbitration circuit, 101: active system main bus, 102: active system tracking bus, 201: active system main bus, 202: active system tracking bus, 301: bus between active system and standby system.

Claims (2)

[Claims] 1. A tracking bus connected to a standby system,
A standby shared memory for storing the active control information, and arbitrating the bus right of the active tracking bus and the bus right of the standby tracking bus, and the bus right of the active tracking bus and Bus right management means for centrally managing the existence of the bus right of the standby tracking bus; and the bus right management means obtains the bus right of the active tracking bus and the bus right of the standby tracking bus. And a control information writing means for writing the control information of the operating system to the shared memory of the standby system when the standby system is used. 2. A tracking bus connected to a standby system,
A standby shared memory that stores the control information of the active system; a bus right management unit that manages the presence of the bus right of the active tracking bus and the bus right of the standby tracking bus; Arbitration means for arbitrating the tracking bus of the standby system when it is indicated that the bus right of the tracking bus of the standby system exists, and the arbitration means of the standby system arbitrated by the arbitration means. Self-diagnosis means for performing self-diagnosis of the shared memory of the standby system via a tracking bus.