JP3019336B2 - Microprocessor development support equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a microprocessor development support apparatus, and can easily perform error processing of a target system, particularly, debugging of a target system when a microprocessor itself becomes abnormal. The present invention relates to a microprocessor development support device that can be used.

[Conventional technology]

Conventionally, a microprocessor development support device has provided emulation of a target system and its debugging function. The interface with the target system also has a function equivalent to the original function of the microprocessor as much as possible as the emulation of the microprocessor. Therefore, debugging of the target system can be performed with the same interface as that of the original microprocessor. However, recent trends in target systems include incorporating measures to improve reliability, or the microprocessor itself, for example, operating multiple microprocessors simultaneously,
It has a function of mutually detecting and processing an abnormality (hereinafter, referred to as an abnormality processing function). For this reason, it is necessary to perform this kind of debugging using a microprocessor development support device. In particular, in order to generate a state in which the microprocessor has failed, the target system itself is caused to simulate the failure of the microprocessor. A new circuit must be added for debugging. This example will be described with reference to FIGS. 3 and 4. FIG. 3 shows an example of a target system to be debugged this time, and it is expected that systems of this kind with improved reliability will increase in the future. Control signals and the like output from the microprocessor are omitted for convenience of explanation. FIG. 4 is a block diagram showing only a target interface portion of the conventional microprocessor development support device. The actual microprocessor development support device further includes a mapping circuit, an internal alternative memory, a break circuit, a trace circuit, and the like.

The target system shown in FIG. 3 is a normal mode microprocessor (hereinafter referred to as an NCPU) 25 for performing a normal operation.
Internally executes a command in exactly the same way, but reads the output signals of the NCPU 25 (for example, the address, output data, and control signals of the NCPU 25) internally, and compares them with the internally generated data. 26, target address (hereinafter, referred to as T address) 4, target data (hereinafter, referred to as T data) 21,
And a control circuit 29 that detects that the NCPU 25 and the CCPU 26 are out of synchronization via the memory 27 and the I / O 28, and performs subsequent control via the abnormality processing signal 30.

When the target system shown in FIG. 3 is operating normally, the operation is exactly the same as the case of a single microprocessor. However, for example, if the NCPU 25 falls into some abnormal state, the CCPU 26
A mismatch is detected by comparing the output signals of PU25 and the NCPU
25 or an error processing signal 30
To the control circuit 29 using At this time, the control circuit 29 recognizes that an abnormality has occurred in the system, and
To stop the operation of this system, retain necessary information, and notify the user of the occurrence of an abnormality.

FIG. 4 is a block diagram in which only the target interface portion of the conventional microprocessor development support device is extracted. The left side of the broken line shows the inside of the microprocessor development support device, and the right side shows a cable between the microprocessor and the target system. The microprocessor 1 outputs the address 3 to the target system as the T address 4 via the address buffer 2. In addition, the data 20 is output to the target system as T data 21 via the data buffer 19, or the T data 21 is input as data 20 via the data buffer 19. Further, a read signal (hereinafter referred to as ▲) 13, a write signal (hereinafter referred to as ▼) 14, a memory request signal (hereinafter referred to as ▲)
▼) 15, interrupt signal (hereinafter called INT) 1
6. An initialization signal (hereinafter, referred to as RESET) 17 and a clock signal (hereinafter, referred to as CLK) 18 are input / output to / from the target system via buffers. The above-mentioned various buffers require detailed control in accordance with their respective operations, but their description is omitted in the present invention. Microprocessor 1
Performs emulation of the target system using the above address, data and control signals. The microprocessor 1 operates in synchronization with CLK18 which is one of the control signals, and is initialized when RESET17 becomes active.
Becomes active and enters interrupt operation. To read and write data from the memory, activate the T address 4 and ▲ ▼ 15.
By making を 13 or ▼ 14 active, the T data 21 can be read as data 20 or the data 20 can be written as T data 21 to the memory of the target system. The execution is interrupted by using the break function or trace function not shown in this figure.
The execution history can be checked and debugging can be performed. However, if debugging of the target system as shown in FIG. 3 when an error occurs is attempted with a microprocessor development support device as shown in FIG. 4, an error generating mechanism is incorporated in the target system. You must debug the error handling function. In particular, generating an abnormality at a specific timing requires a large-scale circuit to be incorporated in a target system, which poses a serious problem in practical use.

[Problems to be solved by the invention]

As is clear from the above description, when the target system itself receives an error handling function, and especially when using the microprocessor development support device to perform debugging including the function when an error occurs in the microprocessor itself, In the microprocessor development support device of this type, it is necessary to take measures such as providing a function to generate an error necessary for debugging on the target system, and debugging cannot be performed with a target system having only the original function. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor development support apparatus capable of easily performing debugging when a microprocessor becomes abnormal without incorporating an abnormality generating function in a target system.

[Means for solving the problem]

A microprocessor development support apparatus according to the present invention includes a normal mode microprocessor that normally operates in response to supplied addresses and data, and operates in response to supplied addresses and data similarly to the normal mode microprocessor. A monitoring mode microprocessor that receives an output signal from the normal mode microprocessor, compares the output signal with an internally generated output signal and outputs an abnormality processing signal, and the monitoring mode microprocessor includes: A comparison circuit for comparing the set address with the address output from the monitoring mode processor, and when the addresses match, the data supplied to the monitoring mode processor to generate the abnormality processing signal. The normal mode micropro Characterized in that it comprises a circuit for differentiating the data supplied to Tsu service.

[Action]

In the microprocessor development support device configured as described above, the input signal from the target system becomes a value specified during the period specified by the user and is taken into the microprocessor. Therefore, the target
It becomes possible for the microprocessor to take an abnormal state from the viewpoint of the system. Therefore, an abnormal state of the microprocessor with respect to the target system can be easily generated at the designated timing, and debugging when the microprocessor becomes abnormal can be easily executed.

〔Example〕

Hereinafter, an embodiment of a debugging microprocessor according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of a microprocessor development support device according to the present invention. The basic configuration and operation are the same as those of the conventional microprocessor development support device of FIG.
In the microprocessor development support device of FIG. 1, the microprocessor 1 stores an address 3 in an address buffer 2
, Is output to the target system at the same time as the T address 4, and is also output to the comparator 5, and is compared with an address (hereinafter, referred to as an S address) 6 set by the user in advance. If they match, the match signal 12 is set to high level. The coincidence signal 12 is one input of an exclusive OR gate (hereinafter, referred to as EOR) 7. As for the data bus, only bit 0 of the data bus is particularly described, and the other data buses are omitted. Bit 0 of the data bus of this microprocessor (hereinafter referred to as bit 0)
M data bit 10 is bit 0 (hereinafter referred to as T) of the data bus of the target system via buffer 9 which becomes active when デ ー タ ▼ 14 is active.
(Referred to as data bits) to the target system. When ▲ ▼ 13 is active,
T data bits 11 from the system are input to the microprocessor via the EOR 7 and the buffer 8 which is then active. In addition, ▲ ▼ 13, ▲ ▼ 14,
▲ ▼ 15, INT16, RESET17, CLK18 are respectively input / output to / from the target system via buffers.
The microprocessor 1 executes emulation of the target system by using the above address, data, and control signals, and suspends execution and checks execution history by using a break function or a trace function not shown in FIG. And perform debugging. That is, the main difference between the microprocessor development support apparatus of FIG. 1 and the microprocessor development support apparatus of FIG. 4 is that when the memory is read from the target system, for example, if the address 3 is changed to the S address by the comparator 5. If it matches 6, the match signal 12 goes high, so that the T data bit 11
This is a point that the microprocessor 1 reads the inverted M data bits 10 via the EOR7.

The microprocessor development support device configured as described above operates as follows. First, this microprocessor development support device is connected to the microprocessor socket of the target system in place of the MCPU 25 on the target system shown in FIG. 3, and debugging is performed. CCPU
26 is in the monitoring mode, where the NCPU 25, that is, the address, data or control signal output from the microprocessor development support device, is compared with the internally generated state, and if a mismatch occurs, the target system transitions to abnormal processing. It is necessary to debug including this function. During the emulation of the microprocessor 1, a match signal normally output from the comparator 5
Since 12 is at low level, it operates in the same manner as described in FIG.

Here, an abnormal state (here, the T data bit 11 is inverted at the time of the input operation) so that the user can debug the abnormal processing function before the emulation starts.
Is set as the S address 6.
When the address 3 matches the S address 6 after the emulation starts, the comparator 5 outputs the match signal 12 as an abnormality occurrence signal.
To a high level. When the match signal 12 goes high
M data bit 10 which is the output of EOR7 is T data bit 11
Is the inverted signal of For this reason, the microprocessor reads abnormal instructions or data different from the normal contents, and an abnormal state occurs, so that this kind of debugging can be easily performed. That is, in this example, the read data becomes abnormal in the bus cycle of a specific address, and when viewed from the target system side, debugging when the normal mode microprocessor becomes abnormal can be easily performed. . In the above example, 1
Although an abnormal state occurs only in one bus cycle, an abnormal state occurs in a plurality of bus cycles if the address range can be specified by the comparator. Furthermore, since this comparator can use the function of the break circuit normally included in the microprocessor development support device, it can be realized by adding a small function to the function of the conventional microprocessor development support device. It is.

FIG. 2 is a block diagram of a second embodiment of the microprocessor development support device according to the present invention. The basic configuration and operation are the same as those of the microprocessor development support device of FIG. The INT 16 shown in FIG. 2 is connected to the microprocessor 1 through an AND gate (hereinafter referred to as AND) 23.
Is input as a microprocessor INT (hereinafter, referred to as MINT) 24. When the switch 22 is off, one input of the AND 23 is at a high level, so that INT16 and MINT24 are the same. When the switch 22 is turned on, one input of the AND 23 becomes low level, so this becomes an abnormality occurrence signal and the INT 16
MINT24 remains at the low level (inactive) regardless of whether or not is at the high level (active) or low level (inactive). In other words, when the user turns on the switch during emulation, MINT
Since 24 becomes abnormal (low level fixed), no interrupt can be input. Therefore, the target
It is possible to realize debugging when the system is in an abnormal state.

〔The invention's effect〕

As described above, a signal input from the target system to the microprocessor development support device is intentionally input to the microprocessor at a timing designated by the user in a state different from the normal state, thereby causing an abnormality in the target system. Debugging in the state can be easily realized.

[Brief description of the drawings]

FIG. 1 is a block diagram relating to an interface of a first microprocessor development support device according to the present invention with a target system, and FIG. 2 is an interface with a target system of a second microprocessor development support device according to the present invention. The block diagram for FIG.
FIG. 4 is a block diagram of a target system capable of detecting an abnormal state, and FIG. 4 is a block diagram relating to an interface of the conventional microprocessor development support device with the target system. 1... Microprocessor, 2... Address buffer,
3 ... address, 4 ... target address, 5 ... comparator, 6 ... setting address, 7 ... exclusive OR gate, 8 ... buffer, 9 ... buffer, 10 ... microprocessor data bus Bits 0, 11 of the target system data bus bits 0, 12, ... match signal, 13
... read signal, 14 ... write signal, 15 ... memory request signal, 16 ... interrupt signal, 17 ... initialization signal, 18
…… Clock signal, 19 …… Data buffer, 20 …… Data, 21 …… Target data, 22 …… Switch, 23 ……
AND gate, 24 ... Microprocessor INT, 25 ...
Normal mode microprocessor, 26 Monitor mode microprocessor, 27 Memory, 28 I / O, 29 Control circuit, 30 Abnormal processing signal

Claims (1)

(57) [Claims] 1. A normal mode microprocessor which normally operates in response to supplied addresses and data, and said normal mode microprocessor which operates in response to supplied addresses and data similarly to said normal mode microprocessor And a monitoring mode microprocessor that receives an output signal from the CPU and outputs an abnormality processing signal by comparing the output signal with an internally generated output signal, wherein the monitoring mode microprocessor has a set address. And a comparison circuit for comparing the address output from the monitoring mode processor with the normal mode microprocessor. Different from the data supplied to A microprocessor development support device, comprising: