JPH01258054A - Access control system for storage device - Google Patents

Abstract

PURPOSE:To prevent the generation of malfunction by controlling whether an address parity is to be inverted or not in accordance with the decoded result of an extended address. CONSTITUTION:A storage device 5 not including a storage part to be accessed by an extended address is provided with an extended address decoder 7 and the decoder 7 decodes an extended address on an address bus 4, controls an address parity on the bus 4 as a parity error, adds the address parity to a parity check part 6, and when the extended address is applied to the device 5, controls the extended address so as to detect an address error. When the number of extended address bits '1' is an even number, the decoder 7 inversionally outputs an address bus parity, and at the time of an odd number, the address bus parity is outputted as it is. Thereby, a parity error is generated and the error is detected as an address error by the check part 6, so that the access of the device 5 based upon the extended address can be inhibited and the generation of malfunction can be prevented.

Description

[Detailed Description of the Invention] [Summary] Regarding an access control method for a storage device in which a central control unit that can access a large-capacity storage device accesses an installed small-capacity storage device, it is possible to access an unimplemented storage device for some reason. The purpose of this is to enable detection as an address error when an extended address that accesses an address is added to a storage device. In an access control method of a storage device, an address bus parity generated based on an address is sent to an address bus, and a parity check section of the storage device detects whether or not there is an address error on the address bus. An extended address decoder is provided in a storage device in which a storage unit to be accessed is not implemented, and the extended address decoder decodes the extended address on the address bus so that the address bus parity on the address bus becomes a parity error. In addition to the above-mentioned parity check section, control is provided so that an address error is detected when an extended address is added to a storage device in which a storage section accessed by an extended address is not implemented.

[Industrial application field]

The present invention relates to an access control method for a storage device in which a small-capacity storage device mounted thereon is accessed by a central control unit that can access a large-capacity storage device.

In consideration of future system expansion, a system may be constructed using a central control unit configured to output an address that allows access to a large-capacity storage device. for example,
Although the number of subscribers currently accommodated by electronic exchanges is small,
If there is a plan to increase the number of subscribers in the future, a central control unit that can access a storage device with a storage capacity corresponding to the maximum number of subscribers will be configured. In such a system, until it is expanded, only a small capacity storage device is required and there is no need to use the extended address, but if for some reason the extended address is sent to the address bus. , it is necessary that there is no malfunction.

[Conventional technology]

In a system in which a central control unit and a storage device are connected via a bus to perform various information processing, a parity check is performed to detect errors in addresses used to access the storage device from the central control unit. For example, as shown in FIG. 5, the address generator 32 of the central control unit 31 generates an address for the storage device 35, the address bus parity generator 33 generates address bus parity, and the address bus 34 generates an address. and the storage device 35
In this case, the parity check section 36 checks the parity of the address and detects the presence or absence of an address error.

When an address error is detected, the storage device 35 invalidates the address and does not read or write data.
There are systems that notify the number 1 and systems that do not respond.

There is also a system in which the address bit width from the address generation unit 32 of the central control unit 31 is increased in consideration of future expandability, and the address bus 34 is configured accordingly. There is a configuration in which only the storage capacity required for the system is installed, and a configuration in which the storage capacity scheduled to be used in the expansion system is installed in advance.

Furthermore, with advances in semiconductor technology, the storage device 35 including the parity check section 36 is generally integrated into an integrated circuit, and therefore it is easy to increase the storage capacity.

[Problem to be solved by the invention]

In the case of a configuration in which the address bit width from the address generation unit 32 of the central control unit 31 is increased and a storage device with a storage capacity that can be accessed with that address bit width is installed in advance before system expansion, the unused storage capacity can be reserved in advance. Since it is something to be implemented, it is less economical. Therefore,
An economical configuration can be achieved by implementing only the memory capacity that is actually used and adding additional units when expanding the system.

In that case, the address bit width for accessing the actually implemented storage device is smaller than the address bit width from the address generation unit 32, and the parity check unit 36 Since the configuration performs a parity check on the number, for some reason the extended address, that is, the address generator 3
If the bits higher than the address of the storage device are used in the address from 2, address bus parity is generated by the address bus parity generation unit 33 based on that address, so the extended address bit "1" If the number is even, the parity check unit 36 will not detect an address error, but if the number is odd, the address error will be detected. If the storage device is accessed and data is read using an address other than the extended address bit, the central control unit 31 will malfunction because the data is not read using the correct address. Furthermore, when writing data, the data will be written to an incorrect address and the previously written data will be destroyed.

Therefore, before system expansion, it is sufficient to provide an address generator 32 with an address bit width compatible with a small-scale system and an address bus parity generator 33, but the central controller 31 may also be integrated into an integrated circuit. Because of this, it is impossible to replace the configuration with one that corresponds to the storage capacity scale of the storage device 35, and replacement is not based on system expansion.

An object of the present invention is to enable detection as an address error when an extended address accessing an unimplemented storage section is added to a storage device for some reason.

[Means to solve the problem]

The access control method for a storage device according to the present invention controls whether or not to invert address bus parity in accordance with the decoding result of an extended address, and will be explained below with reference to FIG.

The address including the extended address from the address generation unit 2 of the central control unit 1 and the address bus parity generated based on the address by the address bus parity generation unit 3 are sent to the address bus 4, and the parity of the storage device 5 is checked. In the access control method for a storage device in which the presence or absence of an address error on the address bus 4 is detected by the unit 6, an extended address decoder 7 is provided in the storage device 5 in which a storage unit accessed by an extended address is not mounted. The extended address on the address bus 4 is decoded by the extended address decoder 7, the address bus parity on the address bus 4 is controlled so that a parity error occurs, and this address bus parity is added to the parity checker 6. Control is performed so that an address error is detected when an extended address is added to a storage device 5 whose storage unit is not yet accessed.

[Effect]

The extended address decoder 7 decodes the extended address bit “1”.
If the extended address bit "1" is an even number, the address bus parity is inverted and output, and if it is an odd number, the address bus parity is output as is.This causes a parity error. Since the parity check unit 6 detects this as an address error, it is possible to prohibit access to the storage device 5 using the extended address and prevent malfunctions.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of main parts of an embodiment of the present invention, and 11
1 is a central control unit, 12 is an address generation unit, 13 is an address bus parity generation unit, 14 is an address bus, 15 is a storage device, 16 is a parity check unit, 17 is an extended address decoder, 18 is a data transfer unit, and 19 is data bus,
20 is a control section, and 21 is a storage section.

Address generator 12 and address bus parity generator 1
3 is realized by functions using an arithmetic unit, an internal storage device, etc. (not shown) of the central control unit 11,
An m-bit address is sent from the address generator 12, and a 1-bit address bus parity p is sent from the address bus parity generator 13 based on this m-bit address. Furthermore, the storage unit 21 of the storage device 15 has the storage capacity before system expansion, and is therefore accessed with an n (n<m) bit address.

Address bus 14 has a width of (m+1) bits, and extended address decoder 17 has extended address bits (m-
n) and the address bus parity p, and outputs a pseudo address bus parity ps in which whether or not the address bus parity p is inverted is controlled depending on the decoding result when an extended address is used. The parity check unit 16 adds the n-bit address for accessing the storage unit 21 and the pseudo address bus parity ps from the extended address decoder 17, and adds the pseudo address bus parity ps to the parity check unit 16.
A parity check is performed on an n-bit address using s, and when an address error is detected due to a parity error, an error detection signal er is applied to the control unit 20.

The control unit 20 controls access to the storage unit 21, and when an n-bit address is added and an error detection signal er is applied from the parity check unit 16, the control unit 20 invalidates the address and prevents access to the storage unit 21. prohibit.

When the extended address is not used, the extended address decoder 17 outputs the address bus parity p directly as a pseudo address bus parity ps. in this case,
The address bus parity generation unit 13 of the central control unit 11 generates address bus parity based on the n-bit address, and the parity check unit 16 detects a parity error if there is no transfer error on the address bus 14. Since no error occurs, the error detection signal er is not output.

Therefore, the control unit 20 decodes the n-bit address to access the storage unit 21, and in the case of data reading, the read data is sent to the data bus 19 via the control unit 20, and the central control unit 11 data transfer unit 1
Transferred to 8. In the case of data writing, data is sent from the data transfer section 18 to the data bus 19, and is added to the storage section 21 via the control section 20 and written therein.

Upon completion of the access to the storage unit 21, an access completion signal is transferred from the control unit 20 to the central control unit 11 via the control bus, and the central control unit 11 moves on to the next process.

As mentioned above, the address bus parity generation unit 13 generates address bus parity p based on an m-bit address including an extended address, and when an extended address is used, it generates address bus parity p based on an n-bit address. Unlike address bus parity, it is affected by the extended address pattern. Furthermore, since the parity check section 16 of the storage device 15 performs a parity check based on an n-bit address, when an extended address is used, there are cases where it can be detected as a parity error and cases where it cannot be detected.

Therefore, in the extended address decoder 17, when "1" of the extended address pin l-(m-n) is an odd number, the address bus parity p is directly converted to the pseudo address bus parity p.
If the number is even, address bus parity p is inverted and output as pseudo address bus parity ps. In other words, if the number of "1"s in the extended address bits is an odd number, nB/
) It is necessary to invert the address bus parity generated from the address of When used,
The pseudo address bus parity ps is controlled so that a parity error occurs.

Therefore, when an extended address is used, the error detection signal er is output from the parity check section 16 and applied to the control section 20. As a result, the control unit 20
invalidates the n-bit address and prohibits access to the storage unit 21. Therefore, when an extended address that accesses a storage unit 21 that is not implemented is sent to the address bus 14, that access is prohibited, so erroneous data will not be read and data will not be written to an erroneous address. No more getting caught. In this case, the access end signal will not be transferred from the control unit 20 to the central control unit 11, and the central control unit 11 will execute exception processing etc. due to a timeout from the start of access to the storage device 15. .

FIG. 3 is a block diagram of an extended address decoder according to an embodiment of the present invention, in which 23 is an even number detection circuit for detecting whether 1" in the extended address bits is an even number, 24 is an OR circuit, and 25 is an AND circuit. The circuit 26 is an exclusive OR circuit.

When the extended address is not used, the extended address pins are all "O" and therefore the output signal of the AND circuit 25 is "0", so the pseudo address bus parity of the output signal of the exclusive OR circuit 26 is The address bus parity p is output as is.

Further, when an extended address is used, if the extended address bit "l" is an odd number, the output signal of the even number detection circuit 23 becomes "0", and the address bus parity p is directly transferred from the exclusive OR circuit 26 to the pseudo address. bus parity ps
is output as

If the extended address bit "l" is an even number, the output signal of the even number detection circuit 23 becomes "1", and the AND circuit 2
Since the output signal of No. 5 also becomes "1", the address bus parity p is inverted by the exclusive OR circuit 26 and output as the pseudo address bus parity ps.

FIG. 4 shows a specific logic circuit of the extended address decoder according to the embodiment of the present invention, showing the case where m-24 and n=22, 27 is an AND circuit, and 28 is an exclusive OR circuit.

m-bit address AOO~ from address generator 12
Address bus parity p is generated in the address bus parity generation unit 13 based on A23, and the address bus parity p is added to the exclusive OR circuit 28, and the address bus parity p of n pinto is added to the exclusive OR circuit 28.
Extended address bits A22 and A23 excluding O-A21
is added to the AND circuit 27.

This extended Ato1/Spit A22. When both bits of A23 are "1", the output signal of the AND circuit 27 becomes "1", and the exclusive OR circuit 28 inverts the address bus parity p to become the pseudo address bus parity ps.
Also, extended address bit A22. Either one of A23 is “
1", or both are "0" (when no extended address is used), the output signal of the AND circuit 27 is 0", so the address bus parity p is directly output as the pseudo address bus parity ps.

If the storage device with the configuration excluding the extended address decoder I7 is integrated circuit, that is, in the conventional configuration, by simply adding the extended address decoder 17 with a simple configuration, the small capacity before system expansion can be reduced. Error detection can be easily performed when an extended address is used. Also, by expanding the system
If a storage device that can be accessed by bit addresses is installed, the extended address decoder 17 will be removed.

〔Effect of the invention〕

As explained above, in the present invention, when a storage device accessed by an extended address is not implemented, the extended address decoder 7 is provided, and when the extended address is used, the address bus parity is inverted based on the decoding result. It is possible to detect this as a parity error in the parity check unit 6 by controlling whether or not the error occurs. Therefore, when an extended address that accesses an unimplemented storage device is sent for some reason, an address error is detected. It is possible to detect this as an error and prohibit access to the storage device
Malfunctions of the central control device 1 can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram of main parts of an embodiment of the present invention, FIG. 3 is a block diagram of an extended address decoder of an embodiment of the present invention, and FIG. 4 is a block diagram of an extended address decoder of an embodiment of the present invention. FIG. 5 is an explanatory diagram of a conventional example of the concrete logic circuit of the extended address decoder of the embodiment. 1 is a central control unit, 2 is an address generation section, 3 is an address bus parity generation section, 4 is an address bus, 5 is a storage device, 6 is a parity check section, and 7 is an extended address decoder.

Claims (1)

[Claims] An address including an extended address from an address generation unit (2) of a central control unit (1) and an address bus parity generated based on the address by an address bus parity generation unit (3). address bus (4) and storage device (5).
), in which a parity check unit (6) of a storage device detects the presence or absence of an address error on the address bus (4), wherein the storage unit accessed by the extended address is an unimplemented storage device. (5) is provided with an extended address decoder (7), and decodes the extended address on the address bus (4) with the extended address decoder (7) to open an address bus barrier on the address bus (4). The parity check section (
In addition to 6), access control of a storage device is characterized in that an address error is detected when an extended address is added to a storage device (5) in which a storage unit accessed by an extended address is not implemented. method.