JPS62245453A - Substituting method for alternative memory - Google Patents

Abstract

PURPOSE:To improve the reliability of a main storage device (MS) and an alternative memory function by checking the alternative memory function while substituting the MS with an alternative memory. CONSTITUTION:A 1-bit register 9 which holds the contents of data transmitted from a write register 5 to a memory chip 1 is arranged in parallel to a memory chip 1. Then when the contents of data read out of the MS are corrected and written in the alternative memory, the contents of its one bit are held in the register 9 and the address register 3a of the alternative memory side is not updated in a cycle wherein the address register 3b of the MS side is updated to read a next bit; and the written data is read out as it is and compared by a comparing circuit 10 with the contents held in the register 9 and when they coincide with each other,it is judged that the alternative memory function is in normal operation. The contents of the address register 3a are equalized to the contents of the address register 3b and the writing, reading, and comparison of the next bit are repeated. If the comparison result indicates dissident, the abnormality of the alternative memory function is reported to a CPU to interrupt the substitution of the alternative memory.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a replacement memory replacement method that is a measure against hard errors in main storage (hereinafter referred to as MS), etc., in which data written to the replacement memory is stored in a register. and before the address of the alternate memory is updated by a replacement operation, the contents of the alternate memory are read and compared with the write data, and if both data have the same contents, the next address is replaced, If the data is not the same, it is determined that there is a failure in the replacement memory function, and the replacement with the replacement memory is canceled, and the MS
While replacing the main memory and the spare memory, it is checked whether the spare memory function is operating normally, and prevents delays in access to the MS due to repeated unnecessary reading and writing. This invention discloses a technique for increasing the reliability of a replacement memory function.

[Industrial application field]

In order to maintain high reliability of the main memory (MS) of a data processing device, the present invention provides a memory chip separate from the memory chips constituting the MS, and replaces a chip that has a fixed failure in the MS. Regarding a replacement memory replacement method that prevents the occurrence of multi-bit errors in MS and reduces the failure rate,
In particular, the present invention relates to a replacement memory replacement method in which the replacement memory function is checked at the same time as replacement in order to maintain the reliability of the replacement function and replacement memory.

[Conventional technology]

Conventionally, a small-capacity memory chip is prepared separately from the memory chip that constitutes the MS as an alternate memory function.
When a fixed fault is discovered during MS patrol, etc., the memory contents of the chip are read out and an ECC (Error Ch.
After correcting the error using the error checking and correction function, it is temporarily replaced with a spare memory, and during that time countermeasure processing for the MS is carried out.The fixed failure of the MS expands into a multi-bit error, making countermeasures complicated and difficult. A method is used to try to terminate the process before it is done.

However, in the conventional spare memory function, when the spare bit position is indicated, the MS and the spare memory are simply replaced, and the spare memory function is not checked.

[Problem that the invention seeks to solve]

With conventional technology, it is not confirmed that the replacement memory function is operating normally, and even if it is not operating normally, reading and writing of addresses for the chip to be replaced are repeated, and during that time, the MS It is not possible to access the MS, and it is only when the MS is accessed after replacement that an abnormality in the spare memory function becomes apparent.

The present invention was devised in view of these problems, and it is possible to check whether the replacement memory function is operating normally while replacement is being performed, without delaying the replacement operation. , MS due to repeated useless reading and writing
An object of the present invention is to provide a replacement memory replacement method that prevents delays in access to the MS and improves the reliability of the MS and replacement memory functions.

[Means for solving problems]

In the present invention, the means for solving the above problems is as shown in the circuit configuration diagram for explaining the principle in FIG.
A memory chip 1 with a replacement memory function is provided separately from the memory chip 2 constituting the MS, and in the replacement memory function that replaces the memory contents of the memory chip 2 in which a fixed failure has occurred in the MS, the replacement memory function operates and the replacement memory This method is based on a method for replacing a spare memory, which is characterized by having a circuit configuration for checking the function, and checking the function of the spare memory to confirm whether or not the replacement is being performed normally.

[Effect]

As already mentioned, as a replacement memory replacement operation, C
When a fixed failure is discovered during PU MS patrol, etc.
The memory contents of all addresses of the chip including the fixed failure address are read out one word at a time, corrected by the ECC function, and then this data is written to the MS and the spare memory.This operation is repeated. The data to be written is stored separately in a register, and when the next word is read from the MS,
By reading the previous data from the spare memory and comparing it with the data from the register, it is possible to simultaneously check whether the spare memory function is functioning normally without delaying the replacement operation.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to examples and drawings.

Spare memory function check circuit (FIG. 1) FIG. 1 is a block diagram showing an example of a spare memory function check circuit that implements the replacement method according to the present invention. In FIG. 1, a memory chip 1 of the replacement memory is formed of a separate chip from a memory chip 2 constituting the MS, and each of these two memory chips is provided with an address register 3a and 3b. Chip WE (Write1
! nable) pin is under the control of the memory control circuit 4.

A write register 5 is connected to the write side of the MS,
A readout register 6 is connected to the readout side,
The data read into the read register 6 is correctly rewritten by the ECC function circuit 7 and then inputted into the write register 5 again. The write data from the write register 5 is also connected to the memory chip 1 via the selector 12 so that it is written not only to the memory chip 2 of the MS but also to the spare memory. When MS patrol is performed from the CPU unit and a 1-bit error is detected, the content indicating the bit position to be replaced is written to the replacement bit register 8 based on the syndrome information in the ECC function circuit 7, and the error is detected. MS
One word of data containing the memory contents of the chip is read into the read register 6, one bit error is corrected by the ECC function circuit 7, and the data is set in the write register 5, and the replacement bit position specified by the replacement pit register 8 is read out. Accordingly, the bit selected by the selector 12 is written from the write register 5 to the spare memory 1, and at the same time, the other bits are rewritten to the MS2. The address is stored in two address registers 3a and 3b.
As shown in , the address of the chip that causes the MS error is updated, and reading and writing of one word at a time are repeated. Also, selector 1 on the read side
3, the bit designated by the replacement pit register 8 in the 1-word data read from the MS 2 is replaced with 1-bit data read from the replacement memory 1 and supplied to the read register 6.

In such a replacement memory replacement circuit, the present invention arranges a 1-bit register 9 that holds the contents of data transmitted from the write register 5 to the memory chip 1 in parallel with the memory chip 1, and When correcting the read content and writing it to the replacement memory, the 1-bit content is held in the register 9, and the replacement is performed in the cycle in which the address 3b on the MS side is updated and the next bit is read. The address 3a on the memory side is not updated, the written data is read as is, and compared with the contents held in the register 9 using the comparator circuit 10. If they are the same, the alternate memory function is considered to be operating normally. Judgment, address 3a
Make the contents the same as the contents of MS address 3b, and add the following 1
Repeat writing, reading, and comparing bits. If the comparison results do not match, c) the CPU unit is notified of an abnormality in the spare memory function, and replacement with the spare memory is interrupted.

In addition, 11 in the figure is a check circuit to confirm that the data from the CPU is set in the spare pit register 8, and if the contents of the spare pit register 8 are not blank (all zeros), it will set "1". Output.

Function check timing (Figure 2) FIG. 2 is a time chart of the above operation.

The correspondence between each stage in FIG. 2 and each part in FIG. 1 is as follows. Note that the timing in the horizontal direction in the figure assumes that one section is divided into read or write periods for one word.

The 0th stage indicates the timing at which the replacement bit is specified from the replacement pit register 8.

The 0th stage is M updated by the address register 3b of the MS.
This is the address content of S.

The 0th stage indicates whether the MS access is read or write.

The 0th stage indicates a period in which the WE pins of the MS and the alternate memory are in the "enabled" state under the control of the memory control circuit 4.

The 0th stage is a flag for data to be written to the spare memory, and is 1
The flags held in bit register 9 are shown.

The 0th stage indicates a period in which updating of the address register 3a of the spare memory is suppressed by instructions from the spare pit register 8 and control from the memory control circuit 4.

The 0th stage is the address contents of the spare memory updated by the address register 3a of the spare memory.

The 0th stage is the Rea that accesses the spare memory for reading.
d) or write.

The 0th stage indicates a comparison operation period in the comparison circuit 10.

That is, as shown in the above time chart, first, in the first period, when data is read from the address "O" specified in the address register 3b of the MS, the address data "O" is stored in the spare memory. It is also registered in the address register 3a, and in the second period, the memory control circuit 4
The WE pin becomes "enabled" by the control from
Since the two memories enter the write mode, the data at address "01" is written to the specified position of the alternate bit register 8. Meanwhile, during this period, the address register 3a performs the check shown in FIG. If the signal from the circuit 11 is ``1'', the signal from the memory control circuit 4 is timingd by the E (C1ock enable) pin, and the address update is suppressed. Therefore, in the third period, the MS The side address register 3b is rewritten to the next address “1”, but the address register 3a of the spare memory remains at the “O” address.
While the data at the next 1” address is being read from S,
The data at the previous address "0" is read from the spare memory and compared with the data flag at the 0th stage by the comparison circuit 10. When normal return data returns to CPU'U,
The next fourth period starts without any problems, the address register 3a of the replacement memory is also updated to the address "1", and the WE pin becomes "enabled" under the control from the memory control circuit 4, as in the second period. , the two memories are in write mode, and the specified location of the replacement bit register 8 is written.
Data at address "1" from write register 5 is written. If normal return data is not returned to the CPU and there is an abnormality in the function, the replacement operation is immediately stopped.

In this way, the above device controls the timing of the address register 3a of the spare memory from the memory control device 4 and compares the data flag held in the 1-bit register 9 with the data from the spare memory. , the normality of the replacement memory function can be confirmed during the replacement operation.

〔Effect of the invention〕

As described above, according to the present invention, the spare memory function is checked while the MS is being replaced to the spare memory. There is no need to repeat replacement, prevent delays in accessing the MS due to repeated unnecessary reads and writes, avoid expansion into multi-bit errors, and
It is possible to provide a replacement memory replacement method that can improve the reliability of the & replacement memory function. Note that the present invention refers to M in a narrow sense.
Needless to say, the present invention is not limited to S, but can be applied to any storage device that employs replacement memory.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram for explaining the present invention in detail and showing an embodiment of an alternate memory function check circuit according to the present invention, and FIG. 2 is a time chart of the embodiment. 1; Ms memory chip, 2; Memory chip of alternate memory, 3a; Address register of alternate memory, 3b; Address register of main memory, 4; Memory control circuit, 5; Register for writing to main memory, 6; Main memory reading register, 7 HEcca function circuit, 8; alternate bit instruction register, 9; 1-bit register that holds data to be written to alternate memory, lO: comparison circuit, 11; check circuit, 12.13: selector. W E ; write enable of the present invention:! l
117-a function check with k irrational person! 7 circuits of Issou Ryoi 1 is not shown, it is a circular movement, it is not shown.

Claims (1)

[Claims] In a replacement memory replacement method that includes a memory chip (1) with a replacement memory function separately from a memory chip (2) constituting a storage device, and replaces the memory contents of a chip in which a fixed failure has occurred in the storage device, the replacement operation is performed. A replacement memory replacement method characterized in that, at the same time, a replacement memory function is checked to confirm whether or not replacement is being performed normally.