JPH01309159A - Multi-port memory - Google Patents

Abstract

PURPOSE:To enable a memory itself to avoid its working defects caused at collision of write addresses by invalidating the write requests to some or all ports having coincidence of addresses and therefore preventing the writing collision to the same address. CONSTITUTION:An address coincidence detecting circuit 11 checks the coincidence of write addresses among ports. When the coincident addresses are detected, a warning signal generating circuit 12 gives the information to the outside of a memory by means of a warning signal Alarm to show the detection of the coincident addresses. At the same time, a write request invalidating circuit 13 stops the relevant writing action. These circuits 11-13 have the simple constitutions and can be set into a chip which contains a memory cell array 16. Thus it is not required to suppress the external writing actions to the same address via the software or the hardware. In addition, such problems like the circuit/wiring spaces, etc., can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] The present invention relates to a multi-port memory having a plurality of writable ports.

To prevent malfunctions when the write addresses of each port collide,
The purpose is to provide a means to prevent this with internal memory functions.

An address match detection circuit that compares two write address signals input to each port and generates a detection signal when a loss is detected, and a warning of a write address loss to the outside of the memory cell based on the above detection signal. and a write request invalidation circuit that invalidates write requests to some or all ports with matching addresses, and is configured to prevent collisions of writes to the same address.

[Industrial application field]

The present invention relates to a multi-port memory having a plurality of writable ports used for, for example, internal storage of a CPU or shared storage of a multiprocessor system.

In recent years, with the development of various computer technologies, pipeline control and multiprocessor processing have come to be performed even on relatively small-scale computers.

In all of these processes, since a plurality of processes are in progress at the same time, it is inevitable that a conflict of simultaneous access requests to a shared storage device will occur.

A solution used in such cases is the use of multi-board memory.

Multi-board memory can be read/written by specifying different addresses from 7 ports at the same time.
It is actually used for internal storage of CPUs, shared storage of multiprocessor systems, etc. However, this multi-board memory also has problems. If write operations are performed to the same address at the same time, the contents of the memory are not guaranteed, and in the worst case, the memory itself may be destroyed.

At present, external hardware or software is used to deal with this problem, but this imposes a burden on processing time, circuit/wiring space, etc., and an effective solution to this problem is required.

[Prior Art] FIG. 7 shows a block diagram of a two-point static RAM as an example of a conventional multi-board memory. For convenience,
Here, we will call the two ports A port and B port, respectively.

In FIG. 7, 16 is a memory cell array, 17A is an A
How many output amplifiers, 17B is B individual output amplifier, 20A is A boat side address register, 20B is B boat side address register, 21A is A port side column decoder, 21B
22A is a column decoder on the B port side, 22A is a row decoder on the A port side, 22B is a row decoder on the B port side, and 23 is a clock sofa.

A memory cell for one bit (assuming CMO3) in the memory cell array 16 is configured by, for example, a circuit as shown in the eighth section.

FIG. 9 shows a timing chart of typical input/output signals of the memory shown in FIG. The operation of the memory shown in FIG. 7 will be explained according to the timing chart shown in FIG. 9.

The black tsuk is common to both boats and is designated CLK. A port address signal ADAn.

The address signal ADBn of the B port is used for both reading and writing. Then, the read operation is performed while the clock CLK is High, and the clock CLK is Low.
A write operation is performed during the period.

XWEA and XWEB are write enable signals for each port, and when these signals are Lo-, a write operation is performed. DIN-A and DIN-B are data signals on the A port side and the B boat side, respectively.

In the 17th phase shown in FIG. 9, the A-boat side reads the contents of the address ■, and the B-port side reads the contents of the address ■. XWEA, XWEB are Il
Since it is high, no writing is performed.

In the second phase (phase 2), the A port side reads the contents of the address ■ and then writes data ■ to the address ■, and the B port side reads the contents of the address ■ and does not write.

In the third phase (phase 3), the A boat side reads the contents of the address ■ and does not write.

After reading the contents of address ■, the B port side writes data [phase] to address ■.

In the fourth phase (phase 4), the A port side writes data 0 to the address ■ after reading the contents of the address ■, and the B port side writes data @ to the address ■ after reading the contents of the address ■. Write.

As in the fourth phase, when writing simultaneously.

When the same address is specified, WW LA (Write Word L
ine A) and WW L B (Write Wo
rd Line B) became the old GH, and WG
A (Write Gate A) and W G B
(WriteGate B) are open. At this time, if the write data from one boat is different, the launch will not be stable, and as a result, the memory contents will become unstable, or in the worst case, the two will be damaged by the through current. , memory cells are destroyed.

In order to avoid such inconveniences, it is necessary to check address coincidence outside the memory before sending an address signal to the memory, and in some cases, it is necessary to suppress the write operation. In order to do this, conventionally, a lot of burden has been placed on processing time, circuit/wiring space, etc.

[Problem to be solved by the invention]

As described above, conventionally, when using multi-port memory, it is necessary to prevent malfunctions caused by simultaneous writing to the same address from multiple ports.

Some kind of software or hardware countermeasure was required, which was burdensome in many ways.

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned problems and provides a means for preventing malfunctions caused by a conflict between write addresses of respective ports using functions within the memory.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, 11 is an address match detection circuit, 12 is a warning signal generation circuit, and 13 is a write request invalidation circuit.

14 is a clock buffer, 15 is an address decoder for decoding addresses, and 16 is a memory cell array in which memory cells are arranged according to addresses.

Reference numeral 17 represents an input/output amplifier that inputs and outputs data.

The address match detection circuit 11 checks whether the write addresses match between each port, and if there is a matching address, the warning signal generation circuit 12 notifies the outside of the memory using a warning signal Alarm to notify that fact. At the same time, the write request invalidation circuit 13 stops the write operation that is problematic.

[Effect]

Address match detection circuit 11. Since the warning signal generation circuit 12 and the write request invalidation circuit 13 can be configured with simple circuits, they can be incorporated into a chip in which the memory cell array 16 is provided, using software or hardware.

There is no need to externally suppress old addresses for the same address, and problems such as circuit/wiring space are also solved.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an example of an address match detection circuit according to an embodiment of the present invention, and FIG. 4 is an example of a warning signal generation circuit according to an embodiment of the present invention. , FIG. 5 shows an example of a write request invalidation circuit according to an embodiment of the present invention, and FIG. 6 shows a timing chart according to an embodiment of the present invention.

FIG. 2 shows an example in which the present invention is applied to a two-port static RAM similar to the conventional example shown in FIG. It is similarly applicable to other types of multiport memories.

The address match detection circuit 11 shown in FIG. 2 is constituted by a circuit as shown in FIG.

ADAn is address input from A boat, ADBn is B
This is address input from the boat. Each of these address inputs is passed through an exclusive OR circuit XOR, and when the outputs are all 0, the address-number configuration signal C is set to Hi (Hh) by the NOR circuit NOR.

The warning signal generating circuit 12 shown in FIG. 2 is constituted by a circuit as shown in FIG.

XWEA is the A boat measurement possible signal, XWEB is the B boat
CLK is a clock, C is an address-number output signal output from the address match detection circuit 11, and Alarm is a write address match warning signal. XWEA, XWEB, CLK are all LO-
When the address-number output signal C is the old gh, the write address match warning signal Alarm becomes the old gh.

The write request invalidation circuit 13 shown in FIG.

It is composed of a circuit as shown in FIG.

XWEA is a signal that can be written to port A, and XWEB is a signal that can be written to port B.
The port example write enable signal Alarm is a write address match warning signal output from the warning signal generation circuit 12. XWEC is an internal write enable signal on the A port side, and XWED is an internal write enable signal on the B port side.

In FIG. 2, address signals input from both boats A and 8 are applied to address registers 2OA and 20B, respectively.
is maintained. The outputs of address registers 2OA and 20B are 1 column decoders 21A and 21B and row decoders 22A and 2
2B and the address match detection circuit 11.

In the address match detection circuit 11, the addresses of both ports A and 8 are compared, and if a match is found, the output is t(
Become intense. In this embodiment, there is no particular distinction between read and write addresses.

Even if there is no write conflict, if the address fails, the output of the address match detection circuit 11 becomes High.

In the timing chart shown in FIG.

The second phase (phase2) and the fourth phase (pha
se4) corresponds to this, and at this time, the A word C is Hi.
It's gh.

In the warning signal generation circuit 12, the address match detection circuit 1
Based on the output of 1, a warning signal is generated. This signal indicates that the addresses of both ports A and 8 have failed, and the write signals of both ports 5 and 5 are low.

That is, it becomes the old gh only when a write operation is specified and the clock is low, that is, at the write timing. Taking FIG. 6 as an example, this corresponds to the fourth phase (phase 4). The warning signal Alarm becomes the old gh, and a warning is issued to the outside via a terminal or the like.

The write request invalidation circuit 13 is a warning signal generation circuit 12.
Based on the output signal of , the write enable signal of the boat to be inhibited from being written is set to High.

Fixed to no writing. Taking FIG. 6 as an example, the signal XWED in the fourth phase (phase 4)
corresponds to this.

In this embodiment, the circuit shown in FIG. 5 does not invalidate the write enable signal of the A port even if the addresses match, but only invalidates the write enable signal of the B port. That is, the external circuit using the A boat is configured to be able to perform processing with top priority regardless of the operation of the external circuit using other boats. Of course 1
It is also possible to disable the write enable signals of both boats.

Considering actual usage examples, even though it is a multiprocessor system, there are often large differences in the importance and speed requirements of processing, such as the central processing unit (CPU) and input/output processing unit (IOP). In such a case, a considerable performance improvement can be expected by giving top priority to the CPU with the highest processing density.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to avoid malfunctions caused by write address collisions by the memory itself, which improves system reliability, simplifies design, and improves processing speed. You can expect it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram of an embodiment of the present invention. FIG. 3 is an example of an address match detection circuit according to an embodiment of the present invention. FIG. 4 is an example of a warning signal generation circuit according to an embodiment of the present invention. FIG. 5 is an example of a write request invalidation circuit according to an embodiment of the present invention. FIG. 6 is a timing chart according to an embodiment of the present invention. Figure 7 is an example of a conventional multi-board memory. Figure 8 shows an example of a memory cell for one bit. FIG. 9 shows a timing chart of typical input/output signals in the conventional example. In the figure, 11 is an address match detection circuit, 12 is a warning signal generation circuit, and 13 is a write request invalidation circuit. 14 is a clock buffer, 15 is an address decoder, 1
6 represents a memory cell array, and 17 represents an input/output amplifier.

Claims (1)

[Claims] In a multi-port memory having a plurality of writable ports, an address match detection circuit (11) that compares write address signals input to each port with each other and generates a detection signal when a match is detected. , a warning signal generating circuit (12) that warns the outside of the memory cell of a write address match based on the detection signal, and a write request disabling circuit (12) that disables a write request to some or all ports whose addresses match. 13
), and prevents writing conflicts to the same address.