JPS6252338B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing detection method, particularly to an address multiplexed RAM (RANDOM ACCESS).
This paper relates to a timing check method for storage devices using (MEMORY).

Generally, address multiplexed RAM supplies address signals and the like in a time-division manner. That is, in the address multiplexed RAM, column addresses and row addresses are supplied in a time-division manner during reading and writing, and a write instruction is subsequently supplied during writing.

For this purpose, the column addresses provided in a time-sharing manner,
To capture line addresses and write instructions
RAS (ROW ADDRESS STROBE) timing, CAS (COLUMN ADDRESS STROBE) timing, and WE (WRITE ENABLE) timing are used.

Therefore, since normal operation will not occur unless these timings are supplied, these timings are checked to detect whether or not the operation is normal.

Furthermore, storage devices used in information processing devices often consist of one control section and one storage element section within one storage device. Interlacing was often used to improve the data processing ability of information processing devices.

However, with the increase in the performance and capacity of semiconductor memory elements, multiple memory banks that can operate simultaneously within one memory device are constructed, and
4WAY and 8WAY interlacing is becoming possible. This tendency is particularly noticeable in large and ultra-large computer systems, and the improvement in data processing capacity is remarkable.

At present, address multiplexed dynamic RAM is commonly used as a memory element. This type of memory device divides the access address into two, a column address and a row address, in order to access one cell of the memory cell matrix.
It is set in the address register in the storage element at two timings: RAS timing and CMS timing. By doing this, the number of IC pins is reduced and the packaging density is improved. Therefore, when reading data from an element, it is necessary to
It is necessary to provide two timings to the element in a specified time relationship, and furthermore, in the case of writing, it is necessary to provide WE timing. In this way, the normal 3
However, as mentioned above, in large computer storage devices, the storage device is divided into 8 or 16 banks to enable interlacing, so a timing generation circuit is required for each bank. The number of timing generation circuits within the storage device increases.

The conventional timing check method performs a timing check on each of RAS timing, CAS timing, and WE timing independently.
When there is an error for each, an error signal is generated.

Below, regarding the conventional timing inspection method,
This will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an example of a conventional timing check system.

In the conventional example shown in FIG. 1, numerals 1 to 3 indicate a RAS timing generation circuit, a CAS timing generation circuit, and a WE timing generation circuit, respectively.

Their outputs are buffer gate circuits 4 to 6, respectively.
output signals 101-1 as shown in FIG.
03 is generated and sent to the storage element section.

Note that the signal waveform shown in Figure 2 is ECL
(EMITER COUPLED LOGIC) level, indicating high level logic '0' and low level logic '1'.

Complement side outputs 104-106 of buffer gate circuits 4-6 are sent to registers 7-9 and AND gate circuits 10-12. Complement side output 104~ sent to registers 7~9
106 is delayed by one clock. registers 7-9
Complement side outputs 107 to 109 are sent to AND gate circuits 10 to 12, and as shown in FIG. A WE timing check signal 112 is output from the AND gate circuit 12. These signals may or may not be output depending on the command, and the timing at which they are output differs depending on partial write or full write.

Therefore, a control signal for checking the timing is generated independently for each timing.

In FIG. 1, 16 is a request register;
17 is a command register, and 18 is a bank address register.

The request command sent to the storage device is decoded by the command decoder circuit 19 via paths 119 and 120, and the subsequent operation is determined. A path 122 indicates a read operation signal, a path 123 indicates a full write operation, a pass 124 indicates a partial write operation, and a pass 125 indicates a refresh operation signal. Each of these signals is sent to shift registers 20-23 and delayed until the timing at which the check is to be performed.

Further, the bank address is also sent to the shift register 24 via the path 121 and delayed until the check timing. In this example, reading
Timing is to be checked at 8T after receiving the request for full write or refresh, and at 12T for partial write. Each signal delayed by shift registers 20 to 24 is
At the 8th T, it is sent to each timing check control signal generation circuit via paths 126 to 129. R.A.S.
The timing check control signal (8T) 116 must be output at the time of reading, all writing, and refreshing. Inverter gate 25-2
7. A signal 135 that satisfies the above conditions is generated by a circuit consisting of paths 132 to 134 and a NAND gate 28.

CAS timing check control signal (8T) 11
7 needs to be output at the time of reading and at the time of all writing. This is created by a circuit consisting of inverter gates 25, 26, paths 132, 133, and NAND gate 29 (signal 136).

WE timing check control signal (8T) 118
must be output during all writes. This WE
The timing check control signal (8T) 118 is the output signal 127 of the shift register 21.

The above signals are distributed to the timing generation circuit of each bank, so bank address signal (8T) 128
and is sent to bank decoder circuits 30-32. Outputs 137-13 of bank decoder circuits 30-32
9 is a timing check control signal for the 8th T in each bank.

On the other hand, during partial writing, it is necessary to generate the RAS timing check control signal 116, CAS timing check control signal 117, and WE timing check control signal 118 at the 12th time. Partial write timing check control signal 140 is generated by partial write signal (12T) 130, bank address (12T) 131 and decoder circuit 33.
is generated. This partial write timing check control signal 140 is sent to the gate circuits 34 to 36, and is logically summed with each of the 8T timing check control signals already mentioned, to generate a RAS timing check control signal as shown in FIG. 116, CAS timing check control signal 11
7, becomes the WE timing check control signal 118. Each timing check signal and control signal is sent to exclusive OR circuits 13 to 15, and if one of the signals is not output as specified, a logic '0' signal is output to the output to indicate that an error has occurred in the timing. Become.

Although only one bank is shown in FIG. 1, as the number of banks increases, the number of bank decoder circuits 30 to 33, gate circuits 34 to 36, and exclusive OR circuits 13 to 15 increases.

Furthermore, an increase in the number of banks also increases the mounting space, and as a result of timing division and distribution, the amount of HW, the number of connection points, etc. increase, and failure of the check circuit itself may become a problem.

In other words, the conventional timing inspection method has the drawback of requiring a large amount of hardware.

An object of the present invention is to provide a timing inspection method that can reduce the amount of hardware.

That is, an object of the present invention is to improve the timing check circuit hardware by checking that all RAS, CAS, and WE timings are output only when a write command is issued in a multi-bank semiconductor memory device. An object of the present invention is to provide a timing check method that can reduce the amount of data.

The timing check method of the present invention is an address multiplex type
In a storage device using RAM, a RAS timing check signal generation circuit, a CAS timing check signal generation circuit, a WE timing check signal generation circuit, and a timing check control signal generation circuit that outputs only when a write command is issued are used to generate a signal when a write command is issued. said RAS timing;
It is configured to include a check circuit that checks whether all timings of CAS timing and WE timing are output.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing one embodiment of the present invention. FIG. 4 is a timing chart of signal waveforms at various parts of the embodiment shown in FIG.

The storage device to which RAS timing, CAS timing, and WE timing is supplied is composed of multiple banks that are clock synchronous and can be interleaved. Memory element is address multiplexed dynamic
It uses RAM.

51 is a dynamic RAM RAS timing generation circuit, 52 is a CAS timing generation circuit, 5
3 shows a WE timing generation circuit. The outputs are sent to buffer gate circuits 54 to 56, respectively.
It is sent to the storage element section through outputs 201, 202, and 203 as shown in the figure.

Note that the signal waveform shown in FIG. 4 is written at the ECL level, indicating H level logic '0' and L level logic '1', and is converted to the interface level of the memory element being used in the memory element section. shall be taken as a thing. Complement side outputs 204, 205, 206 of buffer gate circuits 54-56 are connected to registers 57, 58, 59 and AND gate circuit 60,
61 and 62. register 57,5
Each signal sent to 8 and 59 is delayed by 1T here. Complement side outputs of registers 57, 58, 59 are sent to AND gate circuits 60, 61, 62, which output trailing edge differential pulses of each timing signal as outputs 210, 211, 212 shown in FIG. These signals are input to the AND gate circuit 63 and are processed as timing check signals 213 for each bank.
Output.

On the other hand, requests, commands, and bank addresses sent to the storage device are set in a request register 65, a command register 66, and a bank address register 67, respectively. request,
The command is sent to the command decoder circuit 68 via paths 216 and 217, where the command is decoded. Here, unlike the conventional timing check, only the write command is checked, so only the full write signal 220 and the partial write signal 221 are required. These signals are sent to shift registers 70, 71 and delayed so that the necessary timing can be extracted.

Similarly, for the bank address, pass 2
18 to a shift register 69 and delayed. When writing all data, the timing check signal 213 is output at the 8th T, so the shift register 6
Take out the 8th T output of 9,71 and pass 222,2
25 to the bank decoder circuit 73.
When the full write signal exists, the timing check control signal 227 at the time of full write is sent to the bank decoder circuit 7 for the bank whose bank address has been decoded.
Output from 3.

Also, during partial writing, the timing check signal is output at the 12th T, so the 12th output of the partial write signal shift register and the 12th output of the bank address shift register are taken out and sent via paths 224 and 225. and sent to the bank decoder circuit 72. When a partial write signal exists, a timing check control signal 226 is sent to the bank whose bank address has been decoded during partial write.
is output from the bank decoder circuit 72. Timing check control signal 227 during full write and timing check control signal 2 during partial write
26 is sent to a gate circuit 74, where it is logically summed and its output becomes a timing check control signal 214. The timing check signal 213 and the timing check control signal 214 always have waveforms of opposite polarity, and under normal conditions, the output 215 of the exclusive OR circuit 64 is logic '1'. when writing
If there is an abnormality in any of the RAS timing, CAS timing, WE timing, or check control signal, the output 21 of the exclusive OR output circuit 64
Error detection is performed by setting 5 to logic '0'. The broken line shown in FIG. 4 indicates the case of an error. In this embodiment, since a check control signal is not generated at each timing to perform a check, it is possible to reduce the amount of hardware required for the check circuit in the case of a multi-bank configuration, and since the number of signals is small, there is no possibility of failure at the connection point. It is also advantageous against Regarding failure detection ability, even if the failure is intermittent, it is fixed for a few μs, and if a write command is sent even once during that time, it can be detected as a timing error. It can be said that there is no difference from checking every time.

The timing check method of the present invention has the advantage that the hardware amount of the timing check circuit can be reduced by setting conditions for the test.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an example of the conventional technology, Fig. 2 is a time chart showing signal waveforms in each part of Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is a circuit diagram showing the It is a time chart showing signal waveforms at each part in the figure. 1...RAS timing generation circuit, 2...CAS
Timing generation circuit, 3...WE timing generation circuit, 4-6...Buffer gate circuit, 7-9...
...Register, 10-12...AND gate circuit,
13-15...Exclusive OR circuit, 16...Request register, 17...Command register, 1
8...Bank address register, 19...Command decoder circuit, 20-24...Shift register, 25-27...Inverter gate, 28-2
9...NAND gate, 30-33...Bank decoder circuit, 34-36...Gate circuit, 51...
RAS timing generation circuit, 52...CAS timing generation circuit, 53...WE timing generation circuit, 54-56...Buffer gate circuit, 57-
59...Register, 60-63...AND gate circuit, 64...Exclusive OR circuit, 65...Request register, 66...Command register, 6
7...Bank address register, 68...Command decoder circuit, 69-71...Shift register, 72-73...Bank decoder circuit, 74...
...Gate circuit.

Claims (1)

[Claims] 1 Address multiplexed RAN (RANDOM ACCESS)
In storage devices using RAS
(ROW ADDRESS STROBE) timing check signal generation circuit and CAS (COLUMN ADDRESS
STROBE) timing check signal generation circuit; WE (WRITE ENABEL) timing check signal generation circuit; a timing check control signal generation circuit that outputs a timing check control signal only when a write command is issued; RAS timing,
A timing inspection method characterized by comprising a check circuit that performs a timing check depending on whether all timings of CAS timing and WE timing are output.