KR830001406B1 - Semiconductor memory - Google Patents

Abstract

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Description

Semiconductor memory

1 is a block diagram of a semiconductor memory device showing one embodiment of the present invention.

2 is a time chart of the signal of each part of FIG.

3 is a block diagram of a semiconductor memory device showing another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device using a semiconductor memory element requiring a refresh operation, and more particularly, to an improvement in a method of inspecting a semiconductor memory element control signal.

In general, in a semiconductor memory device requiring refresh, only one or two control signals are turned ON or OFF in the difference between the operation modes of reading, writing, and refreshing data.

Therefore, in the semiconductor memory device using such a semiconductor memory device, the operation mode is simply changed due to the malfunction of the logic circuit.

For example, the address signal is inputted by time division multiplexing with a row address signal and a row address signal, inputted by an open dress strobe signal, and a row address strobe is subsequently applied. In the case of a type of semiconductor memory device requiring only an open-dress signal and an open-dress strobe signal when refreshing by taking a row address signal by a signal, the relationship between each operation mode, the open-dress strobe signal, and the hang-dress strobe signal is as follows.

In the case where the row address strobe signal of the data write mode is not turned on due to a temporary malfunction, this means that the data write mode is changed to the refresh mode in the refresh mode.

The operation of the memory device at this time is that the data is rewritten and written to the write mode. In reality, only the previously written data is refreshed, and the data at the next reading is old data.

However, even when the old data is written, redundant bits such as the diagonal check bit and the like are generated from the write data, so that the read is not detected as an error in the tilt check or the like at the time of reading. In other words, the data is changed.

Such malfunctions have conventionally been a method of increasing the number of circuits even when no inspection or inspection is performed.

There are two methods of detection. For example, in the case of detecting malfunction of the address decoder circuit, one method is to provide a circuit for comparing the address decoder circuit with another and the outputs of the two address decoder circuits. In this method, a malfunction is detected when the comparison in the comparison circuit does not match.

The other is to install a slope check signal generation circuit on the input side of the address decoder circuit and a slope check circuit on the output side.

In this case, the slope inspection signal generation circuit takes in the input of the address decoder circuit and outputs ON or OFF when the number of ONs in the output line (plural) of the address decoder circuit should be odd or even. The tilt inspection circuit takes in the output of the address decoder circuit and the output of the tilt inspection signal generation circuit and detects a malfunction when the total number of ON is odd. These two methods are only for detecting the malfunction of the address decoder circuit, but there are drawbacks in that the number of circuits increases because two circuits are required.

Accordingly, an object of the present invention is to eliminate the above-described problems, and to provide a semiconductor memory device having an effect of performing a tilt test using only an open-dress strobe signal and a hang-address strobe signal which are basically required without adding a test signal. It is.

A feature of the present invention is that, for example, an open-dress strobe signal and a hang-dress strobe signal for driving a semiconductor memory element can be tilted without reading or writing data and without adding a test signal for each operation mode of refresh. For inspection, the semiconductor memory device array in which the random number of semiconductor memory devices is arranged in the width direction of the data is arranged in an excellent column, and one open strobe signal and one row address strobe signal are opened when data is read or written. When sending out and refreshing to the selected semiconductor memory device row, only open dress strobe signal is sent out to all the semiconductor memory devices arranged in the address direction at the same time. Configured to be excellent A.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory device according to one embodiment of the present invention, and FIG. 2 shows a time chart of each signal.

The timing generating circuit 1 outputs the open strobe strobe timing signal 11 and the row address strobe timing signal 12 when reading or writing data, and outputs only the open strobe timing signal 11 when refreshing.

The open-dress strobe timing signal 11 and the row address strobe timing signal 12 are applied to the address decoder circuit 2 so as to select only one column in the semiconductor memory element columns 3 to 6 ( 13) and (14), the signal is divided into four of the addressed strobe signals 15 to 18 and the row addressed strobe signals 19 to 22, respectively. The distributed signal is connected to the semiconductor memory element columns 3 to 6 and also to the gradient inspection circuit 7.

Each of the semiconductor memory element sequences 3 to 6 constitutes a memory capacity of M word XnN bits using N semiconductor memory elements of M word Xn bits, and N pieces of data are read and written simultaneously.

Therefore, the width of reading and writing data is nN bits. In this case, four semiconductor memory device strings are arranged to form a storage capacity of 4M word XnN bits. Therefore, at the time of reading and writing data, only the open-dress strobe signal and the row-address strobe signal connected to four selected semiconductor memory element strings are output.

In addition, in the refresh operation, data reading and writing operations cannot be performed during the refresh operation. Therefore, in order to reduce the time required for the refresh operation, a method of simultaneously refreshing all the semiconductor memory element sequences and thus all the semiconductor memory elements is used. In this case, the refresh is to simultaneously refresh all the semiconductor memory element columns 3 to 6, and when refreshing, the dress strobe signals 15 to 18 are simultaneously output to all the semiconductor memory element columns 3 to 6, and the row is refreshed. The address strobe signals 19 to 22 are not output.

Next, the output states of the open strobe signals 15 to 18 and the row address strobe signals 19 to 22 will be described with respect to data reading, writing, and refresh.

In the time chart of FIG. 2, it is assumed that the negative signal indicates the output ON.

First, when data is read or written, the address strobe timing signal 11 and the row address strobe timing signal 12 are output from the timing generating circuit 1.

Next, in the address decoder circuit 2, when any one column of the semiconductor memory element columns 3 to 6, for example, the semiconductor memory element column 3 is selected by the column select address signals 13 and 14, is selected. The open-dress strobe signal 15 and the row address strobe signal 19 are outputted, and when the semiconductor memory element string 6 is selected, the open-dress strobe signal 18 and the row address strobe signal 22 are outputted. .

Therefore, at the time of reading or writing data, the total of two open strobe signals and one row address strobe signal are output.

When refreshing next time, only the opening strobe timing signal 11 is output from the timing generating circuit 1 and is simultaneously output to four of the opening strobe signals 15 to 18 by the address decoder circuit 2.

As described above, of the eight open address strobe signals 15 to 18 in the total of the row address strobe signals 19 to 22 during the normal operation in any operation mode, it is excellent to output them simultaneously. Inspected by the slope inspection circuit (7).

If the signals are correctly input to the timing generating circuit 1 and the address decoder circuit 2, and the signals are correctly output from the timing generator circuit 1 and the address decoder circuit 2, the gradient inspection circuit 7 has an excellent number of outputs ON. And no output comes out from the slope inspection circuit 7. As shown in FIG. However, if the output of the address decoder circuit 2 is not correct as a result of any abnormality, the number of outputs ON input to the slope inspection circuit 7 becomes a radix and is output from the slope inspection circuit 7 to detect a malfunction. do.

3 shows another embodiment of the present invention, and the same reference numerals as those of FIG. 1 indicate the same thing.

The difference in configuration from the above embodiment is that the semiconductor storage element is directly distributed without distributing the row address strobe timing signal 12 by the column select address signals 13 and 14 connected to the address decoder circuit 2. To connect to everyone.

In a semiconductor memory device of a type which inputs by time-division multiplexing an ordinary address signal, the row address strobe signal is opened inside the memory device and gated by the address strobe signal. The memory device does not operate at all.

Therefore, the above-described row address strobe signal can be connected to all the memory elements at the same time, and the memory element string can be selected using only the open strobe signal.

In the operation of this embodiment, one of the opening strobe signals 15 to 18 and the row address strobe timing signal 12 are outputted by the column selection address signals 13 and 14 when reading or writing data. When refreshing, the open strobe signals 15 to 18 are simultaneously output.

Therefore, in normal operation, it is excellent to simultaneously output four of the open-dress strobe signals 15 to 18 and the total of five of the row address strobe timing signals 12 simultaneously.

By inspecting this in the slope inspection circuit 7, malfunction can be detected as in the case of FIG.

In the above embodiment, the case of four semiconductor memory device strings has been described, but the present invention is not limited thereto.

Also, any logic circuit such as a buffer circuit is inserted in the middle of the open-dress strobe timing signal 11, the open-dress strobe signal 15 to 18, the hang address strobe timing signal 12, and the hang address strobe signal 19 to 22. Nor is it limited.

As for the row address strobe timing signal 12, a method of distributing by the column selection address signals 13 and 14 and a method of directly connecting the row address strobe timing signal 12 to each semiconductor memory element column are described. Although shown, if the sum total of the input signal of the slope test circuit 7 is comprised so that it may become an even number always in normal operation | movement, the number of distribution will not be restrict | limited, with or without a decoder.

According to the present invention as described above, only the input signal of the semiconductor memory element is inputted to the gradient inspection circuit, but also malfunctions of circuits such as a timing generator circuit and an address decoder circuit, as well as malfunctions of circuits located earlier than these circuits. Can be detected.

This makes it possible to detect a wide range of malfunctions with fewer circuits than in the prior art.

Claims (1)

A semiconductor memory device using a semiconductor memory device in which two sets of drive signals for reading and writing and one set of driving signals for refreshing are provided, wherein any number of semiconductor elements is selected in the width direction of data. 12. A semiconductor memory device, characterized in that the semiconductor memory device strings arranged in an excellent arrangement are arranged so that all of the driving signals are input to the slope inspection circuit.

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