JP2628588B2 - DRAM refresh circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh circuit of a dynamic random access memory (hereinafter referred to as “DRAM”) widely used as a memory of an electronic device.

Conventional technology Conventionally, in a memory system using DRAM, read,
DRAM control such as writing and refreshing is performed by an external circuit. In a normal memory access operation such as reading and writing, cells connected to the same row (row) address as the cell selected at that time in the DRAM are used. Despite the automatic refresh, a special refresh cycle is provided at regular intervals for the DRAM refresh operation, and all cells are refreshed during this period. FIG. 10 is a block diagram of a conventional DRAM control circuit, including a refresh interval timer circuit 101, a refresh address generation circuit 102, and a DRAM address switching circuit.
103, a refresh timing control circuit 104, and a DRAM access control circuit 105. In particular, in the refresh operation, a timer circuit for generating a refresh request at regular intervals is provided to execute a predetermined number of refresh operations within a constant time. The refresh cycle has been executed for all cells of the DRAM according to the request of the timer circuit.

SUMMARY OF THE INVENTION A microprocessor unit (hereinafter referred to as "MPU") when a refresh cycle to a DRAM is being executed.
When a memory access operation (read / write) is instructed to the DRAM, the DRAM is performing a refresh operation, so that the memory access is delayed until the end of the refresh cycle.

In the memory access operation, since all the cells connected to the same row (row) address as the cells selected as described above are automatically refreshed, the refresh operation is performed on these cells again in the refresh cycle. Doing so wastes time, leading to a decrease in the throughput of access to the memory system.

The present invention prevents the refresh operation from being performed on the same row (row) address as the cell selected by the memory access operation, reduces the number of executions of the refresh cycle as much as possible, and provides a memory system. It is intended to improve access throughput.

Means for Solving the Problems The present invention is provided in correspondence with a row address of a DRAM in order to solve the above-mentioned problem, is cleared when a corresponding row is refreshed, counts an elapsed time after clearing, and counts. When the value reaches a predetermined value, a refresh interval timer means comprising a plurality of refresh address timers for deriving a refresh request signal for a corresponding row address and an access (read / write) cycle to the DRAM are monitored. Row address decoding means for clearing the count of the refresh address timer corresponding to the row of the accessed cell; refresh order means for determining the execution order of the refresh request signal derived from the refresh interval timer means; The above DRAM access DRAM access control means for controlling, and a signal indicating the end of the access cycle from the DRAM access control means is detected to derive a signal indicating a refresh cycle, and a signal indicating the refresh cycle is sent to the DRAM access control circuit. A refresh timing control means for supplying a signal for inhibiting access to the DRAM, and a DRAM address for selectively supplying a refresh address output from the refresh order means to the DRAM with a signal indicating a refresh cycle from the refresh timing control means. A predetermined time from when the refresh address timer is cleared to when the refresh request signal is derived, and a time required for continuously refreshing all rows from a time when the DRAM can hold the memory. Set smaller than the subtracted value. Set.

Operation The refresh circuit configured as described above operates as follows. First, there are refresh interval timer circuits corresponding in number to the respective row addresses. The refresh interval timer circuits output refresh requests for the corresponding addresses at intervals of executing the refresh operation. Each refresh address timer constituting the refresh interval timer circuit is cleared when the corresponding row is refreshed, counts the elapsed time after the clear, and outputs a refresh request signal when the count value reaches a predetermined value. . The predetermined value is set to be smaller than a value obtained by subtracting a time required for continuously refreshing all rows from a time when the DRAM can hold the memory. The next-stage refresh order circuit determines the execution order of the refresh requests from the preceding stage, requests output of a refresh address in accordance with the determination, and requests the refresh timing circuit to execute a refresh cycle to the DRAM. The row address decode circuit monitors an access (read / write) cycle to the DRAM and clears the count content of the refresh interval timer circuit of the corresponding row address.

Therefore, in the refresh cycle of the DRAM, the refresh cycle is not executed for the row address accessed in the immediately preceding access (read / write) cycle. By setting the above-mentioned predetermined value, even when access to the DRAM is not performed at all during the access cycle and it becomes necessary to refresh all the rows in the refresh cycle, there is no possibility that the storage of the DRAM is erased.

EXAMPLES The present invention will be described in detail below with reference to examples shown in the drawings.

A DRAM requires a refresh operation because a dynamic cell is used as a cell for storing data. To configure a memory system using such a DRAM, a certain period (256 refresh cycles / 4m
It is necessary to execute a refresh cycle every sec). The present invention is intended to limit such a refresh cycle to the minimum necessary. The operation principle of the present invention will be briefly described. DRAM uses 4 msec by utilizing that cells connected to the same row address as cells selected in a normal read / write cycle by the MPU are automatically refreshed. The refresh circuit is controlled so as not to execute the refresh cycle for the row address selected within. At this time, the refresh cycle executed for the DRAM is a row address strobe (hereinafter referred to as "RAS") shown in FIG.
This is an only refresh cycle. In the RAS only refresh mode, the column address strobe (hereinafter referred to as “CAS”) is set to high level and only RAS operates.
In this mode, all cells connected to each row are refreshed by selecting each of the 256-bit row addresses. 25 general-purpose DRAM
With 6K bits, the refresh is 256 refresh cycles /
A description will be given by exemplifying one executed at a rate of 4 msec.

FIG. 1 is a block diagram of a general memory system. A memory circuit 1 composed of a DRAM is connected to an MPU 2 by a data bus, and a DRAM controller 3 is provided between the memory circuit 1 and the MPU 2. The DRAM controller 3 is connected to the MPU 2 by an address bus and connected to the DRAM controller 3. Is MPU2
A control signal is supplied. Memory circuit 1
Is supplied with a memory address and a memory control signal from the DRAM controller 3.

 FIG. 2 is a block diagram of a main part of the present invention.

In FIG. 2, reference numeral 4 denotes a control signal received from the MPU or an address signal supplied through the address bus,
▲ ▼, ▲ ▼, ▲ for memory circuits such as DRAM
▼ A DRAM access control circuit for supplying a memory control signal such as (write enable). Reference numeral 5 denotes address buses A0 to A7, ie, decodes 256 kinds of row addresses from 8 bits of DRAM row address, and a refresh interval timer circuit 6 Clear signal CL1 (n) (n = 1 to 25)
6), and a timing signal CLTMG is led from the DRAM access control circuit 4 to the row address decode circuit 5. As shown in the timing chart of FIG.
It is assumed that the signal indicates the access of M (excluding the refresh cycle). Refresh interval timer circuit 6
Consists of a number of timers corresponding to the refresh address, that is, the row address of the DRAM.
The count of the timer corresponding to the same row address as the cell accessed by the DRAM is cleared by (n). Then, an interval for executing the refresh is measured, and a refresh request signal REFREQ (n) is output to the refresh sequence circuit 7 of the next stage for the address requiring the refresh. When a plurality of REFREQ (n) from the refresh interval timer circuit 6 occur, the refresh order circuit 7 requests the next-stage refresh address circuit 8 to output a refresh address in a step in which the execution order of the refresh request is predetermined. A signal G (n) for one address determined in this manner is used as a clear signal CL2 () for clearing the count of the timer of the corresponding address of the refresh interval timer circuit 6. n) is given to the refresh interval timer circuit 6.

The refresh address circuit 8 guides the refresh address outputs RA0 to RA7 to the DRAM address switching circuit 9 in the next stage. In the DRAM address switching circuit 9, the ROW /
Row address A0-8, column address A9- from address bus A0-17 during DRAM access by ▲ ▼ signal.
17 and the refresh cycle shown in FIG.
The refresh address outputs RA0 to RA7 are selected by the YC signal to derive addresses MA0 to MA8 of the DRAM. This REFCY
In C, the DRAM address signals MA0 to MA8 derived from the DRAM address switching circuit 9 are such that the addresses for the rows of the same cells as the cells written in the DRAM during 4 msec are omitted.
Reference numeral 10 denotes a refresh timing control circuit.
REFREQ, which is a refresh request signal from the refresh sequence circuit 7, and DR from the DRAM access control circuit 4.
AM ▲ ▼ signal is supplied to DRAM access control circuit 4.
The DRAMINH signal and the REFRAS signal are supplied to the refresh sequence circuit 7, the GTMG signal and the LCLK signal, and the DRAM address switching circuit 9 is supplied with the REFCYS signal. The CLK signal in the figure is 33.33kHz
Is supplied to the refresh interval timer circuit 6, and the SYSCLK signal is supplied to the DRAM access control circuit 4, refresh interval timer circuit 6, refresh sequence circuit 7, and refresh timing control circuit 10 as a 10 MHz clock signal. .

Therefore, the address signal MA from the DRAM address switching circuit 9 is
0 to 8 and ▲ ▼ from the DRAM access control circuit 4,
▲ ▼ Both signals cause DRAM (not shown) to ▲
Is high level, and at the timing of the only refresh cycle, each row is sequentially refreshed except for the same row as the cell accessed in the immediately preceding access.

Details of each block shown in FIG. 2 will be described below in order.

FIG. 3 is a detailed block diagram of the refresh interval timer circuit 6, which is constituted by an 8-bit refresh address timer circuit 11 (n) (n = 0, 1 to 255) corresponding to 256 row addresses in a 256K DRAM. Have been. These timer outputs REFREQ (n) ｛n = 0,1,
2… 255｝ is a counter value of 128; that is, about 4 msec ｛30 use
c (= 33, 33 kHz) * 128 = 3.84 msec｝ When it rises, it goes to the high level, and the row address n is sent to the next-stage refresh order circuit 17.
Is output as a refresh request. The reason why the refresh interval is set to 3.84 msec is because the waiting time when all 256 counters simultaneously activate REFREQ is considered (if the refresh cycle time = 0.4 usec, the waiting time = 0.4 * 256 = 102.4use
c). Two DF / Fs (flip-flops) 12 and 13 are CLK
(= 33.33 kHz) to synchronize with SYSCLK (= 10 MHz). CL1 (n) and CL2 (n) are output from the row address decode circuit 5 and the refresh order circuit 7 by clear signals of the counter.

FIG. 4 is a detailed block diagram of the row address decoding circuit 5. The decoding circuit 5 decodes 256 types of row addresses from the address buses A0 to A7, that is, 8 bits of the DRAM row address by the decoding circuit 14, and decodes them. To the refresh address timer circuit 11 (n)
Output as CL1 (n) clear signal. The CLTMG signal, which is a timing signal of the CL1 (n) clear signal, may be a signal having a timing as shown in the timing chart of FIG. Ex). The operation of the row address decode circuit 5 is performed in the DRAM access by the MPU 2 described in the operation principle.
It recognizes the selected row address and outputs a signal for clearing the counter of the refresh address corresponding to the row address.

The next refresh sequence circuit is constituted by a circuit as shown in FIG. The function of this circuit is to determine one address to be executed when some of the 256 REFREQ inputs are simultaneously activated and refresh cannot be executed simultaneously. In this circuit, REFREQ
REFREQ is executed in order from the smaller value of n shown in (n), but it is not particularly necessary to execute in this order. The operation of this circuit is first REFREQ
(N) is latched by the first latch 15 by LCLK. This is because REFREQ
This is to prevent the processing content from changing during execution because the state of (n) may change. These latch outputs are input to the next-stage order determination circuit 16, and one address is determined by the above operation. This result is latched by the second latch 17 at the rising edge of SYSCLK, and is synchronized with SYSCLK. The clear signal CL2 (n) of the counter of the refresh interval timer circuit 6 corresponding to one address determined in this way is output. The CL2 (n) signal is also used as a G (n) signal for the refresh address circuit 8. These CL2
(N), GTMG and LCLK which are timing signals of G (n) signal
Is input from the refresh timing control circuit, and ΣRE
Outputs FREQ signal.

FIG. 6 is a detailed block diagram of the refresh address circuit 8, and includes 256 8-bit refresh address data registers 18 corresponding to each refresh address.
(0), 18 (1), 18 (2)... 18 (255).
Among these registers, G corresponding to the refresh address determined by the preceding refresh sequence circuit is used.
Only one register is selected by the signal (n), and its output is output as refresh addresses RA0 to RA7. The refresh address RA selected in this way is
0 to 7 are input to the DRAM address switching circuit 9 shown in FIG.

The DRAM address switching circuit 9 is composed of two selector circuits. The first selector 19 generates a row address and a column address to be supplied to the DRAM by changing the level of the ROW / COLUMN signal from the MPU address bus during a read / write operation to the DRAM by the MPU or the like. The second selector 20 switches between the MPU address information and the refresh addresses RA0 to RA7 by the REFCYC signal from the refresh timing control circuit 10. The output signals MA0 to MA8 of the selector 2 are used as address inputs to the DRAM.

The operation of the refresh timing control circuit 10 and the DRAM access control circuit 4 will be described with reference to a timing chart shown in FIG.

The timing chart of FIG. 8 shows a case where only REFREQ (0) and (1) of refresh addresses 0 and 1 are simultaneously activated (high). REFREQ
When (0) and REFREQ (1) become active, ΣREFREQ also becomes active for the refresh timing control circuit 10. This makes the refresh timing control circuit 10
Then, the LCLK signal is set to a high level. The state of REFREQ (n) is latched by the first latch 15 of the refresh sequence circuit 7 at the rising edge of the LCLK signal, and the next sequence determination circuit 16 determines the refresh operation for the refresh address (0). Since the preparation for the refresh operation has been completed as described above, the next refresh cycle occurs. However, this cycle cannot be executed simultaneously with the read / write cycle by the MPU access, so it is necessary to wait for the end of the access cycle. This operation is performed by monitoring the level of the DRAMCS signal generated by the DRAM access control circuit 4. DRAMCS signal from MPU to DRAM
Is an active low signal when the access to is executed. That is, the refresh cycle can be executed by detecting the high level of the DRAMCS. When detecting the high level of the DRAMCS, the refresh timing control circuit 10 activates the REFCYC (= DRAMINH) signal. REFCYC is given to the DRAM address switching circuit as a signal indicating a refresh cycle, and DRAMINH
Is a signal supplied to the DRAM access control circuit 4 to prohibit access from the MPU to the DRAM. Therefore, even if there is an access from the MPU during this time, this access is kept waiting until the refresh cycle ends. When REFCYC goes high, the refresh timing control circuit 10 sets the GTMG signal to active low and returns LCLK to low level. Further, this signal is applied to refresh sequence circuit 7, where G corresponding to the selected refresh address (0) is provided.
The (0) and CL2 (0) signals are made active low, and applied to the refresh address circuit 8 and the refresh interval timer circuit 6, respectively. Refresh address output corresponding to G (0) from refresh address circuit 8
RA0 to RA7 are derived, and the refresh address outputs RA0 to RA0 are output.
7 is supplied to the DRAM via the DRAM address switching circuit 9. Also, the counter of the corresponding refresh address timer (0) is cleared by CL2 (0), and REFREQ (0) becomes inactive. After the refresh address is determined
By making REFRAS active at the timing shown in FIG. 9, a RAS only refresh cycle is performed on the DRAM. ΣREFREQ remains REFRE even after the RAS signal is inactive
Since it remains active due to Q (1), it is necessary to continue the refresh cycle. At this time DRAM
The CS signal is already at the low level as shown in FIG. 8 and does not meet the conditions for executing the refresh cycle. In this case, however, the level of the DRAMINH signal is added at the time of detection to make the condition for cycle execution. Thereafter, the refresh operation for the refresh address (1) may be performed in the same manner as in the case for the refresh address (0). Finally, the CLTMG signal derived as an output of the DRAM access control circuit 4 is a signal indicating the access state of the DRAM. In FIG. 8, the signal is the same as the CAS timing at the time of accessing the DRAM. In the access by the two MPUs shown in FIG. 8, the row addresses are 60H (= 96), 20 respectively.
Since H (= 32), the row address decode circuit activates CL1 (96) and CL1 (32), respectively, and supplies them as clear signals for the next-stage refresh interval timers (96) and (32). The embodiment of the present invention operates as described above.

Effect of the Invention Since the present invention has the above configuration, when refreshing a DRAM, the refresh of a row of a cell accessed within a predetermined time is not performed, so that the time required for refresh is reduced. This makes it possible to construct a memory system using a dynamic memory with high throughput.

[Brief description of the drawings]

FIG. 1 is a block diagram of a control circuit of a memory system used in the present invention, FIG. 2 is a block diagram of a main part of the present invention, and FIG.
FIGS. 4, 4, 5, 6 and 7 are block diagrams showing details of each part shown in FIG. 2, FIGS. 8 and 9 are explanatory diagrams of the operation of the present invention, and FIG. It is a block diagram of a conventional example. 1 ... memory circuit, 4 ... DRAM access control circuit, 5 ... row address decode circuit, 6 ... refresh interval timer circuit, 7 ... refresh sequence circuit, 9 ... DRAM address switching circuit, 10 ... refresh timing Control circuit, 11 (0), 11 (1) ... 11 (256) ... refresh address timer.

Claims (1)

(57) [Claims] 1. A DRAM is provided corresponding to a row address of a DRAM.
A plurality of refresh address timers are cleared when the corresponding row is refreshed, count the elapsed time after the clear, and derive a refresh request signal for the corresponding row address when the count value reaches a predetermined value. Refresh interval timer means, a row address decode means for monitoring the access (read / write) cycle to the DRAM, and clearing the count of the refresh address timer corresponding to the row of the accessed cell; The refresh order means for determining the execution order of the refresh request signal derived from the interval timer means, the DRAM access control means for controlling the access of the DRAM, and the signal indicating the end of the access cycle from the DRAM access control means are detected. Refresh timing control means for outputting a signal designating a refresh cycle, and supplying the signal designating the refresh cycle to the DRAM access control circuit as a signal for prohibiting access to the DRAM; and refreshing from the refresh timing control means. And DRAM address switching means for selectively giving a refresh address output from the refresh order means to the DRAM with a signal designating a cycle, wherein the predetermined value is calculated from the time when the DRAM can hold the memory. Characterized in that it is set smaller than the value obtained by subtracting the time required to continuously refresh the rows
DRAM refresh circuit.