JPS62214588A - Refresh control method for dynamic memory - Google Patents

Abstract

PURPOSE:To avoid the contention between a memory access request and a refresh request by applying DMA refresh to the refresh control of a dynamic memory only when no refresh is applied by access refresh. CONSTITUTION:When a refresh start section 32 receives a memory access request signal 5 after the reception of a pulse signal 4, the section 32 outputs an access refresh start signal 11 after the end of memory access. The section 32 receives the next signal 4 after a specified time elapses while no signal 5 is outputted after the reception of the signal 4 and when the signal 5 is outputted from a CPU 1, the section 32 outputs an access refresh start signal 11. Further, when the CPU 1 outputs a hold enable signal 6, the start section 32 outputs a DMA refresh start signal. A refresh signal generation section 12 is started by the signal 10 or 11 to execute the refresh of the memory 9. Thus, the contention between the memory access request and the refresh request is avoided and the decrease in the processing capability of the CPU 1 is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a refresh control method for dynamic memory, and in particular to a method for controlling refresh of a dynamic memory, and in particular, a method for avoiding a reduction in the processing performance of a CPU due to competition between refresh requests and memory access requests and refresh. The present invention relates to a refresh control method suitable for.

[Background of the invention]

Dynamic memory requires a refresh operation to be performed periodically in order to retain the stored contents.

As a conventional dynamic memory refresh control method, as described in Japanese Patent Laid-Open No. 58-29197,
It is known to periodically apply a memory refresh request signal to the highest priority channel of a DMA control device, hold the CPU, and perform refresh. However, the dynamic memory refresh control method described in the above publication is.

In terms of system throughput, the overhead of holding the CPU each time during refresh and the i! There is a problem that f is large.

Further, as another conventional dynamic memory refresh control method, the method described in Japanese Patent Application Laid-open No. 17178/1983 is known. The dynamic memory refresh control method described in the above publication uses microinstructions to It determines that the execution of an instruction does not generate a memory access request and outputs a refresh request. However, in reality, there are many types of software, and it is impossible to add an extra step such as the above determination to all software.

[Purpose of the invention]

The present invention has been made in view of the problems of the prior art described above, and is a dynamic memory refresh control that avoids conflicts between refresh requests and memory access requests, and avoids a reduction in CPU processing performance due to refresh operations. The purpose is to provide a method.

[Summary of the invention]

The dynamic memory refresh control method of the present invention determines whether or not a memory access instruction has been issued from the CPU after a predetermined time has elapsed since the completion of refresh of the dynamic memory, and when it is determined that the memory access instruction has been issued. teeth.

After the memory access ends, the dynamic memory is refreshed (hereinafter referred to as across refresh), and if it is determined that no memory access command has been issued, the CPU is held and then the dynamic memory is refreshed (hereinafter referred to as across refresh). DMA refresh).

That is, the dynamic memory refresh control method of the present invention is a combination of two types of refresh methods in order to avoid a decrease in CPU processing capacity due to conflict between refresh requests and memory access requests.

In the first refresh method, when a memory access command (memory read or memory write) is issued after a specified period of time has elapsed after the refresh is completed, refresh is performed after the memory access is completed. Since this is a refresh, it is called an access refresh. That is, there is always an interval between one normal memory access and the next memory access. Focusing on this, it becomes possible to avoid simultaneous occurrence of memory access requests and refresh requests by activating refresh after memory access. Furthermore, if refresh is performed between memory accesses, conflicts between memory access requests and refresh requests can be avoided.

This eliminates the need to wait for memory access.

It is also possible to avoid a decrease in CPU processing capacity due to refresh.

Note that the specified time mentioned here is, for example, assuming that the dynamic memory requires 128 refreshes in 2 ms, 2 m s / 128 times = 156
p sec/times, which is approximately 15.6 μsec to be exact.
becomes. However, in consideration of refresh margins and the like, the specified time is set to 14 μsec here.

The second refresh method is DMA refresh,
This is done to compensate for the problem of access refresh. The problem with access refresh is that the refresh operation is not activated unless a memory access occurs after a specified time. Therefore, access refresh can be guaranteed when the CPU is operating and when the CPU is held and data is transferred between I/O and memory by DMA transfer. When the CPU is operating, there is always a brief fetch (read-ahead of CPU instruction code) and memory access based on the instruction code. Furthermore, memory access always occurs during DMA transfer between I/O and memory. However, when a hold instruction is given to the CPU, no memory access occurs, so refreshing cannot be guaranteed. Therefore, in order to compensate for such problems, if an access refresh is attempted after a specified period of time has elapsed and no memory access is received, the CPU is held.

Execute refresh. Here, instead of refreshing the CPU immediately after the predetermined time has elapsed, the memory may be held and refreshed if a memory access command is not output even after a predetermined period of time has elapsed after the predetermined time has elapsed.

This is because it is directly linked to a decrease in the hold processing ability of the CPU, so it is desirable to avoid this as much as possible. The second refresh control method holds the CPU and performs refresh.
This is called DMA refresh.

Therefore, the refresh control in the present invention is to perform access refresh for J and % book fishing to avoid conflicts between memory access requests and refresh requests, and to perform DMA refresh if access refresh cannot be performed.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a flowchart showing an embodiment of the refresh control method of the present invention. As shown.

If it is determined in step S1 that the prescribed time of 14 μsec has elapsed, then in step S2 it is determined whether a memory access request has been issued. If it is determined that a memory access request has been issued, after executing the memory access, access refresh is executed in step S3, and the process returns to step S1. If it is determined in step S2 that a memory access is not issued, the process proceeds to step S4, and it is determined again whether the prescribed time of 14 μsec has elapsed.

If it is determined in step S4 that the predetermined time has not elapsed, the process returns to step S2 to determine whether there is a memory access request. In step S4,
If it is determined that the specified time has elapsed, step S5
At this point, a hold request is output to the CPU. In step S6, it is determined whether a hold permission signal has been outputted from the CPU, and if it is determined that it has not been outputted yet, the process proceeds to step S7, and it is determined whether or not a memory access request has been outputted. If it is determined in step S7 that a memory access request has been output, access refresh is performed in step S8, and the process returns to step S6. If it is determined in step S7 that no memory access request has been output, the process returns to step S6.

If it is determined in step S6 that a hold permission signal has been output from the CPU, DMA refresh is executed in step S9.

In this way, by the time the DMA refresh is executed,
Since the specified time for two sessions has elapsed, the specified time for one session has been wasted. Therefore, after the DMA refresh ends, the process returns to step S2, and if an access request is output, after the access operation ends, access refresh is performed in step S3. Also, D in step S9
If no memory access request is output after executing MA refresh, step S4. S5. S6. At S9, DMA refresh is performed at regular time intervals.

FIG. 2 is a block diagram showing a specific example of a refresh control device that executes the flowchart shown in FIG. 1. As shown in the figure, this refresh control device includes a CPU, a memory control signal generator 21, a memory 19, a specified time measurement counter 2, a refresh activation unit 32, a refresh signal generator 12, a counter 16, and an address selector. It consists of 18.

First, the access operation of the refresh control circuit shown in FIG. 2 will be explained. When a memory access request signal (memory read signal or memory write signal) 5 is output from the CPUI, the memory control signal generator 21 creates a memory control signal 22 and outputs it to the memory 19. At the same time, the CPU 1 outputs a CPU address signal 8, which is selected by the address selector 18 and input to the memory 19 as a memory address signal 20.

As a result, data is read and written between the CPUI and the memory 19 via the bus 9.

Next, the refresh operation will be explained. First, the counter 2 for measuring a specified time counts the clock signal CLK, as shown in FIG. 3, and outputs a pulse signal 4 every 14 μsec. Pulse signal 4 is input to refresh activation section 32 . When the refresh activation unit 32 receives the memory access request signal 5 after receiving the pulse signal 4, it outputs the access refresh activation signal 11 after the memory access is completed. Refresh starting section 3
2 is.

After receiving the pulse signal 4, a specified period of time elapses without the memory access request signal 5 being output, and then the primary pulse signal 4 is output.
Upon receiving this, the refresh activation unit 32 outputs a hold request signal 7 to the CPUI. If the memory access request signal 5 is output before the hold permission signal 6 is output from the CPU 1 in response to the hold request signal 7, the refresh activation section 32 outputs the access refresh activation signal 11. Further, when the hold permission signal 6 is output from the CPU 1 in response to the hold request signal 7, the refresh activation unit 32 receives this and
Outputs MA refresh activation signal 10.

That is, the refresh starting unit 32 performs control to implement flowchart 1- shown in FIG.

The refresh signal generator 12 is activated by the DMA refresh activation signal 10 or the access refresh activation signal 11, and sends the refresh control signal 14 to the memory 19.
and select the refresh address 17 from the refresh counter 16 with the address selector 18,
The memory address 20 is given to the memory 19 to perform refresh. After the refresh is completed, the refresh signal generator 12 generates a refresh address update signal 15 and a refresh end r signal 13 for updating the refresh address. As a result, the activation condition for the refresh activation unit 32 is canceled and the refresh counter 16 is updated.

FIG. 4 is a block diagram showing a specific example of the refresh activation section 32 shown in FIG. 2, which is composed of an access refresh activation section 32A and a DMA refresh activation section 32B. When the pulse signal 4 indicating the passage of a specified time is input, the output of the OR circuit 23 becomes rt Hu, which is input to the data terminal of the flip-flop 26, and the clock 3
is held in the flip-flop 26. The above retention is
Since the output signal 35 of the flip-flop 26 is input again to the data terminal by the OR circuit 23, it is self-held. The fact that the content of the flip-flop 26 is rt Hrt means that the specified time has elapsed.

When memory access request signal 5 is input in this state,
Set the access refresh activation signal 11 to II HIT.

Here, the reason why the access refresh activation signal 11, two stages of flip-flops 27 and 28, and the inverter 30 are formed is that when the output signal 35 and the memory access request signal 5 are asynchronous, they cannot be synchronized. It is for the purpose of doing.

Next, when the content of the flip-flop 26 is "I-I", when the prescribed time has elapsed and the pulse signal 4 is inputted again, the AND condition of the AND circuit 24 is satisfied and outputs H'". The signal is inputted to the data terminal of the flip-flop 29 via the OR circuit 25.The flip-flop 29 holds "H" which is inputted to the data terminal at the input timing of the clock 3.

11 HIT held in the flip-flop 29 is self-held by the OR circuit 25, and the flip-flop 2
The output "H" of 9 becomes a hold request signal 7 to the CPUI. If the memory access request signal 5 is input after the hold request signal 7 is output and before the hold permission signal 6 is input from the CPUI, the access refresh activation signal 11 is output from the flip-flop 28. Further, when the hold permission signal 6 is input, the AND condition of the AND circuit 31 is satisfied, and the DMA refresh start signal 10 is output.

When the refresh is completed, the refresh activation signals 10 and 11 are canceled by the signal 34 in the case of access refresh and by the signal 33 in the case of DMA refresh.

The above signals 33 and 34 correspond to the refresh end signal j3 shown in FIG.

In addition, after the DMA refresh ends, if there is no memory access, the output signal 35 holds ■('', so the hold request signal 7 is output at every specified time, and the DMA refresh is started every time the hold permission signal 6 is input. It is executed repeatedly.

An example of a time chart when the access refresh described above is performed is shown in FIG. 5, and an example of a time chart when the DMA refresh is performed is shown in FIG.

As is clear from the above description, according to the embodiments described above, refresh is normally executed between one memory access and the next memory access, so there is no conflict between a memory access request and a refresh request. Also, DMA
Since refresh occurs only when the CPU receives a stop command, it is possible to prevent a decrease in the processing performance of the CPU.

〔Effect of the invention〕

As described above, according to the present invention, refresh control of the dynamic memory is basically performed by Aquias refresh, and DMA refresh is performed only when refresh cannot be performed by access refresh. Therefore, refresh is basically performed after the end of the memory access and before the start of the next memory access. Therefore, conflicts between memory access requests and refresh requests can be avoided. Therefore, since memory access requests are not made to wait, it is possible to eliminate a decrease in the processing performance of the CPU due to refreshing.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing an embodiment of the dynamic memory refresh control method of the present invention, and FIG.
A block diagram showing a specific example of a refresh control device that executes the flowchart shown in the figure, FIG. 3 is a waveform diagram showing the pulse signal shown in FIG. 2, and FIG. 4 shows details of the refresh starting section shown in FIG. 2. FIG. 5 is a time chart showing an example of when access refresh is performed, and FIG. 6 is a time chart showing an example of when DMA refresh is performed. DESCRIPTION OF SYMBOLS 1...CPU, 2...Counter, 12...Refresh signal generation part, 16...Refresh counter,
I8...address selector, 19...memory, 32
... Refresh starting section, 32A... Access refresh starting section, 32B... DMA refresh starting section.

Claims (1)

[Claims] 1. It is determined whether or not a memory access command has been issued by the CPU after a predetermined period of time has elapsed since the completion of refresh of the dynamic memory, and if it is determined that a memory access command has been issued, the corresponding After the memory access is completed, dynamic memory is refreshed, and if it is determined that no memory access command has been issued, the CP
A dynamic memory refresh control method characterized in that after holding U, the dynamic memory is refreshed. 2. Holding the CPU only when the memory access command is not issued even after a certain period of time has passed after it is determined that the memory access command has not been issued;
A dynamic memory refresh control method according to claim 1, characterized in that the dynamic memory is refreshed.