JPS63204592A - Memory refresh control system - Google Patents

Abstract

PURPOSE:To execute refreshing operation with a simple circuit constitution by storing a microinstruction for executing refreshing operation in the main memory of a control memory and generating an interruption to the microinstruction at a fixed period to execute the refreshing operation of the main memory. CONSTITUTION:The microinstruction for executing the refreshing operation of the main memory 2 from a fixed address is previously stored in the control memory 12, the fixed address is formed at the fixed period and an interruption to the microinstruction is generated from a means 8. When the interruption is generated in the fixed address on the way of processing an instruction word by the microinstruction, the refreshing operation of the main memory 2 is executed by the microinstruction started from the fixed address at the end of the processing of the instruction word. Since the refreshing operation is controlled by the microinstruction, the dynamic RAM can be refreshed with a simple hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a memory refresh control system, and more particularly to a dynamic random access memory refresh 1 control system for a main memory in an information processing apparatus.

BACKGROUND OF THE INVENTION A conventional refresh control method of this type of dynamic under-access memory will be explained with reference to the drawings.

What is shown in Figure 2? FIG. 3 is an external view of a random access memory block having a dynamic type 256 and bitx 1 configuration, and FIG. 3 does not show the corresponding names and functions of the bins of the memory chip.

For example, the physical bin number 1 has a pin name of 8, and is the input bin for 1 bit of the 19-bit address. This memory is l'<AS, C△S, WI
E is waiting for three control input bins, and the combination of these three control bins provides four modes of operation: read 1-7 mode, read 7-mode, freshco mode, and standby [-mode]. You can now choose. This situation is shown in FIG.

Also, this memory has a configuration of 256 bits x 1 and requires 18 bits for the address, which requires 18 bins for the address (pull), increasing the chip size.Therefore, we divided this address into two. The upper 9 bits (referred to as a column address) and the lower 9 bits (referred to as a row address) are the upper 9 bits (referred to as a column address) and the lower 9 bits (referred to as a row address).
When the level reaches 0'', the address is internally read.

FIG. 5j shows the relationship between the address pins of the memory block and internal addresses. In FIG. 5, 2° to 217 are the addresses, 20 to 28 are row addresses, and 29
~217 is the column address. Also, 21~
28 is called a refresh address, and if one of these addresses is accessed once, that is, during a read cycle, write cycle, or fresh cycle, if it is accessed again within 4 milliseconds. The address is refreshed.

By doing this for all refresh addresses, all storage elements of this memory are refreshed. Therefore, if we increment the refresh address by 1 every 4 milliseconds/28-16 microseconds, and dynamically remove the memory in the read cycle, then BU[1t! The main memory will continue to hold its memory contents even if there is no read or 21-in instruction from the sleeve.

FIG. 6 shows time charts for each input/output g=child in these four operating modes. For example, when reading data stored from the memory, input the row address to AO to 88 with RA S = 0, then CAS =
0 and input the column address to AO-A8, [
) The data of the corresponding address appears at the out end f.

When a processor accesses main memory, it basically uses addresses and write data as shown in Figure 7.

The passthrough is an interface for read data and READ and WRITE instruction signals. For example, when reading data from the main memory, the address of the data to be read is output to the address line, and by outputting READ (, i\'J・, the main memory outputs the read data to the read data signal line. Then, the processor takes this information internally.An example of an information processing device whose main memory is a guinomic random access memory that satisfies these conditions is shown in FIG.

This information processing yP device mainly uses dynamic random access memory 2a! 25, a processor 24 that processes data also stored in the main memory 25 according to instructions stored in the main memory 25, and this processor 1J2.
From the read or write instruction signal issued from 4: t
- Refresh controller 26 that generates read/write 1/refresh cycle timing for memory 25
It consists of

Briefly explaining the operation of this device, when the processor 24 wants to read data from the main memory 25, it sets the address of the main memory 25 in the 18-bit address register 27 and outputs the READ signal.

In response to this, the refresh controller 26 first updates the row address part 9 of the address register 27.
The bit is selected by the address multiplexer 28 and the row address selector 32 and output to 80-A8 of the main memory 25, and the timing generation circuit 29 sets it as RAS-0.

Next, 9 bits of the column address part of the address of the address register 27 are transferred to the address full 1 plexer 28. The row address selector 32 is selected and output to 8 to 8 of the main memory, and the timing generation circuit 29 outputs the CA
Let S=O. Then, since the main memory 25 is in the read cycle shown in FIG.
The data is output to the QIJt terminal, and the processor 24 takes in this data. Moreover, this refresh controller 26 has 1
It has a built-in pulse generator 31 of 6 IJs, and is controlled so that the main memory 25 undergoes a refresh cycle every 16 IJs. This selects the row address selector 32 so that the output of the 8-bit refresh counter 30, which is incremented by 1 every 16 cycles, is input to Δ0 to Δ7, and the timing generation circuit 29 sets it to RAS-0. It is done by doing this.

The problem in this case is that when the processor 24 outputs a READ signal or a WRITE signal and the refresh controller 26 controls the main memory 25 to execute a refresh cycle, normally the timing generation circuit I-I A to have a processor from 29
The L T signal is output to eliminate the conflict between the refresh cycle and the processor's main memory operation request.
By delaying AD or WRITE requests
It is supposed to be done.

In other words, the HALT signal is
6, the processor 24 stops operating, and when the refresh cycle flI ends, the IALT signal is no longer output, the processor 24 outputs the READ signal again, and this time the refresh controller 26 accepts the request, and the main memory 25 Enter the lead cycle. This situation is shown in FIG.

In this way, in the conventional information processing apparatus of the eighth Fn, in order to operate the refresh cycle at a constant period, a pulse generator 31 of a constant period, a refresh address generating counter 30, and a processor are used. The selector 32 selects and outputs the address from the flexible 1 counter 30, the refresh cycle and the 1([Δr)/WRITEWRITE from the processor.
Circuit that causes the processor to “stop” 1-state when a signal is received 2
It has 9 built-in.

The refresh control method of the conventional dynamic random access memory described above operates the main memory with one refresh cycle at regular intervals. A refresh counter that generates a refresh address, a selector that selects an address from the refresh counter and the processor, and a refresh cycle and a procedure (READ from 1) are required. The drawback is that it requires circuitry to halt the processor when /WRtTE requests conflict.

OBJECTS OF THE INVENTION An object of the present invention is to provide a memory refresh control method that can refresh a dynamic random access memory with a compact circuit configuration.

According to the present invention, an instruction word stored in a main memory consisting of a dynamic random access memory is decoded and executed by a microphone stored in a control memory. This is a memory refresh control method in which a microinstruction for refreshing the main memory 8 operations is stored in the control memory in advance from the fixed address, and the fixed address is generated at a constant cycle and the microinstruction is Provide a means to generate an interrupt for an instruction,
While the microinstruction stored in the control memory is processing an instruction word, the microinstruction stored in the control memory is stored at the fixed address 7111.
A memory refresh control method is proposed, characterized in that when an interrupt occurs, the main memory is refreshed by a microinstruction starting from the fixed address at the end of processing of the instruction word.

1. Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The main memory 2 has bitx 1 bit in 256 as shown in FIG.
This is one storage device with 256 old tX32b configurations in which 32 Hi-configuration dynamic random access memories are arranged in parallel. For each of the RAS, C.DELTA.S, and WE signals, a write mode, a read mode, a refresh mode, and a standby mode can be selected. In addition, the definition of row address, column address, refresh address, J3J, and each of the four operations C-mode signal line dupmic di! -Tona is Figures 4 to 7
J3 shown in the figure is the same as that described in FIG. 8 of the prior art.

1 is an instruction stored in the main memory 2] - the code part, the register specification part that becomes the operand, and the main memory 2
This is an information processing device that reads and decodes a command word made up of an address designation part, reads out data stored in the main memory 2, performs an operation, and stores the result of the operation in the main memory 2.

Refresh controller 3 is connected to Doma + from processor 1
It receives a signal instructing to read or write data to r12 and an address signal, and writes [(ΔS,C
This circuit sets the timing of the signals AS, WE, AO to 88.

The instruction register 4 is a register that reads and temporarily holds the instruction word held in the main memory 2. data register 5
is a register that reads data held in the main memory 2 and temporarily holds it. The instruction decoder 6 is the instruction register 4
This is a decoder that outputs the start address of the corresponding microinstruction from the instruction code section of the microinstruction. The microinstruction address register 7 is a register that holds the address of the microinstruction to be executed in the next machine cycle of the microinstruction being executed. The fixed address generator 8 is a circuit that generates the start address of a microinstruction for refreshing the main memory 2. The 4IIIS pulse generating circuit 9 is a circuit that generates pulses at a period of 4 milliseconds, which is shorter than the time required for the stored contents to be lost when the electric charge in the main memory 2 falls below a certain level.

The micro-instruction address selector 10 outputs the contents of the micro-instruction address register 7 during the processing of the instruction word stored in the instruction register 4, and also outputs the contents of the instruction address register 7 in the last machine cycle of the instruction unit n. Output the contents. Further, this selector 10 is a selector that outputs the contents of the fixed address generator 8 when a pulse from the 4 ms pulse generating circuit 9 is received in the last machine cycle of the instruction word. Next microinstruction address generator 11;
This circuit adds 1 to the output of the microinstruction address selector 10 and sets it in the microinstruction address register 7.

The control memory 12 holds a microinstruction whose format is shown in FIG. 10, which means that this microinstruction is a microinstruction step that processes the last instruction word. This microinstruction includes a field "END" which controls the microinstruction address selector 10, and a field "IR!" which instructs execution of data reading and writing into the main memory 2. 1. “W” and a field “SE” that controls decoding the instruction word held in the instruction register 4 and performing the operation on the specified operand.
L 14”, “5EL17”, S E L 1
8”.

The format is as shown in FIG. 10, which consists of ``ΔL U'' to ``DIR'' and a field ``CONST'' for specifying a constant.

The microinstruction register 13 temporarily holds the output of the control memory 12, and the microinstruction address selector 10 uses the output.
This is a register that instructs execution of reading and writing of data to the main memory 2 by controlling operations on and operands.

Here, the format of the instruction word of this processor is set to the first
As shown in FIG. 1, OP is an instruction code section and serves as an input to the instruction decoder 6. GRl is a general-purpose register designation section and serves as an input to the selector 14.

GR2 is also a general-purpose register designation section and serves as an input to the selector 14. D is a displacement part of the address of the main memory, and is an input to the selector 17.

FIG. 12 shows the instruction codes and their functions for two typical instructions. For example, ADMG has an instruction code of Q
2 (tlex,), reads the word whose address is the sum of the general-purpose register specified by GR2 and D from the main memory, calculates the sum with the general-purpose register specified by GR1, and calculates the sum of the general-purpose register specified by GR1. This is an instruction to store in a general-purpose register.

The fixed address generator 15 is a circuit that generates an address where the instruction counter value is stored and inputs it to the selector 14 in order to retrieve the instruction counter value included in the general-purpose register group 16. Selector 14 is GRI of instruction register 4
, GR2 and the output of the fixed address generator 15 are selected by the 5EL14 field of the microphone [1 instruction register 13 and outputted to become the address of the general-purpose register group 16. The general-purpose register group 16 is a register group that includes an instruction counter and serves as a plurality of general-purpose registers for performing various operations.

The selector 17 selects and outputs the D field of the instruction register 4, the data register 5, the general-purpose register l'ff16, and the work register 20 (described later) using the 5EL2 field of the microinstruction register 13, and outputs the D field of the instruction register 4, the data register 5, the general-purpose register l'ff16, and the work register 20, which will be described later, using the 5EL2 field of the microinstruction register 13. This is a selector that takes one input. Selector 18
is a selector that selects and outputs the contents of the C0N5T field of the microinstruction register 13 and the output of the work register 20 by the 5EL3 field of the microinstruction register 13, and serves as the other input of the enumerator 19, which will be described later. It is.

The arithmetic unit 19 receives the selector 17 and the selector 18 as input,
It is controlled by the ALU field of the microinstruction register 13, performs calculations, and outputs the results to a work register 20 and an address register 21, which will be described later. The work register 20 temporarily holds the output of the arithmetic unit 19, and selector 17. Selector 18. This register is used as an input to the general-purpose register group 16 and as write data to the main memory 2.

What about address register 21? This is a register that temporarily holds the output of one unit and uses it as an address in the main memory 2.

The address multiple block 22 is a selector that selects the column address part and row address part of the address held in the address 21 under the control of the timing generation circuit 23 and outputs the selected column address part and row address part to the addresses AO-A8 of the main memory 2. The timing generator 11 circuit 23 generates timing for selecting RAS, CAS, WE of the main memory 2 and the address multiplexer 22 from the WRITE, REΔD signals output by the W and R fields of the microinstruction register 13. It is a circuit.

Next, the operation of this circuit will be explained step by step. The previously mentioned ΔDMG instruction and the refresh operation of fi2 will be explained in detail. FIG. 13 shows a module that processes the MG instruction and a module that controls the refresh operation of the main memory 2 among the microinstructions stored in the control memory 12 of FIG. .

First, when the ADMG instruction is stored in the instruction register 4,
The instruction code section is decoded by the instruction decoder 6, and the processing start address is 00Q (flex, ).
is output, passes through the microinstruction address selector 10, becomes the address of the control memory 12, and becomes 000 (IIQX,)
The address is read and set in the microinstruction register 13. The content of this microinstruction is to set the selector 14 to GR2.
Then, change the selector 17 to the general-purpose register group 16 and set it to GR2.
This means reading the contents of and setting them in the work register 20. At the same time, 1 is added to the microinstruction address OOO(lleX,), which is the output of the rector 10, by the next microinstruction address generation error 11, and 001 (Hex,) is set in the microinstruction address register 7.

Therefore, in the next machine cycle, the output 001 (flex,) of the microinstruction address register 7 passes through the microinstruction address selector 10 and accesses the control memory 12, and as a result, the microinstruction at address OO1 (lleX,) is executed. be done. Similarly below 002.003,004
．． The microinstructions are then executed.

Now, in the microinstruction at address OO1 (llcx,),
The selector 17 is controlled to output the D (displacement) field of the instruction register 4, the work register 20 is output from the selector 18, and the contents of the work register and the D section of the instruction register are added to the address register 21. Set to . Next, the microphone at address 002 (flax, ) [1
The command outputs a read instruction signal to the main memory 2, and
The content of l is 8L! is set in the work register 20 through the director 17 and the Q operator 19, and the output of the main memory 2 is set to f.
– set in the data register.

Next, the microinstruction at address 003 (flex,) t adds the contents of the data register 5 and the contents of the 1 node register 20 and sets it in the work register 20 again. Next, in the microinstruction at address 004 (flex,), the dt register l! The contents of the work register 20 are allocated to GR1 of ¥16.

Next, in the microinstruction at address OO5 (flax,),
The contents of the instruction counter included in the general-purpose register group 16 are read to the selector 17, and
Adding the constant 1 of the 0N5T field, the address stored in the main memory 2 of the next instruction word is calculated by 51 and set in the work register 20 and address register 21. next,
In the microinstruction at address OO6 (llex,), ADM
A signal indicating that this is the last step in the processing of the G instruction is output to the microinstruction address selector 10, and the main memory 2
The contents of the work register 20 are written to the part of the general-purpose register group 16 where the instruction counter is held, and the instruction word to be executed next is set in the instruction register 4.

In the next machine cycle, this instruction word is processed by ADMG.
It begins like a command. When the micro-instruction address selector 10 outputs a pulse from the 41s pulse generation circuit 9 while executing the microphone [1 instruction at address 006(l(ax,)), the micro-instruction address selector 10 selects the contents of the fixed address generator 8. Output and jump to refresh control routine.At address 100 (flax,), work register 20
and sets the initial value O in the address register 21. At the next address 101 (IIQX, ), 2 is added to the value of the work register 20 to change the refresh 1 address, the work register 20 and address register 21 are hit again, and the main memory 2 is read out. This is repeated by setting all the refresho addresses to 1 and ending at address 200 (IIQX,). In the next machine cycle, execution of the next suspended instruction is continued for a period of if1.

As described above, a pulse is generated before the charge is lost from the memory element and its memory contents are lost, and when the pulse is generated, the microinstruction is sent to the main memory even after the instruction word has been processed. Nori freshco! It branches to a microinstruction sequence that performs a IIIJ operation, performs a refresh, and resumes execution of the next instruction after the refresh is completed.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by performing refresh control of the Guinamik Y1 random access memory using microinstructions, a refresh counter that generates a refresh address that was conventionally necessary, a refresh l address, and a refresh address are provided. This eliminates the need for a selector that selects a counter and a circuit that stops the processor when a READ/WRITE request from J- conflicts with the refresh cycle, and allows dynamic random access memory to be refreshed with simple hardware. It has the effect of being able to do the following.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an information processing device that is an embodiment of the present invention, Fig. 2 is an external view of a dynamic random access memory, and Fig. 3 is the pin number of the memory shown in Fig. 2 and its corresponding correspondence. FIG. 4 is a diagram showing the relationship between the operation mode of the memory in FIG. 2 and the control signal.
Figure 5 shows the address input terminal and internal address of Figure 2. Figure 6 is a diagram showing the relationship between column addresses, row addresses, and refresh addresses. Figure 6 is a time chart showing the temporal transition of signal lines in J7 in each operation mode of Figure 2. Figure 7 is a processor diagram. 8 is a block diagram showing an example of an information processing device using a conventional dynamic random access memory as the main memory, and FIG. 9 is an image of the information processing in FIG. 8. ; FIG. 10 is a time chart showing the situation when a read request to the main memory is issued from the processor while the refresh controller is executing a refresh cycle for the main memory in n. FIG. 11 is a diagram showing the format of a microinstruction and its meaning; FIG.
The figure shows examples of commands and their functions in the information processing device of FIG. 1, and FIG.
2 is a diagram illustrating an example of a microinstruction for controlling processing of an MG instruction and refreshing of main memory; FIG. 1. Disclosure of the codes of the main parts 1...P[1]...Main memory 3...Refresh controller 8...
・Fixed address generator 9...4ms pulse generation circuit 10...Micro instruction address selector 11・
...Next microinstruction address generator 12...
... le (control memory

Claims (1)

[Claims] A memory refresh control method for an information processing device in which a command word stored in a main memory consisting of a dynamic random access memory is decoded and executed by a microinstruction stored in a control memory, the control memory A microinstruction for refreshing the main memory is stored in advance from the fixed address in the memory,
Means is provided for generating the fixed address at a constant cycle and generating an interrupt for the microinstruction, and an interrupt is generated at the fixed address while the microinstruction stored in the control memory is processing an instruction word. If a refresh occurs, the main memory is refreshed by a microinstruction starting from the fixed address at the end of processing of the instruction word.