JPH07302219A - Data processor and data processing method - Google Patents

Abstract

PURPOSE:To in the output timing of chip enable signals and addresses, to shorten data read/write periods, to quicken the start of arithmetic operations and to accelerate read modification write operations relating to the improvement of a data processor. CONSTITUTION:This processor is provided with a memory control means 11 for reading data from an information storage device 13 based on reference signals CLK or writing the data to the information storage device 13 and a data working means 12 for working the data read from the information storage device 13. The memory control means 11 reads the data from the information storage device 13 and writes the worked data in the same storage address of the information storage device 13 during the data read/write periods T allocated beforehand.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor and a data processing method, and more particularly to speeding up a read-modify-write operation of a microcomputer. In recent years, in the usage modes of microcontrollers that perform various information processing,
Models that can perform high-speed calculations are becoming a priority. For example, a data operation instruction is prepared in which data is read from an arbitrary storage address in the memory, an operation is performed on the data, and the operation result is written again in the same storage address.

According to the read-modify-write operation of such a data operation instruction, three cycles of the reference signal are added to the read cycle for reading the data from the memory, even though the operation result is written again at the same storage address. Allocation, 3 of the reference signal in the write cycle to write data to the memory
Each cycle is assigned. Therefore, when executing a read-modify-write instruction with an information storage device such as a dynamic random access memory or a pseudo static random access memory as a control target, the method of allocating 6 cycles of the reference signal for the data read and write periods is Further data processing time cannot be shortened, which hinders the performance improvement of the processor.

Therefore, by devising the output timing of the address and the chip enable signal, the data read / write period can be shortened, the operation operation can be started earlier, and the read modify write operation can be speeded up. Is desired.

[0004]

2. Description of the Related Art FIGS. 5 to 7 are explanatory views according to a conventional example. FIG. 5 is a configuration diagram of a data processor according to a conventional example, and FIGS. 6 and 7 are operation explanatory diagrams (Nos. 1 and 2) thereof, respectively. For example, a data processor that executes a read-modify-write instruction based on a reference signal (hereinafter referred to as a CLK signal) has a DRAM controller 1, an address register 2, and a general-purpose register 3 connected to an internal bus 6, as shown in FIG. , An arithmetic logic unit (hereinafter simply referred to as ALU) 4 and a data control unit 5.

Here, the read-modify-write instruction is an instruction execution content in which data is read from an arbitrary storage address of the memory, an operation is performed on the data, and the operation result data is written in the same storage address again. Specifically, the data control unit 5 includes a DRAM control unit 1, an address register 2,
The contents control the input / output of the general-purpose register 3 and the ALU 4.

For example, when a read-modify-write instruction is executed by targeting a dynamic random access memory (hereinafter referred to as DRAM) 9, as shown in FIG. And the latter half 3 cycles to the write cycle (W.CYC). The read cycle is a period for reading data from the memory, and the write cycle is a period for writing data in the memory.

In the first cycle of the read cycle,
D from the address register 2 via the DRAM control unit 1
The row address is output to the RAM 9, and the column address is output from the register 2 to the DRAM 9 in the second cycle. The row address is an address that selects the word line at the storage address of the DRAM 9, and the column address is the address that selects that bit line. The row address is output based on a row address output signal (hereinafter simply referred to as RAS signal). The column address is output based on a read strobe signal (hereinafter simply referred to as RDX signal).

As a result, in the third cycle of the read cycle, the DRAM 9 to the DRAM control unit 1 are operated based on the column address output signal (hereinafter referred to simply as the CAS signal).
Data is read to the general-purpose register 3 via. Then, in the first cycle of the write cycle, the row address is output to DRAM 9 based on the RAS signal. This row address is an address for selecting a word line when designating a new storage address of the DRAM 9 for the operation result data.

Then, in the second cycle of the write cycle, the ALU 4 starts the data operation, and when the data operation is completed, the column address is output to the DRAM 9 based on the write enable signal (hereinafter referred to as WTX signal). This column address is an address for selecting the bit line of the new storage address of the DRAM 9. As a result, the operation result data is transferred from the general-purpose register 3 to the DRAM 9 in the third cycle from the end of the data operation in the second cycle of the write cycle.

Further, when a read-modify-write instruction is executed targeting a pseudo static random access memory (hereinafter referred to as PSRAM) 10, FIG.
As shown in FIG. 3, the first half 3 cycles to the CLK signal are assigned to the read cycle (R.CYC), and the second half 3
Cycles ~ are assigned to the write cycle (W.CYC).

In the first cycle of the read cycle,
An address is output from the address register 2 to the PSRAM 10 based on a chip enable signal (hereinafter simply referred to as a CEX signal). This address is output through 6 cycles of a read cycle and a write cycle in a PSRAM that requires a memory holding operation. Second of read cycle
In this cycle, the output enable signal (hereinafter simply referred to as the OEX signal) falls. As a result, in the third cycle, the OEX signal = “L” (low)
From the PSRAM 10 to the DRAM controller 1 based on the level
Data is read to the general-purpose register 3 via.

Next, in the first cycle of the write cycle, the CEX signal changes from "L" to "H" (high) level and O.
The EX signal transits from "L" to "H" level. After that, when the CEX signal transits to the “L” level in the second cycle, the ALU 4 starts the data operation. When this data calculation is completed, DRA is transferred from the general-purpose register 3 based on the WTX signal = “L” level.
The operation result data (write data) is transferred to the PSRAM 10 via the M control unit 1.

[0013]

By the way, according to the read-modify-write operation of the conventional example, the operation contents are read from the same storage address, and the operation result data is written again to the storage address. Despite this, the row address is set to the DRAM in the first cycle of the write cycle.
It is output to 9.

This is because even if the data read or write operation based on the normal 6 cycles is applied to the read modify write operation, the new storage address of the DRAM 9 is determined early so that the "data transfer time" is increased. This is because it was thought that "it can be shortened." That is, the row address is output to the DRAM 9 based on the RAS signal in the first cycle, and the word line at the new storage address of the operation result data is determined earlier, so that the ALU 4 in the second cycle of the write cycle is written. Simultaneously with the end of the operation, the column address is output to the DRAM 9 based on the WTX signal, and the operation result data can be transferred from the general-purpose register 3 to the DRAM 9 using the third cycle from the end time.

However, considering the read-modify-write operation of writing the operation result data again to the same storage address, the row address is output to the DRAM 9 in the first cycle of the write cycle, and the column address is output in the second cycle. Specifying the address again causes a delay in the operation start of the ALU4. As a result, if the normal data read or write operation is directly applied to the read-modify-write operation, even if the operation operation start time of the ALU 4 is advanced and the operation result data is obtained at high speed, the row address is not confirmed. And DR the calculation result data
Unable to transfer to AM9.

As a result, the DRAM 9 and the PSRAM 10
Read modify write period targeting
In the method of allocating and executing 6 cycles of the CLK signal,
There is a problem in that the data processing time cannot be shortened any further and this hinders the performance improvement of the processor. The present invention was created in view of the problems of the conventional example, devises the output timing of the address and the chip enable signal, shortens the data read / write period, and accelerates the start of the arithmetic operation. An object of the present invention is to provide a data processor and a data processing method capable of accelerating a read modify write operation.

[0017]

FIG. 1 shows a principle diagram of a data processor and a data processing method according to the present invention. The data processor of the present invention, as shown in FIG.
Memory control means 11 for reading data from the storage address of the information storage device 13 based on the reference signal CLK and writing the processed data to the same storage address of the information storage device 13, and the information storage device. The data processing means 12 for processing the data read from the data processing device 13 is provided.

In the data processor of the present invention, the data processing means 12 stores a first register 12A for storing an address required for writing and reading the data, an arithmetic unit 12B for arithmetically operating the data, and the data. Based on the second register 12C and the reference signal CLK, the memory control means 11, the first register 12A, and the arithmetic unit 12B.
And a data control unit for controlling the input / output of the second register 12C
12D and.

In the data processor of the present invention, the memory control means 11 selects at least either the dynamic random access memory DRAM or the pseudo static random access memory PSRAM based on the memory selection signal SX. . The first data processing method of the present invention reads the data from the storage address of the information storage device 13 and writes the processed data in the same storage address of the information storage device 13 in a series of operations in which the reference signal CLK A data read / write period T defined by a unit cycle is allocated, and at least
In the first half of the data read / write period T, a row address for selecting the word line of the storage address of the information storage device 13 is output, and in the latter half of the data read / write period T following the output of the row address, the information storage The column address for selecting the bit line of the device 13 is output.

In the first data processing method of the present invention,
At least the first of the data read / write period T
In the second cycle of the data read / write period T, the row address for selecting the word line at the storage address of the information storage device 13 is output.
The column address for selecting the bit line of the storage address is output, the data is read from the storage address of the information storage device 13 in the third cycle of the data read / write period T, and the The data is calculated in four cycles, and the calculated data is written in the same storage address of the information storage device 13 by using the fifth cycle of the data read / write period T from the end of the calculation of the data. It is characterized by including.

The second data processing method of the present invention is based on a series of operations for reading data from the storage address of the information storage device 13 and writing the processed data in the same storage address of the information storage device 13. A data read / write period T defined by a unit cycle of the signal CLK is assigned, and at least in the first to fifth cycles of the data read / write period T, an address designating a storage address of the information storage device 13 is output. Then, in the third cycle of the data read / write period T, the information storage device 1
Data is read from the storage address of 3, and data is calculated in the fourth cycle of the data read / write period T,
Using the fifth cycle of the data read / write period T from the end of the data calculation, the calculated data is written to the same storage address of the information storage device 13, and the above object is achieved. To achieve.

[0022]

[Operation] The operation of the data processor of the present invention will be described. For example, when the memory control unit 11 selects a dynamic random access memory (hereinafter referred to as DRAM 13A) as the information storage device 13 based on the memory selection signal SX and the control unit 11 executes read modify write, the reference signal CLK is set. DRAM based
Data is read from 13A, which is data processing means 1
2. The processed data is processed by the DRAM 13
Written to A.

That is, each control signal generated based on the reference signal CLK is output from the data control unit 12D to the first register 12A, the operation unit 12B, the second register 12C and the input / output buffer of the memory control means 11, respectively. When done,
In the first half of the data read / write period T, the row address is output from the first register 12A to the DRAM 13A, and the word line at the storage address of the DRAM 13A is selected based on this row address. In the latter half of the period T, the column address is output from the register 12A to the DRAM 13A, and the bit line at the storage address is selected based on this column address.

In other words, in the first cycle of period T,
The row address is output from the first register 12A to the DRAM 13A, the column address is output from the first register 12A to the DRAM 13A in the second cycle, and the column address is output from the storage address of the DRAM 13A to the second in the third cycle. The read data is read to the register 12C of the above through the memory control means 11.

In the fourth cycle of the period T, when the reading of the read data is confirmed, the arithmetic unit 12B starts the arithmetic operation of the data, and from the end of the arithmetic operation, the fifth cycle of the period T is used to execute the operation of the DRAM 13A. The operation result data is written in the same storage address via the memory control means 11 (first data processing method). Therefore, by outputting the row address to the DRAM 13A in the first half of the period T and continuing the output of the column address in the latter half of the period T, the row address of the write cycle in the write cycle as in the conventional example can be obtained. The operation unit 12B can start the operation from the time when the read of the read data is confirmed or the lower data of the read data is input to the second register 12C without waiting for the confirmation.

As a result, it becomes possible to execute the read modify write operation using 5 cycles of the reference signal CLK. As a result, the calculation result data can be transferred to the DRAM 13A at an early stage, and the speed of data processing can be increased. Further, unlike the write cycle of the conventional example, it is not necessary to output the row address and the column address that again specify the storage address at the time of write access.

Further, in the data processor of the present invention, a pseudo static random access memory (hereinafter referred to as PSRAM) is used as the information storage device 13 based on the memory selection signal SX.
13B) is selected and the memory control means 11 executes the read-modify-write, data is read from the PSRAM 13B during the data read / write period T allocated in advance, and the data is processed by the data processing means 12. The processed data is written in the PSRAM 13B.

That is, each control signal generated based on the reference signal CLK is output from the data control unit 12D to the first register 12A, the arithmetic unit 12B, the second register 12C and the input / output buffer of the memory control means 11, respectively. When done,
During the data read / write period T, the address is output from the first register 12A to the PSRAM 13B, and the word line and the bit line at the storage address of the PSRAM 13B are selected based on this address.

In other words, in the first to fifth cycles of the period T, the address designating the storage address of the PSRAM 13B is output, and in the third cycle, the storage address of the PSRAM 13B is stored in the second register 12C. Control means 11
Read data is read via. In the fourth cycle, when the reading of the read data is confirmed, the arithmetic unit 12B starts the arithmetic operation of the data based on the chip enable signal, and the PSRAM 13B is used in the fifth cycle of the period T from the arithmetic end time. In the same storage address of
The operation result data is written via the memory control means 11 (second data processing method).

Therefore, by continuing the output of the address designating the storage address of the PSRAM 13B in the first to fifth cycles of the period T, the chip enable signal is generated in the second cycle of the write cycle as in the conventional example. Read data read is confirmed without activating, or
By activating the chip enable signal from the time when the lower data of the read data is input to the second register 12C, it is possible to accelerate the operation start.

As a result, similarly to the first data processing method, the operation result data can be transferred to the PSRAM 13B early, and the speed of data processing can be increased.

[0032]

Embodiments of the present invention will now be described with reference to the drawings. 2 to 4 are diagrams for explaining the data processor and the data processing method according to the embodiment of the present invention. 2 is a configuration diagram of a data processor according to an embodiment of the present invention, FIG. 3 is a waveform diagram of a read modify write operation at the time of DRAM access, and FIG.
The waveform diagrams of the read-modify-write operation during SRAM access are shown respectively.

For example, the DRAM 25 and the PSRAM 26
As shown in FIG. 2, the data processor for executing the read-modify-write command targeting the information storage device such as
2 and a clock generator 23. That is, DRA
The M control unit 21 is an example of the memory control unit 11 of FIG. 1, and the DRAM 25 or the PSRAM 26 is based on a reference signal (hereinafter simply referred to as a CLK signal) and a memory control signal S 10.
Data (DATA) is read from the DRAM and the DRAM
25 or the PSRAM 2 is controlled to write the calculation result data. The DRAM control unit 21 receives the D data via the external data bus 27, the external address bus 28 and various control lines.
It is connected to the RAM 25 and the PSRAM 26.

The DRAM control unit 21 uses a read modify write cycle (hereinafter referred to as RMW cycle).
Further, to the DRAM 25, an address ADR, a read strobe signal (hereinafter simply referred to as RDX signal), a write enable signal (hereinafter simply referred to as WRX signal), a row address output signal (hereinafter simply referred to as RAS signal) and a column address output signal (hereinafter simply referred to as RAS signal). Output as a CAS signal).

Here, R. M. The W cycle is an example of the data read / write period T shown in FIG. 1, and is a period in which 5 cycles of the CLK signal are one unit. R. M. W
If the number of cycles is 5 cycles or less of the CLK signal, the speed of data processing is further increased. In addition, the DRAM control unit 21 controls the R. M. In the W cycle, the address ADR, the chip enable signal (hereinafter simply referred to as the CEX signal) and the output enable signal (hereinafter simply referred to as the OEX signal) are output to the PSRAM 26. As a result, the DRAM control unit 21 reads out the data from the PSRAM 26 and outputs the processed data to the PSRAM 26.
Write to. The DRAM control unit 21 selects either the DRAM 25 or the PSRAM 26 based on the memory selection signal SX supplied from the outside.

The data calculation system 22 is an example of the data processing means 12 and processes data read from either the DRAM 25 or the PSRAM 26. The operation system 22 includes an address register 22A, an arithmetic logic operation unit (hereinafter referred to as ALU) 22B, a general register 22C, an instruction execution control unit 22D, an input buffer B1,
B2, B4, B5, B7 and output buffers B3, B6
Have B8.

The address register 22A is the first register 12
This is an example of A and stores an address required for writing and reading data. The address register 22A is connected to the internal bus 24 via the input buffer B2 and the output buffer B2. The internal bus 24 is connected to the DRAM control unit 21 via the input buffer B1. The buffer B1 inputs and outputs data and addresses based on the gate signal S1. The buffer B2 inputs the address based on the gate signal S2, and the buffer B3 outputs the address based on the gate signal S3.

The ALU 22B is an example of the arithmetic unit 12B, and D
The data read from the RAM 25 or the PSRAM 26 is operated. For example, the ALU 22B uses the augend and addend read from the DRAM 25 as read data, adds both numbers based on the operation mode signal S9, and outputs the operation result data. ALU22B is input buffer B4, B5
And an output buffer B6 to connect to the internal bus 24. The buffers B4 and B5 fetch data from the internal bus 24 based on the gate signals S4 and S5. Buffer B6
Outputs the operation result data to the internal bus 24 based on the gate signal S6.

The general-purpose register 22C is an example of the second register 12C and stores read data and operation result data. The general-purpose register 22C is connected to the internal bus 24 via the input buffer B7 and the output buffer B8. The buffer B7 inputs read data based on the gate signal S7, and the buffer B8 outputs read data based on the gate signal S8.

The instruction execution controller 22D is an example of the data controller 12D, and the DRAM controller 2 is based on the CLK signal.
1, controlling input / output of the address register 22A, ALU 22B and general-purpose register 22C. For example, the data control unit 22D
Are various gate signals S1 to S based on the sequence for executing the read modify write operation and the CLK signal.
8. Generate operation mode signal S9 and memory control signal S10. The sequence for executing the read modify write operation is written in the EPROM or PLA in the control unit 22D.

The clock generation unit 23 uses a CL having a predetermined frequency.
A K signal is generated and supplied to the DRAM controller 21 and the data controller 22D. The clock generator 23 may be provided with a frequency dividing circuit to divide the high speed clock signal. Next, the read-modify-write operation of the processor when accessing the DRAM will be described with reference to FIG.
For example, the DRAM 25 is selected by the memory selection signal SX, and each gate signal S generated based on the CLK signal is generated.
1 to S8 from the data control unit 22D to the buffers B1 to B8
Are output respectively. Further, the calculation mode signal S9 is A
When the memory control signal S10 is output to the LU22B and the memory control signal S10 is output to the DRAM control unit 21, the R.R. M. In the first half of the W cycle, the row address is output from the address register 22A to the DRAM 25, and the word line at the storage address of the DRAM 25 is selected based on this row address. In addition, R. M. In the latter half of the W cycle, the column address is output from the register 12A to the DRAM 25, and the bit line of the storage address is selected based on this column address.

That is, as shown in FIG. M. W
In the first cycle of the cycle, the row address is output from the address register 22A to the DRAM 25. At this time, the gate signal S2 is output from the instruction execution control unit 22D to the input buffer B2, and the address ADR on the internal bus 24 is output.
Is written in the address register 22A. Address ADR
Is output from another register to the internal bus 24. DRA
The M control unit 21 outputs the address ADR to the address output terminal based on the memory control signal S10. Specifically, the DRAM control unit 21 outputs the upper data (row address) of the address ADR from the address output terminal, and activates the output of the RAS output terminal after half a cycle.

R. M. In the second cycle of the W cycle, the column address is transferred from the address register 22A to DRA.
It is output to M25. At this time, the memory control signal 10 is output from the instruction execution control unit 22D to the DRAM control unit 21,
The RDX signal is activated. This allows DRA
The M control unit 21 outputs the lower data (column address) of the address ADR from the address output terminal. After half a cycle, the CAS output terminal and the RDX output terminal are activated.

If necessary, the instruction execution control unit 22D
Outputs the gate signal S8 to the input buffer B8, and the general register 22C outputs the arithmetic value or the like to be the augend to the internal bus 24. Further, the gate signal S5 is output from the control unit 22D to the input buffer B5, and the AD of the ALU 22B is output.
The calculated value is written to the register. R. M. In the third cycle of the W cycle, read data is read from the storage address of the DRAM 25 to the general-purpose register 22C via the DRAM control unit 21. At this time, the instruction execution control unit 22D
The memory control signal S10 is output from the DRAM control unit 21 to the DRAM control unit 21, and the internal bus 24 is transmitted from the DRAM 25 via the external data bus 27, the external data bus terminal and the DRAM control unit 21.
Read data is taken into.

Here, the gate signal S4 is output from the instruction execution control unit 22D to the input buffer B4, and the calculated value is written in the AS register of the ALU 22B. Further, the read data taken in the internal bus 24 outputs the gate signal S7 to the input buffer B7 so that the general-purpose register 22
Latched to C. This will allow AL in the next cycle.
The calculation result is obtained from U22B.

That is, R. M. In the fourth cycle of the W cycle, when the reading of the read data is confirmed, A
Calculation of data is started by LU22B. At this time,
In the ALU 22B, the operation according to the instruction is started based on the ALU mode signal S9. In addition, the instruction execution control unit 22
A memory control signal S10 is output from D to the DRAM control unit 21, the RDX output terminal is inactivated, and the WRX output terminal is activated after half a cycle. Further, the gate signal S6 is output from the control unit 22D to the output buffer B6, and the operation result data of the ALU 22B is transferred to the internal bus 24.
Is output to.

Next, from the time when the data calculation is completed, the R.
M. DRA using the fifth cycle of the W cycle
The operation result data is written in the same storage address of M25 via the DRAM control unit 21 (first data processing method). At this time, in the DRAM control section 21, based on the memory control signal S10, the RAS output terminal, the CAS output terminal,
Also, the WRX output terminal is made inactive, and the latched data is output as it is to the external bus terminal.

DR based on the memory control signal S10
The operation result data from the previous state is output to the external data bus terminal of the AM control unit 21, and the RAS output terminal, the CAS output terminal and the WRX output terminal are made inactive half a cycle later. As a result, the calculation result data on the internal bus 24 is transferred to the external data bus. In this way, the R. M. In the W cycle, the DRAM control unit 21 executes the read modify write operation targeting the DRAM 25.

Next, the read-modify-write operation of the processor when accessing the PSRAM will be described with reference to FIG. For example, the gate signals S1 to S8 generated based on the CLK signal are output from the data control unit 22D to the buffers B1 to B8, the operation mode signal S9 is output to the ALU 22B, and the DRAM control unit 21 receives the memory control signal. When each S10 is output, R.S. M.
Through W cycle, address register 22A to PSR
The address ADR as shown in FIG. 4 is output to the AM 26, and the word line and the bit line of the storage address of the PSRAM 26 are selected based on this.

That is, R. M. In the first to fifth cycles of the W cycle, the address designating the storage address of the PSRAM 26 is output. At this time, in the first cycle, the DRAM controller 21 sends PSRA
The non-multiplexed address ADR is output to M26. For example, addresses of all bits are output to the external address bus 28. Also, instead of the RAS signal, CE
The X signal is activated. In the second cycle,
While the CAS signal remains inactive, the OEX signal is activated at the same timing as the RDX signal.

R. M. In the third cycle of the W cycle, read data is read from the storage address of the PSRAM 26 to the general-purpose register 22C via the DRAM controller 21. Specifically, as in the case of the DRAM 25, the PSR
Read data is read from the AM 26 to the internal bus 24. R. M. In the fourth cycle of the W cycle, when the reading of the read data is confirmed, the data operation is started by the ALU 22B based on the CEX signal. At this time, the RDX signal and the OEX signal are made inactive,
At the same time, by making the RWX signal active, the operation result data of the internal bus 24 is output to the external data bus terminal.

Next, from the end of the data calculation, the R. M.
Using the fifth cycle of the W cycle, the PSRAM
The operation result data is written in the same storage address of 26 via the DRAM control unit 21 (second data processing method).
At this time, the WRX signal and the CEX signal are made inactive. As a result, the R.V. M. W
In the cycle, control signal S1 similar to that of DRAM 25
Based on S10 to S10, the read-modify-write operation targeting the PSRAM 26 is executed.

As described above, according to the data processor of the embodiment of the present invention, as shown in FIG. M. DR in W cycle
Read the data from AM25 and DR the operation result data
DRAM 25 for writing to AM 25, and DRAM 25
And a data calculation system 22 for calculating the data read from the.

For this reason, R. M. In the first half of the W cycle,
The row address is output to the DRAM 25 and the R.D. M. By continuing to output the column address in the latter half of the W cycle, the read data read is confirmed or the lower data of the read data is A without waiting for the row address confirmation in the write cycle as in the conventional example.
The arithmetic operation can be started in the ALU 22B from the time when it is input to the S register.

As a result, the read-modify-write access, which was executed by dividing the read cycle and the write cycle into two as in the conventional example, can be executed at high speed as one read-modify-write access. As a result, in the read-modify-write operation using 5 cycles of the CLK signal, the operation result data can be transferred to the DRAM 25 early, and the speed of data processing can be increased. Further, unlike the write cycle of the conventional example, it is not necessary to output the row address and the column address that again specify the storage address of the operation result data.

In the data processor according to the embodiment of the present invention, the R. M. By continuing to output the address designating the storage address of the PSRAM 26 in the first to fifth cycles of the W cycle, the chip enable signal is not activated in the second cycle of the write cycle as in the conventional example. , Read data read is confirmed, or
When the lower data of the read data is input to the general-purpose register 22C, the chip enable signal is activated and the ALU is activated.
Calculation can be started by 22B.

For this reason, the calculation result data can be sent to the PSR early.
The data can be transferred to the AM 26 and the read-modify-write instruction targeting the PSRAM 26 can be executed at high speed, as in the case of the DRAM 25. This largely contributes to the performance improvement of the data processor and the speeding up of data processing.

[0058]

As described above, according to the data processor of the present invention, the data read / read assigned in advance is assigned.
A memory control unit that reads data from the information storage device and writes the processed data to the storage device during the writing period, and a data processing unit that processes the data read from the information storage device are provided.

Therefore, by outputting the row address to the information storage device in the first half of the period and continuing the output of the column address in the latter half of the period, the row address can be determined in the write cycle as in the conventional example. The operation can be started without waiting, when the reading of the read data is confirmed, or when the lower data of the read data is input to the register. As a result, it is not necessary to output the row address and column address again at the time of write access, unlike the conventional example.

Further, in the data processor of the present invention, the address designating the storage address of the information storage device is output in the first to fifth cycles of the data read / write period allocated in advance. Therefore, the read of the read data is confirmed without activating the chip enable signal in the second cycle of the write cycle as in the conventional example.
Alternatively, the operation start time can be advanced by activating the chip enable signal from the time when the lower data of the read data is input to the register.

This greatly contributes to the provision of a data processor which executes a read modify write instruction at high speed and its performance improvement.

[Brief description of drawings]

FIG. 1 is a principle diagram of a data processor and a data processing method according to the present invention.

FIG. 2 is a configuration diagram of a data processor according to an embodiment of the present invention.

FIG. 3 is a waveform diagram of a read-modify-write operation at the time of accessing a DRAM according to the embodiment of the present invention.

FIG. 4 is a waveform diagram of a read-modify-write operation when accessing the PSRAM according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a data processor according to a conventional example.

FIG. 6 is an operation explanatory diagram (1) of the data processor according to the conventional example.

FIG. 7 is an operation explanatory diagram (2) of the data processor according to the conventional example.

[Explanation of symbols]

 11 ... Memory control means, 12 ... Data processing means, 12A ... First register, 12B ... Calculation section, 12C ... Second register, 12D ... Data control section, SX ... Memory selection signal, CLK ... Reference signal, ADR ... Address, DATA ... Data, T ... Data read / write period.

Claims (6)

[Claims] 1. Data is read from a storage address of an information storage device (13) based on a reference signal (CLK), and
Memory control means (11) for writing the processed data to the same storage address of the information storage device (13), and data processing means for processing the data read from the information storage device (13) ( 12) A data processor comprising: 2. The data processing means (12) stores a first address for writing and reading the data.
Register (12A), a computing unit (12B) for computing the data, and a second register (12) for storing the data.
C) and the reference signal (CLK), the memory control means (11), the first register (12A), the arithmetic unit (12).
B) and a second controller (12C) and a data control unit (12D) for controlling input and output.
The described data processor. 3. The memory control means (11) selects at least one of a dynamic random access memory (DRAM) and a pseudo static random access memory (PSRAM) based on a memory selection signal (SX). The data processor of claim 1, wherein the data processor is a data processor. 4. A series of operations for reading data from a storage address of the information storage device (13) and writing the processed data to the same storage address of the information storage device (13), by using a reference signal (CLK). A data read / write period (T) defined by a unit cycle is allocated, and at least in the first half of the data read / write period (T), a row address for selecting a word line at a storage address of the information storage device (13) is output. Then, the column address for selecting the bit line of the information storage device (13) is output in the latter half of the data read / write period (T) following the output of the row address. 5. The information storage device (1) at least in the first cycle of the data read / write period (T).
A row address for selecting the word line of the storage address of 3) is output, and a column address for selecting the bit line of the storage address of the information storage device (13) in the second cycle of the data read / write period (T). Is output, data is read from the storage address of the information storage device (13) in the third cycle of the data read / write period (T), and data is read in the fourth cycle of the data read / write period (T). And write the calculated data to the same storage address of the information storage device (13) using the fifth cycle of the data read / write period (T) from the end of the calculation of the data. The data processing method according to claim 4, wherein: 6. A series of operations for reading data from a storage address of the information storage device (13) and writing the processed data to the same storage address of the information storage device (13), using a reference signal (CLK). A data read / write period (T) defined by a unit cycle is allocated, and at least the first to fifth cycles of the data read / write period (T) specify the storage address of the information storage device (13). The address is output, data is read from the storage address of the information storage device (13) in the third cycle of the data read / write period (T), and the data is read in the fourth cycle of the data read / write period (T). The information storage device is operated by operating data and using the fifth cycle of the data read / write period (T) from the end of the data operation. In the same storage address of 3), a data processing method, wherein a writing operation data.