JP3389152B2 - DRAM control circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a DRAM (Dynamic
Random Access Memory) DRAM control circuit for generating address-related signals, especially DR for generating DRAM address-related signals based on signals output from CPU
It relates to an AM control circuit.

[0002]

2. Description of the Related Art A conventional DRAM control circuit is shown in FIG. 11 and its timing chart is shown in FIG.

The conventional DRAM control circuit includes an address switching circuit 902, an address decoder circuit 903, and an RAS / C.
It is composed of an AS generation circuit 904. The address decoding circuit 903 determines whether or not the address on the address bus output by the CPU 901 is within the DRAM address area, and the determination result is / CS-DRAM (the first "/" in the signal name indicates negative logic). The same applies hereinafter). The RAS / CAS generation circuit 904 outputs / RAS, / CAS with the CPU-ASTB (Address Strobe) output by the CPU 901 as a time reference, and ADD- for switching between a row address and a column address.
Output SEL. The address switching circuit 902 uses ADD
RAM-A by switching between upper and lower addresses ADD0 to 19 output from the CPU 901 by the SEL signal
Output as DD0-9.

FIG. 12 is a circuit diagram showing the internal structure of the RAS / CAS generation circuit. The circuit shown in FIG. 12 inputs the address switching signal ADD-SEL to the selector S of the selector circuit (IC8) in FIG.

The operation of the conventional RAS / CAS generation circuit shown in FIG. 12 at the time of writing or reading will be described with reference to FIGS. 12 and 13.

At time A0, / MRD (or / MW
When R) changes from LOW to HIGH, the output Q of the flip-flop FP4 becomes LOW, so the flip-flops FP5, FP6, and FP7 are preset, and their outputs Q become HIGH. Also, at this time / REFR
Q is HIGH. Therefore, at this time, / RAS, / C
AS and ADD-SEL are HIGH.

At time A1, CPU-ASTB goes high.
Since it becomes IGH, the output of the flip-flop FP4 is preset. At time A2 to A3, CPU-AS
TB becomes LOW, so the output of IC12 is H
IGH, flip-flops FP5, FP6, FP
The preset signal 7 is inactive.

At time A2, / CS-DRAM goes low.
When OW becomes / REFRQ is HIGH, so IC1
The output of 3 becomes LOW. Therefore, at time A3,
/ RAS becomes LOW, and ADD-S at time A4
EL becomes LOW, and / CAS becomes LO at time A5.
W.

At time B1, / MRD (or / MW
When R) changes from LOW to HIGH, the output Q of the flip-flop FP4 becomes LOW, so the flip-flops FP5, FP6, and FP7 are preset, and their outputs Q become HIGH. Also, at this time / REFR
Q is HIGH. Therefore, at this time, / RAS, / C
AS and ADD-SEL are HIGH.

In the conventional circuit, the CPU 901 has a DRAM
To access 905 with zero wait, use / R
The falling edge of AS is the last CLKOUT of cycle T1.
At the same time as the falling edge (A3) of ADD-SEL and the rising edge (A3) of CLKOUT during cycle T2.
Simultaneously with 4), / CAS falling edge is cycle T2
At the same time as the last falling edge of CLKOUT (A5).

The active conditions of / RAS and / CAS in the conventional circuit will be described. As shown in FIGS. 11 and 12, the condition under which / RAS falls is CPU-AST.
That is, / CS-DRAM changes from HIGH to LOW when B is HIGH. / CS-DRAM is a CPU
It is generated by performing address decoding of the address bus signal 901, and becomes LOW when the address of the DRAM 905 is selected. / RAS is a signal obtained by inverting CLKOUT output by the CPU 901 with the IC 11 / CLK−.
It falls in synchronization with the rise of OUT. The condition for / RAS to rise is that / MRD and / MWR become inactive. / CAS falls in synchronization with the rise of / CLK-OUT after / RAS becomes LOW. The condition that / CAS rises is the same as the condition that / RAS rises.

The refresh method in the conventional circuit is shown in FIG.
As shown in FIG. 4, it is a CAS before RAS system. / R
The generation of AS and ADD-SEL is the same as that at the time of reading / writing, so the description is omitted. In addition, lead /
At the time of writing, / CS-DRAM transits to active at time A2, but at the time of refreshing, / REFRQ transits to active at time A2 instead. Therefore, via IC13, to the D input of FP5,
At the time of refresh, the same signal as that at the time of read / write is input. / REFRQ is input to IC14, so IC14 falls before / RAS / CA
S is generated.

[0013]

The conventional DRAM control circuit shown in FIGS. 11 and 12 has the following problems.

The first problem is that the conventional circuit has a DRAM 90.
In order to cause the fall of / RAS at the time of reading / writing to 5 at time A3, it is necessary to minimize the propagation delay of IC9, IC12, and FP5 that influence the generation of the / RAS signal.

The reason is that in order to cause the fall of / RAS in the conventional circuit to occur at time A3, CPU-AST is required.
IC1 of the signal obtained by inverting B with IC9 and the output Q of FP4
The logical product signal by 2 must be HIGH before the time A3, and therefore, the IC9, I
Unless the propagation delay of C12 and FP5 is minimized,
This is because the elapsed time from the time A2 of the fall time of the CPU-ASTB must be shorter than the original elapsed time of the CPU.

The second problem is that the conventional circuit has a plurality of DRAs.
If M is attempted to be controlled, the circuit scale becomes large, which is an obstacle to downsizing the circuit.

The reason is that the RAS / C in the conventional circuit is used.
IC 13, FP5, FP in the AS signal generation circuit 904
6, FP7, IC14 are circuit configurations necessary for controlling one DRAM, and when controlling a plurality of DRAMs, IC13, FP5, FP6, FP7, IC1
This is because a plurality of 4 are required.

The object of the present invention is to simplify the circuit configuration,
An object is to provide a DRAM control circuit that operates at high speed and has a small circuit scale.

[0019]

A DRAM control circuit according to the present invention includes a clock output from a CPU (Central Processing Unit) and a trailing edge of a first clock in a write cycle or a read cycle. A DRAM (Dynamic Random Random) is activated based on an address strobe signal that becomes active and becomes inactive after the first rising of the clock and an address signal that changes when the address strobe signal changes from inactive to active.
In the DRAM control circuit for generating a control signal for the m access memory (dynamic random access memory), the address strobe signal becomes active and becomes inactive at the same time based on the clock and the address strobe signal. , RAS signal generation means for generating an RAS (Row Address Select) signal which becomes active at the second falling edge of the clock in the write cycle or the read cycle, and based on the clock and the RAS signal An address selection signal generating means for generating an address selection signal that changes from a row address select to a column address select at the rising edge of the second clock of the write cycle or the read cycle;
Based on the address strobe signal and the address selection signal, the address strobe signal becomes active and becomes inactive at the same time, and becomes active at the falling edge of the third clock of the write cycle or read cycle. Address Select,
CAS signal generating means for generating a row address select) signal.

Further, the DRAM control circuit according to the present invention is
In the above DRAM control circuit, the CA is synchronized with the refresh signal which changes from inactive to active at the rising edge of the first clock of the refresh cycle.
It is characterized by further comprising CAS signal changing means for activating the S signal.

Further, the DRAM control circuit according to the present invention is
In the above DRAM control circuit, the DRAM to be controlled
In a write cycle or a read cycle in which is not selected, the address selection signal maintaining means for maintaining the address selection signal as a row address select based on the address signal, and the DRAM to be controlled are not selected. In the write cycle or the read cycle, it further comprises a CAS signal maintaining means for maintaining the CAS signal inactive based on the address signal.

Further, the DRAM control circuit according to the present invention is
In the above DRAM control circuit, one RAS signal generating means is provided, and a plurality of the address selection signal generating means and the CAS signal generating means are provided.

Further, the DRAM control circuit according to the present invention is
In the above DRAM control circuit, one RAS signal generating means is provided, and a plurality of the address selecting signal generating means, the CAS signal generating means, and the CAS signal changing means are provided.

Further, the DRAM control circuit according to the present invention is
In the above DRAM control circuit, one RAS signal generation means is provided, the address selection signal generation means, the CAS signal generation means, and the CAS signal change means,
A plurality of the address selection signal maintaining means and the CAS signal maintaining means are provided.

Further, the DRAM control circuit according to the present invention is
In a DRAM control circuit that generates a RAS signal, an address selection signal, and a CAS signal based on a clock signal and an address strobe signal output from a CPU, when the address strobe signal becomes active, the RAS signal and the CAS signal are output. Make it inactive, and
Means for setting the address selection signal to a low address select; and the address selection signal for sequentially activating the RAS signal in synchronization with a change in the clock signal sequentially generated after the address strobe signal becomes inactive. To a column address select and activates the CAS signal.

[0026]

[First Embodiment] Referring to FIG. 1, a DRAM control circuit according to a first embodiment of the present invention includes a C
The PU 101, the address switching circuit 102, the address decoding circuit 103, the RAS generation circuit 104, the CAS generation circuit 106, and the DRAM 105 are provided.

The CPU 101 uses the data signals DB0 to DB15.
To and from the DRAM. Also, the CPU 101
Are address signals ADD0 to 19 and CPU-ASTB
(CPU-AddressSTroB) signal, CLK-OUT (ClocK OU
T) signal, / REFREQ (REFreshREQuest) signal, / MR
It outputs a D (Memory ReaD) signal and a / MWR (Memory WRite) signal. The address switching circuit 102 outputs the address signal A
DD0 to 19 are input, and the upper part or lower part of the address signals ADD0 to 19 is set to R depending on the value of the ADD-SEL (ADDress SELect) signal generated by the CAS generation circuit 106.
Output as AM-ADD (RAM ADDress) 0-9. The address decoder 103 has address signals ADD0-19.
Is the result of inputting and decoding / CS-DR
Outputs AM (Chip Select DRAM) signal. The RAS generation circuit 104 inputs the CPU-ASTB signal and the CLKOUT signal, and uses these / RAS (Row Address Selec).
t) signal, / RAS2 signal is generated and output. The CAS generation circuit 106 uses the CPU-ASTB signal and CLKOUT.
Signal, / CS-DRAM signal, / RAS2 signal are input, and by using these, ADD-SEL signal, / CAS (C
olumn Address Select) signal is generated and output.

Referring to FIG. 2, the RAS generation circuit 104.
Includes inverters IC1 and IC2 and D type flip-flops FP1 and FP2.

Referring to FIG. 3, the CAS generation circuit 106.
Is an inverter IC3, an OR logic gate IC4, a NAN
D logic gate IC5, D type flip-flop FP
3, AND gate IC6 is provided.

FIG. 4 shows the address decoder 103.
And an OR gate IC7.

Referring to FIG. 5, the address switching circuit 10
2 includes a 2-to-1 selector 108.

FIG. 6 shows a timing chart at the time of reading data from the DRAM 105 or writing data to the DRAM 105.

At time A0, the previous read (or write) operation (not shown) ends, and / MRD (or / MW
R) changes from LOW to HIGH. On the other hand, / MWR
(Or / RD) remains HIGH.

At time A1, address signal ADD0
~ 19 changes, CPU-ASTB goes LOW
To HIGH. At the same time, / CPU-ASTB goes high
It changes from IGH to LOW. Therefore, FP1, FP2, F
P3 is preset by / CPU-ASTB, / R
AS, / RAS2, / CAS0 become HIGH. Therefore, ADD-SEL becomes HIGH by IC4. Also, because / REFRQ remains HIGH, IC6
As a result, / CAS also becomes HIGH. ADD-SEL is H
Since it becomes IGH, the ADD0-09 signals (row address signals) are output as the RAM-ADD0-9 signals.
Also, / CS-DRAM is the address (000
00H to 3FFFFH) has been selected, it becomes LOW.

Before the time A3 has passed after the time A2 has passed, the CPU-ASTB changes from HIGH to LOW. At the same time, / CPU-ASTB becomes HIGH.

At time A3, CLKOUT goes high.
When it changes from H to LOW, / RAS becomes HI by FP1.
It changes from GH to LOW.

At time A4, CLKOUT is LOW
Becomes HIGH from / FP2, / RAS2 becomes H
It changes from IGH to LOW. Also, / CS-DRAM is L
Since it is still OW, it is possible to add ADD-SEL by IC4.
Changes from HIGH to LOW. Further, since ADD-SEL becomes LOW, ADD10 to 19 signals (column address signals) are output as RAM-ADD0 to 9 signals.

At time A5, CLKOUT goes high.
When changing from H to LOW, / REFRQ remains HIGH, so the clock of FP3 is changed to LOW by IC5.
To HIGH. Therefore, by FP3 / CAS0
Changes from HIGH to LOW. Also, / REFRQ is H
IGH remains, so by IC6 / CAS is HI
It changes from GH to LOW.

At time A8, / MRD (or / MW
R) changes from LOW to HIGH. This is the same as the operation at time A0, and the read or write operation ends therewith.

The DRAM 105 is shown in FIG.
The timing chart at the time of refreshing by AS is shown. The CAS before RAS refresh is performed when the CPU issues a refresh signal.

At time A0, the previous read (or write) operation (not shown) ends, and / MRD changes from LOW to HIGH. On the other hand, / MWR remains HIGH.

At time A1, address signal ADD0
~ 19 changes, CPU-ASTB goes LOW
To HIGH. At the same time, / CPU-ASTB goes high
It changes from IGH to LOW. Therefore, FP1, FP2, F
P3 is preset by / CPU-ASTB, / R
AS, / RAS2, / CAS0 become HIGH. Therefore, ADD-SEL becomes HIGH by IC4. Also, because / REFRQ remains HIGH, IC6
As a result, / CAS also becomes HIGH. ADD-SEL is H
Since it becomes IGH, the ADD0-09 signals (row address signals) are output as the RAM-ADD0-9 signals.
Also, since / CS-DRAM has an undefined address,
It becomes HIGH or LOW.

At time A2, / REFRQ becomes HIG.
It changes from H to LOW. At this time, since / CAS0 remains HIGH, IC6 changes / CAS from HIGH to LOW.

Before the time A3 after the time A2 has passed, the CPU-ASTB changes from HIGH to LOW. At the same time, / CPU-ASTB becomes HIGH.

At time A3, CLKOUT goes high.
When it changes from H to LOW, / RAS becomes HI by FP1.
It changes from GH to LOW.

At time A4, CLKOUT is LOW
Becomes HIGH from / FP2, / RAS2 becomes H
It changes from IGH to LOW. Also, / CS-DRAM is L
Since it is still OW, it is possible to add ADD-SEL by IC4.
Changes from HIGH to LOW. Further, since ADD-SEL becomes LOW, ADD10 to 19 signals (column address signals) are output as RAM-ADD0 to 9 signals.

At time A5, CLKOUT goes high.
Although it changes from H to LOW, / REFRQ remains LOW, so the clock of FP3 output by IC5 is HI.
It remains GH. However, / REFRQ is already LO
Since it is W, IC6 outputs / CASLOW.

At time A8, / MRD (or / MW
R) changes from LOW to HIGH. This is the same as the operation at time A0, and the refresh operation ends therewith.

The DRAM 105 is shown in FIG.
The timing chart at the time of refreshing is shown. RAS
Only refresh is performed when the CPU accesses a main memory space other than the DRAM without issuing a refresh signal.

At time A0, the previous read (or write) operation (not shown) ends, and / MRD (or / MW
R) changes from LOW to HIGH. On the other hand, / MWR
(Or / RD) remains HIGH.

At time A1, address signal ADD0
~ 19 changes, CPU-ASTB goes LOW
To HIGH. At the same time, / CPU-ASTB goes high
It changes from IGH to LOW. Therefore, FP1, FP2, F
P3 is preset by / CPU-ASTB, / R
AS, / RAS2, / CAS0 become HIGH. Therefore, ADD-SEL becomes HIGH by IC4. Also, because / REFRQ remains HIGH, IC6
As a result, / CAS also becomes HIGH. ADD-SEL is H
Since it becomes IGH, the ADD0-09 signals (row address signals) are output as the RAM-ADD0-9 signals.
Also, / CS-DRAM is the address (000
00H to 3FFFFH) is no longer selected, so HI
It becomes GH.

Before the time A3 has passed after the time A2 has passed, the CPU-ASTB changes from HIGH to LOW. At the same time, / CPU-ASTB becomes HIGH.

At time A3, CLKOUT goes high.
When it changes from H to LOW, / RAS becomes HI by FP1.
It changes from GH to LOW.

At time A4, CLKOUT is LOW
Becomes HIGH from / FP2, / RAS2 becomes H
It changes from IGH to LOW. Also, / CS-DRAM is H
Since it remains IGH, the output of IC4, ADD-
SEL remains HIGH.

At time A5, CLKOUT goes high.
When changing from H to LOW, / REFRQ remains HIGH, so the clock of FP3 is changed to LOW by IC5.
To HIGH. However, the D input (ADD of FP3
-SEL signal) remains HIGH, so / CAS
0 remains HIGH. Also, / REFRQ is also HI
Since it remains GH, the output of IC6, / CAS, remains HIGH.

At time A8, / MRD (or / MW
R) changes from LOW to HIGH. This is the same as the operation at time A0, and the refresh operation ends therewith.

[Second Embodiment] Next, a second embodiment of the present invention.
Will be described in detail with reference to the drawings.

In the second embodiment, the address decoding circuit 103 of the first embodiment has a plurality of address decoding circuits 103-.
1 to 103-n, the CAS generation circuit 106 becomes a plurality of CAS generation circuits 106-1 to 106-n, and DRA
The point that M105 becomes a plurality of DRAMs 105-1 to 105-n and ADD-SEL addition circuit 107 is added is
Different from the first embodiment. The RAS generation circuit 104 is the same as that of the first embodiment, and only one is provided in this embodiment. FIG. 1 shows a configuration example of the ADD-SEL adder circuit 107.
It shows in 0. Also, the address decode circuits 103-1 to 10-1
03-n have different address decode values.

Referring to FIG. 9, there is shown a configuration of a DRAM control circuit when a plurality of DRAMs are connected. Multiple DRA
At the time of M control, the generation of the RAS signal is generated by connecting to the CPU D
Regardless of the number of RAMs, the RAS signal generation is common to C
Input the data input D of the flip-flop (FP1) to the PU-ASTB and the signal obtained by inverting the CPU-ASTB by the inverter (IC1) to the preset PR of the FP1, and input I
The FP1 output is preset to a high level and the RAS signal rises in synchronization with the fall of C1. The falling edge of the RAS signal is a signal obtained by inverting CLKOUT output from the CPU by an inverter (IC2), and is asynchronous with the inversion of CLKOUT of CPU-ASTB and falls at (A3).
The rising edge of the RAS signal indicates the CPU-A of the next cycle.
When STB rises, FP1 is preset by the output of IC1 and rises.

The CAS signal is generated by the CS from the address decoding circuits corresponding to the number of DRAMs connected to the CPU.
-DRAM signals and CAS signal generation circuits corresponding to the number of DRAMs are required, but the CAS signal generation circuits all have the same circuit configuration. When the CS-DRAM is at the low level after the CPU-ASTB has fallen to the low level and the CS-DRAM is at the low level, the FP3 NAND (IC5) of CLKOUT and REFRQ causes the CAS signal to fall.
IC synchronized with the inverted signal of CLKOUT during EFRQ
By outputting 5, the fall signal is output from the AND (IC6) output when REFRQ is at the high level, and the CAS signal falls at (A4). Each ADD-
The SEL signal is input to the address adder circuit shown in FIG. 10 and ANDed (IC15) to perform address switching of the address bus signal from the CPU as one ADD-SEL signal. When the output of IC15 is high level, the address of the DRAM is A row address is output for the input, and a column address is output for the address input of the DRAM when the output of the IC 15 is low level. The rising edge of the CAS signal rises when the FP3 is preset in synchronization with the rising edge of the CPU-ASTB.

The DRAM is refreshed by RE of the CPU.
The output obtained by ANDing (IC6) the FRQ output and the output of FP3 is used, and when REFRQ is requested by the CPU, it falls at (A2) before the fall of RAS (A3), and CA
S Before RAS refresh operation is performed. When the REFRQ request is not issued from the CPU, the RAS only refresh operation is performed by the output of FP3 for the DRAM when the DRAM is not selected by the address decoding.

[0062]

As described above, the present invention has the following effects.

The first effect is that the RAS / CAS timing creation does not require the creation of critical timing. Therefore, stable operation can be realized in the circuit design. The reason is that since the signal output from the CPU is used, a signal dependent on the CPU can be created.

The second effect is that the circuit configuration is simplified and a circuit having a small circuit scale can be provided. The reason is that since the signals are commonly used in the RAS timing creation, the individually created RAS signal generation circuit becomes unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DRAM control circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a RAS generation circuit 104 of FIG.

FIG. 3 is a diagram showing a CAS generation circuit 106 in FIG.

4 is a diagram showing a configuration example of an address decoding circuit 103 in FIG.

5 is a diagram showing a configuration example of an address switching circuit 102 in FIG.

6 is a timing chart at the time of reading / writing of the DRAM control circuit of FIG.

7 is a CAS before RA of the DRAM control circuit of FIG.
FIG. 7 is a timing diagram at the time of refreshing with S.

8 is a timing diagram of the DRAM control circuit of FIG. 1 during RAS only refresh.

FIG. 9 is a block diagram showing a configuration of a DRAM control circuit according to a second embodiment of the present invention.

10 is a diagram showing an ADD-SEL adder circuit 107 in FIG. 9;

FIG. 11 is a block diagram showing a configuration of a DRAM control circuit according to a conventional technique.

12 is a diagram showing a configuration of a RAS / CAS generation circuit 904 of FIG.

13 is a timing chart at the time of reading / writing of the DRAM control circuit of FIG.

14 is a timing diagram at the time of refreshing the DRAM control circuit of FIG.

[Explanation of symbols]

101 CPU 102 address switching circuit 103 address decoding circuit 104 RAS generation circuit 105 DRAM 106 CAS generation circuit

Claims (7)

(57) [Claims] 1. A clock output by a CPU (Central Processing Unit) and a clock, which becomes active after the first falling of the write cycle or the first clock of the read cycle, and after the first rising of the subsequent clock. Based on an address strobe signal that becomes inactive and an address signal that changes when the address strobe signal changes from inactive to active, a DRAM (Dynamic Ran
dom access memory, dynamic random access memory) in a DRAM control circuit for generating a control signal, based on the clock and the address strobe signal, the address strobe signal becomes active and becomes inactive at the same time. RAS signal generation means for generating a RAS (Row Address Select) signal which becomes active at the second falling edge of the clock in the write cycle or the read cycle, and based on the clock and the RAS signal An address selection signal generating means for generating an address selection signal that changes from a row address select to a column address select at the rising edge of the second clock of the write cycle or the read cycle; the clock; Strobe signal , On the basis of the address selection signal, the address strobe signal is at the same time as inactive when it comes to active, the write cycle or becomes active at the falling edge of the third clock of the read cycle CAS (Colum
n address select, row address select) CAS signal generating means for generating a signal. 2. The DRAM control circuit according to claim 1, wherein the C signal activates the CAS signal in synchronization with a refresh signal which changes from inactive to active at a rising edge of a first clock of a refresh cycle.
DRA further comprising AS signal changing means
M control circuit. 3. The DRAM control circuit according to claim 1, wherein in the write cycle or read cycle in which the DRAM to be controlled is not selected, the address selection signal is set to a low address based on the address signal. Address selection signal maintaining means for maintaining selection, and C for maintaining the CAS signal inactive based on the address signal in a write cycle or a read cycle in which the DRAM to be controlled is not selected.
DRA further comprising AS signal maintaining means
M control circuit. 4. The DRAM control circuit according to claim 1, further comprising one RAS signal generation means, and a plurality of the address selection signal generation means and the CAS signal generation means. circuit. 5. The DRAM control circuit according to claim 2, further comprising one RAS signal generation means, and a plurality of the address selection signal generation means, the CAS signal generation means, and the CAS signal change means. A DRAM control circuit characterized by the above. 6. The DRAM control circuit according to claim 1, further comprising one said RAS signal generation means, said address selection signal generation means and said CA.
A DRAM control circuit comprising a plurality of S signal generating means, the CAS signal changing means, the address selecting signal maintaining means, and the CAS signal maintaining means. 7. A DRAM control circuit for generating a RAS signal, an address selection signal, and a CAS signal based on a clock signal and an address strobe signal output from a CPU, wherein the RAS signal is activated when the address strobe signal becomes active. And means for making the CAS signal inactive and making the address selection signal a low address select, in synchronization with a change in the clock signal sequentially generated after the address strobe signal becomes inactive. The RAS signal is sequentially activated, the address selection signal is switched to the column address select, and the C
A DRAM control circuit comprising: means for activating an AS signal.