JP2903413B2 - DRAM refresh control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM refresh control method, and more particularly, to a DRAM refresh control method capable of reducing a delay in CPU access due to refreshment.

[Related Art] Conventionally, in DRAM refreshment, refreshment is performed for a required refreshment cycle number n defined by the standard during a refreshment interval t _REF defined by the standard. For example, in the case of a 1 Mbit DRAM, since the refreshment interval t _REF = 8 ms and the required number of refreshment cycles n = 512, 15.63 μs (= 8 ms / 51)
Refreshment is performed every two cycles).

If the refreshment conflicts with the access from the CPU, the refreshment is prioritized and the access is made to wait.

FIG. 6 shows this, in which a refresh request RQ of 512 cycles is issued within 8 ms, and when there is no access request AQ from the CPU, a refresh signal r is generated in response to the refresh request RQ. The DRAM is refreshed according to the refresh signal r.

On the other hand, when there is an access request AQ from the CPU and it does not overlap with the refresh request RQ, an access signal a is generated according to the access request AQ, and the access signal a allows the CPU to access the DRAM.

When the refresh request RQ and the access request AQ conflict (for example, RQ512 and AQ03), the refresh request RQ is given priority and the refresh signal r is generated. Access request
AQ is waiting, after the refreshment is over,
An access signal a is generated.

[Problems to be Solved by the Invention] As described above, conventionally, when a refreshment and an access from the CPU overlap, the refreshment has priority and the access is awaited.

However, delaying access from the CPU has a problem of processing overhead. In particular, if a refreshment is interrupted while accessing using the high-speed page mode or static column mode, the ▲ ▼ must be made inactive once, causing a large access delay and a large processing overhead. I was

SUMMARY OF THE INVENTION An object of the present invention is to provide a DRAM refresh control method that can reduce access delay due to refreshment.

[Means for Solving the Problems] The DRAM refresh control method according to the present invention provides a DRAM having a refreshment interval t _REF and a required refreshment cycle number n for a period T = t _REF. The configuration is characterized in that refreshment is performed with n + X (where X is a natural number), and when contention with access occurs, the refreshment is waited for a maximum standby time _Wmax = XT / M, and the access is prioritized. Is what you do.

[Operation] According to the DRAM refresh control method of the present invention, the period T equal to the refreshment interval t _REF is determined by the DRAM standard.
During this period, refreshment is performed with a cycle number M which is X cycles larger than the required refreshment cycle number n according to the DRAM standard.

When refreshment and access conflict,
Access is prioritized during the maximum wait time W _max , so the CPU
Access delay and overhead is eliminated.

Here, since the maximum standby time W _max = XT / M, when the refreshment is waited up to the maximum standby time W _max , the number of cycles of the refreshment is MX, but M = n + X. Thus, the required refreshment cycle number n can be secured, and the stored contents of the DRAM are not lost.

When the access from the CPU continues for the maximum standby time _Wmax or more, the access of the CPU is delayed. However, this is the same as the conventional case, and does not deteriorate. In addition, since the frequency of continuous access by the CPU for such a long time is low, in practice, access is hardly delayed by refreshment.

[Example] Hereinafter, the present invention will be described in more detail based on an example shown in the drawings. It should be noted that the present invention is not limited by this.

FIG. 4 is a block diagram of a processing system 1 that implements the DRAM refresh control method of the present invention. The refresh is performed by the ▲ ▼ only refresh method.

In this processing system 1, a bus 2 includes a CPU 3,
Via the access request circuit 4 and the memory controller 6
DRAM7 is connected.

The arbiter 5 arbitrates contention between the access request AQ from the access request circuit 4 and the refresh request AQ from the refresh request circuit 8, and supplies an access signal a or a refresh signal r to the memory controller 6. This operation will be described later.

The memory controller 6 causes the CPU 3 to access the DRAM 7 when the access signal a is input, and refreshes the DRAM 7 when the refresh signal r is input.

For the sake of explanation, DARM7 refresh interval t
_REF = 8 ms and the required refreshment cycle number n = 512.

The refresh request circuit 8 generates a refresh request R with a cycle number N = n + X = 512 + 1 during a period T = t _REF = 8 ms.
Output Q That is, the refresh request RQ is output every 15.59 μs (8 ms / 513 cycles).

The arbiter 5 outputs the access signal a when the access request AQ is input when the refresh request RQ is not input. When the refresh request RQ is input, the operation is performed by an interrupt as shown in the flowchart of FIG.

In step S1, it is checked whether an access request AQ has been input at the same time. Step if not entered
Proceed to S2 to output a refresh signal r.

If the conflicting access request AQ has been input, the process proceeds to step S3, and it is determined whether or not the interrupt is in a standby loop. The standby loop refers to a loop in which the output of the refresh signal r is kept waiting until the access request AQ disappears in step S5.

Step if not interrupt in wait loop
At S4, access is prioritized, and an access signal a is output. Then, in step S5, the process waits until the access request AQ disappears, and when the access request AQ disappears, the process proceeds to step S6, and outputs the refresh signal r.

On the other hand, if it is determined in step S3 that the interrupt is in the standby loop, the process proceeds to step S7, and the refresh signal r is output with priority given to the refreshment. After the refreshment is completed, the access signal a is output.
That is, in this case, the access of the CPU 3 is delayed.

FIG. 2 is a schematic diagram for explaining the processing of steps S1 to S6 (step S7 is not performed).

The refresh request RQ is output for 513 cycles during 8 ms, and when there is no conflicting access request AQ, the refresh signal r is output in response to the refresh request RQ (for example, RQ001).
Is output.

When the access request AQ is input when there is no refresh request RQ, the access request AQ (for example, AQ01 and AQ0)
The access signal a is output according to 2).

Refresh request RQ (for example, RQ513) and access AQ
(For example, AQ03), the access request AQ (for example,
AQ03) has priority, and the access signal a is output. Thereafter, if the access request AQ (for example, AQ04 and AQ05) continues, the access signal a is continuously output, and after the access request AQ disappears, the request request RQ (for example, RQ
A refresh signal r based on 513) is output.

In this case, the refreshment of 513 cycles is performed within 8 ms, so that the requirements of the standard of the DRAM 7 are satisfied, and the stored contents of the DARM are not lost. Moreover, the access request AQ is not delayed.

Next, FIG. 3 shows a process performed from step S1 to step S7. That is, the access request AQ is 15.59μ
This shows a case in which s (8 ms / 513 cycles) or more continues.

The refresh request RQ (eg, RQ513) competing with the access request AQ (eg, AQ03) has a maximum waiting time W _max = XT / M =
1 × 8 ms / 513 cycles = 15.59 μs, but when the maximum waiting time W _max is reached, the access request AQ (for example, AQ7
0), the refresh request RQ is prioritized, and the refresh signal r is output.

In this case, refreshment of 512 cycles is performed within 8 ms, which satisfies the standard of DRAM7.

The access of CPU3 will be delayed, but this third
Since there are more cases where the access requests AQ are not continuous as shown in FIG. 2 than in the case where the access requests AQ are continuous as shown in FIG. 2, the delay of the access of the CPU 3 is reduced and the processing overhead can be reduced.

FIG. 5 is a block diagram of the processing system 21 based on the before-refresh method.

In this processing system 21, the bus 2, the CPU 3, the access request circuit 4, the arbiter 5, the DRAM 7, and the refresh request circuit 8 are the same components as the corresponding components in FIG.

The difference is that a refresh counter 28 that counts a refresh signal r and outputs a refresh address is provided, and that the refresh address is
In that it has a memory controller 26 for

The operation according to the present invention is the same as that described above, and a description thereof will be omitted.

[Advantage of the Invention] According to the DRAM refresh control method of the present invention, the delay of CPU access due to the overlap between refreshment and CPU access is reduced, thereby reducing processing overhead.

[Brief description of the drawings]

FIG. 1 is a flowchart of the operation according to the DRAM refresh control method of the present invention, FIGS. 2 and 3 are explanatory diagrams of the processing of the flowchart of FIG. 1, and FIG. 4 is a DRAM refresh control method of the present invention. FIG. 5 is a block diagram of another processing system for implementing the DRAM refresh control method of the present invention, and FIG. 6 is an explanatory diagram of a conventional DRAM refresh control method. (Explanation of symbols) 3 CPU, 4 Access request circuit 5 Arbiter, 6 Memory controller 7 DRAM, 8 Refresh request circuit 26 Memory controller 28 Refresh counter.

Claims (1)

(57) [Claims] 1. For a DRAM having a refreshment interval t _REF and a required refreshment cycle number n, a period T =
Number of cycles M = n + X (where X is a natural number) during t _REF
And when a conflict occurs with the access, the refreshment is made to wait until the maximum waiting time W _max = XT / M to give priority to the access.
AM refresh control method.