JP2001117862A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute a high priority program by interrupting single transfer when the high priority program is started during the execution of single transfer where DMA transfer and CPU instruction execution are alternately executed. SOLUTION: A comparing and detecting means 25 detects the occurrence of an access request form a CPU 11 in a specified address area where the high priority program is stored. A bus arbiter 17 makes a DMA controller 13 interrupt DMA transfer, a DMA address in the case of interruption is stored in a stop address register 27 and, then, a bus usage right is continuously given to the CPU 11 so that the high priority program is executed. When the priority program is completed, address data of the stop address register 27 are shifted to a start address register 19 and, then, single transfer is re-started.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer having a DMA function, and more particularly to a microcomputer having a DMA function in a single transfer mode.

[0002]

2. Description of the Related Art A large amount of data is transferred directly between an I / O device and a memory or between a memory and a memory under the control of a bus controller and a DMA controller without the intervention of a CPU in order to efficiently perform a large amount of data at a high speed. Direct memory access (DMA) transfer includes transfer modes such as single transfer, demand transfer, and block transfer. In the single transfer mode, the right to use the bus is transferred from the DMA controller to the CPU every cycle of one data transfer (bus cycle). However, if the transfer of all data from the transfer source has not been completed, the DMA controller Keeps issuing a bus use request signal, so that in the next bus cycle, the right to use the bus is transferred to the DMA controller again and the DMA transfer is performed. As described above, in the single transfer mode, when there is a DMA request, the DMA controller and the CPU alternately acquire the bus use right every bus cycle, and when there is no DMA request, the CPU has the bus use right.

FIG. 7 is a block diagram of a conventional microcomputer 1a having a single transfer mode. The microcomputer 1a includes a CPU 71, a bus controller 72 for controlling an external bus, a DMA controller 73 for determining a DMA priority and controlling a DMA request,
Address and data are transferred to CPU 71 and bus controller 7
2, the DMA controller 73 has an internal bus 74 that can transfer data to each other, and is connected to the memory 4 via an external address bus 2 and data bus 3. Although not shown, it is assumed that other memories and I / O devices related to the DMA transfer are also connected to the address bus 2 and the data bus 3.

[0004] The bus controller 72 includes a DMA address temporary register 75 indicating a transfer destination address of data to be transferred next at the time of DMA transfer, and a bus cycle generation for generating a bus cycle for each transfer time in synchronization with a CPU clock. It comprises a circuit 76 and a bus arbiter 77 for arbitrating the right to use the bus for each bus cycle. Bus Arbiter 77
Is a bus use request signal BR from the DMA controller 73.
In response to the fact that Q is active, the bus use stop signal CPUHLD is made active to the CPU 71, and the CPU 71
In response to the bus stop acceptance signal CPUAK becoming active, the bus use right is transferred to the DMA controller 73 by activating the bus use permission signal BAK to the DMA controller 73. Further, the bus use permission signal BAK to the DMA controller 73 is made inactive, and the bus use stop signal CPUHLD to the CPU 71 is made inactive, thereby returning the bus use right to the CPU 71.

[0005] The DMA controller 73 determines the priority when there are DMA requests from a plurality of devices, and controls the DMA request based on the transmission and reception of the bus use request signal BRQ and the bus use permission signal BAK with the bus arbiter 77. As shown in the memory map 4b of the memory 4, a rank control circuit 78, a start address register 79 for storing a DMA start address of the DMA target area 82, and an address counter 80 for indicating the number of remaining addresses for DMA transfer.
And a mode register 81 having a field for designating a write transfer for transferring data from the I / O device to the memory or a read transfer for transferring data from the memory to the I / O device, and a field for designating the transfer mode. In the following description, it is assumed that write transfer in which the DMA transfer destination is a memory is specified for convenience.

The number of addresses of data to be transferred at the start of DMA transfer is stored as a count value in the address counter 80, and the count value is decremented by one each time data of one address is transferred. Will always be shown. The contents of the start address register are transferred and stored in the DMA address temporary register 75 at the start of the DMA transfer, and are incremented by one each time data of one address is transferred. Holds the next transfer destination address.

If it is necessary for the microcomputer 1a to execute a high-priority program (high-priority program) such as an interrupt process during the DMA transfer in the single transfer mode, if the single transfer is continued, the microcomputer 1a can execute the program quickly. , DMA transfer is temporarily suspended and C
It is necessary to release the bus to the PU 71.

FIG. 8 is a timing chart when a single transfer is interrupted and a bus use right is transferred to the CPU. CPU7
When the high-priority program starts executing in the bus cycle i, the instruction for reading the execution state (status) of the DMA is executed in the next bus cycle (i + 1). If the transfer is being executed, the bus arbiter 7 issues a DMA transfer interruption request by the program in the next bus cycle (i + 2).
Issue to 7. In the next bus cycle (i + 3), the bus arbiter 77 inactivates the bus use permission signal BAK for the DMA controller 73 to suspend the DMA transfer, and the CPU 71 holds the bus use right from the next bus cycle (i + 4). Take.

As described above, in the conventional microcomputer, the CPU reads the state of the DMA during a program requiring quick memory access,
It was necessary to describe in advance an instruction to stop the A transfer. In this process, since several instructions are required to be executed, it takes four bus cycles to suspend the DMA transfer in the single transfer mode in the example of FIG.

FIG. 9 is a block diagram of a second conventional example described in Japanese Patent Application Laid-Open No. 9-297731, in which the problems of the first conventional example are improved. CPU 9
1 and a DMA controller 92 which is another bus master and D
When the RAM refresh controller 93 uses the address bus 94 and the data bus 95 in a time sharing manner,
A bus control register 97 having a field for designating the bus usage rate of each bus master is provided inside a bus distribution control circuit 96 for controlling the right to use the bus, so that the CPU 91 can change the bus usage rate. When an interrupt occurs, the bus distribution control circuit 96 is provided with a function of dedicating the bus to the CPU for a certain period of time. Therefore, when an interrupt occurs, the right to use the bus is transferred to the CPU 96 and execution of the interrupt program is started. . In the case of interrupt processing that is not completed within the period, it is sufficient to change the CPU 91 to increase the bus usage rate at the beginning of the interrupt program. With this configuration, when an interrupt occurs, the bus use right is automatically transferred to the CPU 91 without the need for program description or instruction input, and the CPU 91 can occupy the bus use right until the interrupt processing ends. Becomes

[0011]

In the second prior art, the CPU automatically acquires the right to use the bus during an interrupt and can use the bus preferentially during processing. There is no significant improvement over the first prior art for programs that preferentially use.
Also in the second prior art example, in a high-priority program other than an interrupt, it is necessary to change the bus utilization of the CPU at the beginning of the program in advance so that the DMA transfer is interrupted in the first prior art example. This is because there is no great difference in procedural and temporal aspects as compared with the case where the right to use the bus is transferred to the CPU.

An object of the present invention is to automatically and promptly acquire a bus use right for a program that requires not only interrupt processing but also other priority use of a bus. To provide a microcomputer which can maintain the right to use the bus during the execution of the program.

[0013]

According to a first aspect of the present invention, there is provided a microcomputer including a CPU, a DMA controller for determining a DMA priority and controlling a DMA request, and a bus controller for controlling an external bus. Equipped, said D
In a microcomputer having a single transfer mode in which an MA controller and the CPU alternately acquire a bus use right for each bus cycle, the bus controller may specify a specific address area in a memory connected to the bus. Designating means, comparison detecting means for outputting a match signal when an address accessed by the CPU is within the specific address area, and providing the DMA controller in response to generation of the match signal to the DMA controller in a next bus cycle. A bus arbiter for transmitting a first signal for instructing the use of the bus and transmitting a second signal for instructing the CPU to use the bus in the next bus cycle. According to a second aspect of the present invention, in the microcomputer according to the first aspect, the DMA controller further comprises:
A stop address register is provided for storing a DMA transfer address scheduled in a bus cycle next to the bus cycle in which the coincidence signal is generated while the DMA is stopped. A third microcomputer according to the first invention further includes the DM
The A controller includes a stop address register which starts upon receipt of the first signal and reads the address data of the DMA address temporary register and stores the read address data while the DMA is stopped. According to a fourth aspect of the present invention, in addition to the first, second, or third aspect of the present invention, the permission or prohibition of the output operation of the first signal and the second signal in response to the coincidence signal of the bus arbiter is designated. And a register having a DMA interruption permission bit for storing data to be stored.

In the first, second, third or fourth invention, the specific area designating means stores a start address register for storing a start address of the specific address area and a last address of the specific address area. A first magnitude comparator comprising a last address register, wherein the comparison and detection means outputs a logical 1 when the numerical data of the address accessed by the CPU is equal to or greater than the numerical data of the first address register A second magnitude comparator that outputs a logical 1 when the numerical data of the address accessed by the CPU is equal to or smaller than the numerical data of the last address register; and an output of the first magnitude comparator. And an AND gate which receives the output of the second magnitude comparator as an input and outputs the coincidence signal. There. Alternatively, the specific area specifying means includes a specific area specifying register for storing one of the addresses in the specific address area, and the comparing and detecting means includes a data of a predetermined number of upper bits of an address accessed by a CPU and the data. A match comparator may be configured to compare the data stored in the specific area designation register with the data of the predetermined number of higher bits and output the match signal when they match. Alternatively, the memory has a plurality of specific address areas, a plurality of specific area specifying means corresponding to each of the plurality of specific address areas, and a plurality of specific area specifying means provided corresponding to each of the plurality of specific area specifying means. CPU
A plurality of comparison detection means for outputting a match detection signal when the address to be accessed is included in the address area designated by the corresponding specific area designation means; and outputting the match detection signal from one of the plurality of comparison detection means. An OR gate that outputs a coincidence signal when input is provided.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a microcomputer according to the present invention, when a CPU issues an access request to a specific address area in which a high-priority program is stored during a single transfer in which a DMA transfer and a CPU instruction execution are alternately performed. By detecting this, the single transfer is interrupted, and the bus is released to the CPU continuously until the access to the specific address by the CPU is completed, so that the high-priority program is preferentially executed with respect to the DMA even during the DMA transfer. be able to. The high-priority program is not limited to the interrupt program, but may be a program that requires a priority use of the bus.

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a microcomputer according to the present invention and connection to an external bus and memory. Microcomputer 1
7, a CPU 11, a bus controller 12 for controlling an external bus, a DMA controller 13 for determining a priority of DMA and controlling a DMA request, and transferring addresses and data to the CPU 11. , A bus controller 12 and a DMA controller 13, which are mutually transferable, and are connected to the memory 4 via an external address bus 2 and data bus 3. Although not shown, other memories and I / O devices related to the DMA transfer are connected to the address bus 2 and the data bus 3, similarly to the first conventional example of FIG. In the following description, a case where the memory 4 is a write transfer as a DMA transfer destination will be described. However, in a case of a read transfer, the memory 4 may be read as a DMA transfer source.

The bus controller 12, as in FIG.
A bus cycle generating circuit 16 for generating a bus cycle in synchronization with the clock of the CPU and a bus arbiter 17 for arbitrating the right to use the bus for each bus cycle are provided. DMA address temporary storage circuit 1 having a DMA temporary register 28 indicating a previous address and a CPU temporary register 29 for taking in and updating via the internal bus 14 address data which the CPU 11 outputs to the address bus for accessing the outside.
5, the specific area specifying means 22 for specifying a specific address area range of the memory 4, and the address data in the CPU temporary register 29 and the address area specified by the specific area specifying means 22 are compared. When it is within the area, the match signal IDT which is output to the bus arbiter 17
And a comparison detection unit 25 that activates
The specific area specifying means 22 may be composed of, for example, a start address register 23 for registering a start address of a specific address area provided in the memory 4 and a last address register 24 for registering a last address of the specific address area. FIG.
As shown in the memory map diagram of FIG.
The start address is specified by the start address register 22 and the last address is
Is specified.

As in FIG. 7, the DMA controller 13 determines the priority when there are DMA requests from a plurality of devices and, based on the transmission and reception of the bus use request signal BRQ and the bus use permission signal BAK with the bus arbiter 17. A priority control circuit 18 for controlling a DMA request;
A start address register 19 for storing a start address;
An address counter 20 indicating the number of remaining addresses and a mode register 21 are provided.
A stop address register 27 is provided for storing an address to be transferred in the next bus cycle at the time when the single transfer is interrupted by the generation of the access request to the bus. The mode register 21 includes a field for designating the transfer direction and a field for designating the transfer mode, and also suspends the single transfer mode when an access request to the specific area 31 occurs during the DMA transfer in the single transfer mode. D to set whether to allow
An MA interruption permission bit 26 is provided.

As shown in FIG. 2, at the start of the DMA transfer,
The DMA start address of the DMA target area 30 is stored in the start address register 19, the number of addresses to be DMA-transferred is stored in the address counter 20, and the count value of the address counter 20 is decremented by one every time data of one address is transferred. To indicate the number of addresses remaining to be transferred,
The DMA temporary register 28 transfers and stores the contents of the start address register at the start of the DMA transfer.
Each time the data for the address is transferred, it is incremented by one and the next transfer destination address is held, similarly to the first conventional example of FIG.

FIG. 3 is a timing chart showing a case where a single transfer is interrupted and a bus use right is transferred to the CPU when a CPU access request to a specific area in which a high-priority program is stored. CPU1 in bus cycle i
When an access request for a specific area occurs from 1, in the next bus cycle (i + 1), the bus arbiter 17 confirms that the DMA interruption permission bit 26 in the mode register 21 is set, and the next bus cycle (i + 2) The bus arbiter 17 inactivates the bus use permission signal BAK to the DMA controller 13 and suspends the DMA. Since the CPU 11 holds the right to use the bus from the next bus cycle (i + 3), the DMA transfer in the single transfer mode can be interrupted in three bus cycles so that the CPU 11 can occupy the right to use the bus.

FIG. 4 is a flowchart showing a processing procedure from when a request to access the specific area 31 is issued to the CPU 11 to when the single transfer is interrupted and the high priority program is executed, and after the termination, the single transfer is resumed. is there. Hereinafter, FIG.
FIG. 4 will be described with reference to FIG.

First, it is assumed that an access request for the specific area 31 is issued to the CPU 11 in step 40. When this access request is generated, the comparison detection means 25 detects that the address of the CPU temporary register 29 matches the address range of the specific area 31 indicated by the specific area designating means 22, and the matching signal ID
When T becomes active, the bus arbiter 17 is notified.

In the next step 41, the bus arbiter 17
Checks whether the DMA interruption permission bit 26 of the mode register 21 is set. If the DMA suspend permission bit 26 has not been set, step 50
Then, the single transfer is continued as it is, but if it is set, the process proceeds to the next step 42. Note that the microcomputer configured to interrupt the single transfer whenever there is a request to access the specific area 30 without providing the DMA interruption permission bit 26 is executed in step 4.
1 is omitted.

In step 42, the bus arbiter 17
The bus use permission signal BAK to the MA controller 13 is made inactive to prohibit the DMA controller 13 from using the bus and stop DMA (single transfer). Next, at step 43, the address data of the DMA temporary register 28 is transferred to the stop address register 27 via the internal bus 14.
To save the next transfer destination address at the time of DMA interruption. In step 44, the bus arbiter 1
7 inactivates the bus use stop signal CPUHLD to give the CPU 11 the right to use the bus. Next, at step 45, the bus master executes the CPU cycle of the CPU.

In step 46, the bus arbiter 17
It is determined from the logical level of the coincidence signal IDT whether the address accessed by the CPU is within the specific area. When the access to the specific area is continued, the process returns to step 45 to continue the CPU cycle. When it is determined that the access to the specific area has been completed, it is considered that the execution of the high-priority program has been completed, and the process proceeds to the next step 47.

In step 47, the bus arbiter 17
The bus use stop signal CPUHLD is activated again to prohibit the CPU 11 from using the bus. Then step 48
Then, the bus use permission signal BAK is made active again to transfer the bus use right to the DMA controller 13. Next, at step 49, the address data stored in the stop address register 27 is transferred to the start address register 19, and is set as the transfer destination head address when the single transfer is restarted.
The address counter holds the number of remaining transfer addresses at the stage of step 43, and when the single transfer is restarted, the count (decrement) is restarted therefrom. After completing the preparations for restarting up to this point, the next step 50
Then, the DMA controller becomes the bus master and the DM
A transfer is performed, and the mode returns to the single transfer mode.

As described above, when returning to the single transfer mode, the stop address register 27 is provided to store the address at the time of interruption until the time of resumption, and is loaded into the start address register 19 at the time of resumption. The DMA transfer can be executed continuously without any trouble for the addresses.

FIGS. 5A and 5B are circuit diagrams of an embodiment of a partial circuit for comparing and detecting whether an address accessed by a CPU is within a specific area. In FIG. 5A, the CPU temporary register 29 stores the address data to be accessed by the CPU, and the head address register 23 in the specific area specifying means 22 stores the head address data of the address range in which the high priority program is stored. Is stored in the last address register 24. The last address data of the address range is stored in the last address register 24. Large and small comparators 51, 5
2 is that the numerical data INa input to the A input side is equal to or larger than the numerical data INb input to the B input side (INa ≧
INb) A comparator which outputs a logical 1 in the case of the above and which has such a function and compares the size of two N-bit data in parallel is disclosed in JP-A-62-266617 or JP-A-01-271834. It can be realized using the technology disclosed in the gazette. The A input side of the magnitude comparator 51 is connected to the CPU temporary register 29 and the B input side is connected to the head address register 23.
When the data value of the address to be accessed is equal to or greater than the data value of the head address of the specific area, the output of the magnitude comparator 51 becomes logic 1. On the other hand, since the A input side of the comparator 52 is connected to the last address register 24 and the B input side is connected to the CPU temporary register 29, the data value of the address accessed by the CPU 11 becomes the last address of the specific area. When equal to or less than the data value, the output of the magnitude comparator 52 is a logical one. Therefore, the output of the magnitude comparator 51 and the magnitude comparator 52
The match signal IDT, which is the output of the AND gate 53 that receives the output of the first address register 23 as an input, is only when the address accessed by the CPU 11 is included in the range from the address data of the first address register 23 to the address data of the last address register 24. It becomes 1.

In FIG. 5B, the specific area specifying register 54 in the specific area specifying means 22a stores data in which the upper m bits of the n-bit address data are equal to the specific area address and the upper m bits. Keep it. That is, the data stored in the specific area designation register 54 may be the head address data of the specific area, the last address data, or the address data between them. The high-order m bits of the address data of the CPU temporary register 29 and the high-order m bits of the address data of the specific area designation register 54 are input to the comparison detection means 25a, and are compared for each corresponding bit. It becomes logic 1. Comparison detection means 25
a is, for example, m exclusive OR gates 55-1 to 55
This can be realized using a coincidence comparator composed of a NOR gate 56 having −m and m inputs. Compared to FIG. 5A, there is an advantage in that hardware can be reduced because the size comparators 51 and 52 having a larger number of constituent elements are not used.

FIG. 6 is a circuit diagram of an embodiment of a comparison and detection partial circuit of a microcomputer having a configuration in which a plurality of specific areas can be set. The first comparison / detection unit 6 determines whether the address range of the first specific region designated by the first specific region designation unit 61 matches the address data of the CPU temporary register 29.
2, the address range of the second specific area specified by the second specific area specifying means 63 and the CPU temporary register 29
The second comparison and detection means 64 compares the coincidence of the address data of the third specific area with the address range of the third specific area specified by the third specific area specifying means 65 and the address data of the CPU temporary register 29. Comparison is made by the comparison detection means 66,
Output ID of each of the first, second and third comparison and detection means
A match signal IDT is obtained as an output of the OR gate 67 to which T1, IDT2, and IDT3 are input. When the address to be accessed by the CPU 11 matches the address range specified by any of the first specific area specifying means 61, the second specific area specifying means 63, and the third specific area specifying means 65, the coincidence signal IDT becomes logical 1 Becomes When the interrupt processing program and the other high-priority programs exist, and the storage address of the high-priority program and the storage address of the data are in different areas, there is an advantage that the configuration shown in FIG. 6 can be flexibly used. is there. FIG. 6 shows a case where the number of specific regions is three, but it is clear that the number of specific regions can be easily increased to other numbers.

[0031]

As described above, in the microcomputer of the present invention, when it becomes necessary to execute a high-priority program during execution of DMA in the single transfer mode, not only interrupt processing but also other buses are required. Even for programs that require priority use, C
The PU automatically and quickly acquires the right to use the bus, maintains the right to use the bus during the execution of the program, and automatically returns to the single transfer mode when the execution of the high-priority program ends. Since it is not necessary to add a procedure for stopping single transfer and a procedure for restarting single transfer in the program, the time required to create a high-priority program can be reduced, the program size can be reduced, and single transfer can be interrupted and returned. Since the processing is performed by hardware, there is an effect that the time required for the processing can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer of the present invention.

FIG. 2 is a memory map diagram showing a specific area and a DMA target area.

FIG. 3 is a timing chart when a single transfer is interrupted in the present invention.

FIG. 4 is a flowchart of a processing procedure from interruption to resumption of single transfer in the present invention.

FIGS. 5A and 5B are circuit diagrams of partial circuits for comparing and detecting whether an address accessed by a CPU is within a specific area.

FIG. 6 is a circuit diagram of a comparison and detection partial circuit configured to be able to set a plurality of specific regions.

FIG. 7 is a block diagram of a first conventional example.

FIG. 8 is a timing chart when a single transfer is interrupted in the first conventional example.

FIG. 9 is a block diagram of a second conventional example.

[Explanation of symbols]

 1,1a microcomputer 2,94 address bus 3,95 data bus 4 memory 4a, 4b memory map 11,71,91 CPU 12,72 bus controller 13,73,92 DMA controller 14,74 internal bus 15 address temporary storage circuit 16, 76 bus cycle generation circuit 17, 77 bus arbiter 18, 78 priority control circuit 19, 79 start address register 20, 80 address counter 21, 81 mode register 22, 22a, 61, 63, 65 specific area designation means 23 start address Register 24 Final address register 25, 25a, 62, 64, 66 Comparison detection means 26 DMA interruption permission bit 27 Stop address register 28 DMA temporary register 29 CPU temporary register 30, 82 DMA target area 3 Specific regions 51 and 52 comparator 53 the AND gate 55-1,55-2,55-m exclusive OR gate 56 NOR gate 67 OR gate 75 DMA address temporary register 93 DRAM refresh controller 96 bus distribution control circuit 97 Bus Control Register

Claims (7)

[Claims] 1. A CPU and a priority order of a DMA are determined.
A microcomputer having a single transfer mode in which a DMA controller that controls an MA request and a bus controller that controls an external bus, wherein the DMA controller and the CPU alternately acquire a bus use right every bus cycle, The bus controller, a specific area specifying means for specifying a specific address area in a memory connected to the bus,
Comparison detection means for outputting a coincidence signal when an address accessed by the CPU is within the specific address area; and inhibiting the DMA controller from using the bus in a next bus cycle in response to the generation of the coincidence signal. A microcomputer comprising: a bus arbiter that transmits a first signal to instruct the CPU and transmits a second signal to the CPU to instruct the CPU to use the bus in a next bus cycle. 2. Priorities of CPU and DMA are determined and D
A microcomputer having a single transfer mode in which a DMA controller that controls an MA request and a bus controller that controls an external bus, wherein the DMA controller and the CPU alternately acquire a bus use right every bus cycle, The bus controller, a specific area specifying means for specifying a specific address area in a memory connected to the bus,
Comparison detection means for outputting a coincidence signal when an address accessed by the CPU is within the specific address area; and inhibiting the DMA controller from using the bus in a next bus cycle in response to the generation of the coincidence signal. A bus arbiter for transmitting a first signal to instruct the CPU and a second signal to instruct the CPU to permit use of the bus in a next bus cycle, wherein the bus cycle in which the DMA controller generates the coincidence signal is provided. A stop address register for storing a DMA transfer address scheduled in the next bus cycle while the DMA is stopped. 3. The CPU and the priority of the DMA are determined and
A microcomputer having a single transfer mode in which a DMA controller that controls an MA request and a bus controller that controls an external bus, wherein the DMA controller and the CPU alternately acquire a bus use right every bus cycle, An address temporary storage circuit, wherein the bus controller has a CPU address temporary register for temporarily storing an address accessed by the CPU and a DMA address temporary register for temporarily storing an address of DMA transfer;
A specific area specifying means for specifying a specific address area in a memory connected to the bus; a comparison detecting means for outputting a match signal when address data in the CPU address temporary register is in the specific address area; A first signal instructing the DMA controller to prohibit use of the bus in the next bus cycle in response to the generation of the coincidence signal, and instructing the CPU to permit use of the bus in the next bus cycle. And a bus arbiter for transmitting the second signal. 2. The DMA controller further comprises a stop address register which starts upon receipt of the first signal and reads the address data of the DMA address temporary register and stores the data while the DMA is stopped. And a microcomputer. 4. A register having a DMA interruption permission bit for storing data designating permission or prohibition of an output operation of the first signal and the second signal in response to the coincidence signal of the bus arbiter. Claims 1, 2,
3. The microcomputer according to 3. 5. The specific area specifying means includes a head address register for storing a head address of the specific address area, and a last address register for storing a last address of the specific address area; A first magnitude comparator that outputs a logical 1 when the numerical data of the address accessed by the CPU is equal to or larger than the numerical data of the first address register; A second magnitude comparator that outputs a logical 1 when the value is equal to or smaller than the numerical data of the address register; and an output of the first magnitude comparator and an output of the second magnitude comparator. And an AND gate for outputting the coincidence signal.
The microcomputer according to any one of claims 3 and 4. 6. The specific area specifying means includes a specific area specifying register for storing one of addresses in the specific address area, and the comparing and detecting means includes a predetermined number of upper bits of an address accessed by a CPU. 5. The micro-computer according to claim 1, further comprising a coincidence comparator for comparing the data with the data having the predetermined number of higher bits of the data stored in the specific area designation register and outputting the coincidence signal when the data is coincident. Computer. 7. A memory having a plurality of specific address areas in the memory, a plurality of specific area specifying means corresponding to each of the plurality of specific address areas, and a plurality of specific area specifying means corresponding to each of the plurality of specific area specifying means. A plurality of comparison detection means for outputting a match detection signal when an address accessed by the CPU is included in an address area designated by the corresponding specific area designation means; And an OR gate for outputting a coincidence signal when a coincidence detection signal is input.
4. The microcomputer according to 4.