JPS6011935A - Display device for action mode - Google Patents

Abstract

PURPOSE:To display an action mode even with a system having no action mode display function by providing a control part which stores the action mode value in a mode register and another control part which resets the shunted action mode value to the mode register. CONSTITUTION:A program P1 which is under execution in a mode M1 calls a program P2 which can be executed in a mode M2. Then an arithmetic processor 1 delivers the execution start address of the P2 to an address bus 13 as well as to a fetch signal line 14. In this case, a control part A5 detects that the value equal to the contents of a mode switching register 3 is sent to the bus 13. The contents of a register 4 for the mode value are stored in a mode register 10. Then a control part B8 detects that the value equal to the contents of a mode reset instruction register 6 is sent to a data bus 12 when the processing is reset to the P1 after the processing is through with the P2. Thus the action mode value can be reset to the M1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an operation mode display device for displaying the operation mode of an arithmetic processing unit in a microcomputer system or the like.

Conventional Structures and Problems With the development of microcomputers, microcomputer systems have also become larger, and there is a growing demand for processing contents comparable to those of small minicomputers. While it was possible to manage everything by the user while the scale of the system was small, as the scale of the system increased, it became possible to manage resources such as user programs, peripheral devices, and main memory, and to make the processing unit more efficient. It is desirable to introduce a control III program that controls the operation of the program, and to significantly reduce user management.In these four cases, user programs and control programs can be handled due to the nature of their processing contents. Resources are clearly differentiated. This point will be explained using the aspect of input/output management as an example.

A secondary storage device is a typical input/output device of a computer system. Programs and data are held in the form of files on the secondary storage device, and are recorded according to a certain format defined by the system. This fixed format is not managed by the user but by the control program, so that the user does not need to know the file format. Therefore, human output to the secondary storage device cannot be performed directly from each Rino[] program, and must be performed by i! jfjl must not be configured to mediate the wholesale program. In other words, while the user program is running, access to the input/output device is prohibited or 1j1 (enabled, 1lIIJ1111J
It is necessary to switch the control of the hardware device so that access to the input/output device is allowed only while the program is running.

In this way, in order to instruct the switching of hardware installations, there is an operation mode display device that displays whether the running program is a privileged program (a program) or a non-privileged program (a user program). It becomes necessary. This operation mode display and timing are more important than minicon beaters, but the processing unit itself has this function, but existing microprocessors that are widely used do not have this function. A major obstacle, in building high-performance microprocessor systems! : It has become. Moreover, this switching of hardware due to a change in the operating mode must be performed in hardware at the same time as the branching of the program (change in the operating mode) due to the privileged/unprivileged nature of the program. In some cases, there are 44n4 privileged modes.

OBJECTS OF THE INVENTION As described above, an object of the present invention is to provide an operation mode display device for a system in which the arithmetic processing unit itself does not have an operation mode display function.

Structure of the Invention The present invention comprises a mode register, a mode switching address register, a setting mode value register, a mode save register,
Equipped with a mode return instruction register, when the arithmetic processing unit accesses the same address as the contents indicated in the mode switching address register as an instruction code read cycle, the contents of the mode register are stored in the mode save register, and after storing, the setting mode value register is The operation mode value is changed by storing the contents in the mode register, and after the arithmetic processing unit reads the same instruction as the contents indicated in the mode return instruction register, the contents of the mode save register are returned to the mode register in N operation cycles (]. By storing it, the operation mode is displayed.

DESCRIPTION OF EMBODIMENTS FIG. 1 shows an embodiment of an operation mode display device according to the present invention. In FIG. 1, 1 is an arithmetic processing unit, 2 is a main memory bag U'1.12 (-↓ data bus line, 13-digit address line), 3 is a mode switching address register,
4 indicates a setting mode value register, 6 indicates a mode return instruction register, and 14 indicates that the arithmetic processing unit 61 is accessing the main memory bag d2 as an instruction code reading cycle.
Instruction reading status display signal line (hereinafter referred to as fetch signal port), 10id mode register, 111'i mode J
IJ register, 5 is the control unit A, 3 which is the first control unit
(The second control unit is the control unit B, 7 is a return delay value register, 8 is a sub-control unit B, and 9 is a return delay counter unit. A pair of an address register, a set mode value register, and a pair of an auxiliary control cape B, a return delay value register, and a mode return address register present in the 8 control lances are each set as one set.

Currently, the arithmetic processing unit 1 is executing program P1 that is allowed to run in mode M1, branches to program P2 that is allowed to run in mode M2, and branches to program P2 that is allowed to run in mode M2.
After completing the processing in step 2, return to program P1 and enter mode M1.
Consider the case where processing continues with . Since the currently running program P1 is allowed to execute in mode M1, the value Ml is stored in the mode register OK at the same time as the execution of program P1 starts to indicate that the operating mode is Ml. has been done. The mode switching address register 3 contains the execution start address of the program P2, the setting mode value register 4 contains the mode value M2 at which execution of the program P2 is permitted, and the mode return command register 6 contains the light after the processing of the program P2 is completed. An instruction code (for example, LPSW, RET, etc.) for returning to the program P2 is specified in the mode return delay value register 7 to indicate that the operation mode should be returned at the Nth instruction code read cycle after execution of the return instruction from program P2. Therefore, the value N is set in advance by means not shown in each figure. It is also assumed that the arithmetic processing unit 1t1 can read and write the contents of the mode save register 11 by means not shown.

When the fetch signal line 14 is 1'', the control unit A5 compares the register contents with the value of the address bus 13 and the motrif exchange number, and if they match, detects a match and sends the code to the mode switching signal line 15.
The contents of the mode register 10 are saved to the mode register 10 via the mode display signal line 21, transferred to the register 11, and the contents of the register 4 are transferred to the mode register 1o via the setting mode data line 2o. 'J Fai
jf: has. Sub JilJ control part B8 is fetch signal line 1
4 or 1'', the value of data 1q line 12 (processing unit 1
(represents the instruction code being read) and the contents of the mode return instruction register 6, and if they match, a match detection code is output to the mode return detection signal line 16, and the contents of the mode return delay value register 7 are It is transferred to the mode return delay counter section 9 via the return delay data line 23.

The mode return delay counter section 9 is initialized to the value indicated by the return delay data line 23 in synchronization with the time when the value of the mode return detection signal line 16 changes from 1'' to "0" (at the time of falling). The value is decremented by 1 in synchronization with the fall of the fetch signal line 14, and the value of the fetch signal 14 that occurs during the period when the counter value is 1 is transmitted to the mode return signal line 17, and the value of the mode return signal line 17 is It has a function of transferring the counter value to the mode register 10 when it becomes '1''', and when the counter value becomes ◯, the operation of the mode return delay counter section 9 is stopped.

The operation of the mode return delay counter section 9 will be explained below. Fig. 3 shows a schematic diagram of a case where a program P1, which is allowed to execute in operation mode M1, branches to a program P2, which is allowed to be executed in operation mode M2, and returns to program P1 after completing processing in program P2. Show the diagram. Considering the relationship between the operating mode value and the program execution permission mode, the fact that the program Pi is allowed to execute with the operating mode value Mi means that the program P
1 is in operation, the value of the operation mode value Mi must be guaranteed (i=1.2). When branching from program l+P1 to program P2, program P1, operation mode value M1, and program P
2 and the operation mode value M2.

be done. However, when returning from program P2 to program P1, if the operation mode value is returned to Ml when program P2 returns to program P1,
The operation mode value becomes Ml even though the 1 summer return instruction is being executed, and the correspondence between the program P2 and the operation mode value M2 cannot be guaranteed.

Therefore, after program P2 fetches the return instruction,
A series of recovery procedures are completed and Zologra 1. It is necessary to control so that the operation mode value for the period up to the immediate restart P14 is M2, and the mode return delay counter section fulfills this function.

When a program P1 running in mode M1 calls a program P2 executable in mode M2, the arithmetic processing unit 1
outputs the execution start address of the program P2 to the address bus 13 and simultaneously outputs 1'' to the fetch signal line 14. At this time, the control unit A5 outputs the same value as the content of the mode switching address register 3 to the address bus 13 to fetch the instruction. The output in the cycle is detected, and one of the mode registers 10 is stored in the mode save register 11 by the above-described function, and the content M2 of the set mode value register 4 is stored in the mode register 10. As a result, the operation mode display value of the arithmetic processing unit 1 can be changed from Ml to M2 at the same time as the program control is branched from the program P1 to the program P2.Next, the processing of the program P2 is completed and the program returns to the program P1. When the sub-control unit B8 stores the same value as the content of the mode return command register 6 in the main memory 2,
detects that the instruction is output to the data bus 12 in the fetch cycle, and uses the above-mentioned function to transfer the content N of the mode return delay value register 7 to the mode return delay counter section 9, and then performs the subsequent N-th fetch. When the signal is output, the content M1 of the mode save register 11 is set to the mode register 1o.
The operating mode value can be returned to Ml.

As described above, according to Implementation 11, even in a computer system using an arithmetic processing unit that does not have an operation mode display function, programs and hardware, which are defined by the operation mode, can be switched at the same time. (This can be done without branching to a block with a different mode, and can prevent unauthorized mode changes and gaining access rights to resources that are not allowed to be accessed. In this example, the mode switching address It is also possible to configure the register, the rise mode value register, and the control unit as one set or to have a separate function.

Furthermore, if multiple operating modes are defined, when the program is called, the contents of the mode save register are read and saved to the work 1111 area, and the contents of the saved work area are stored in the ilT and mode save registers before returning. By doing so, it is also possible to nest the operating modes themselves in the same way as the programs themselves. The mode of the calling program can be confirmed by referring to the contents of the mode save register, so if the operating modes form a hierarchical structure, an illegal call can be avoided, and if the tree is Ml-M2-M3 from the lower level. It is possible to detect jump calling of the M3 program from the M1 program in the event of a jump call.

Note that the input signal that decreases the value of the return delay counter section is not limited to the fetch signal.

Effects of the Invention The operation mode display 4AIf of the present invention detects that the arithmetic processing unit accesses a preset address as an instruction code read cycle, and stores the operation mode value defined in that case in the mode register. By implementing the first control unit and the second control unit that detects reading of a return instruction and restores the saved operation mode value to the mode register 111H, an arithmetic processing unit without an operation mode display function can be used. Even in a computer system using a computer system, the operation mode display value can be changed at the same time as processing is transferred to a program with a different operation mode.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an operation mode display device in an embodiment of the present invention, FIG. 2 is a timing chart 1 showing the operation of the mode return delay counter section in diagram g1, and FIG. 31 is a relationship between operation mode values and programs. This is the second school map showing. 1... Arithmetic processing unit 112... Above ↑,
・Device, 3...Mode switching address register, 4...-
...Setting mode value register, 5... City IJ + month 1 part A (first city 1''ll111 part), 6...
・Mode return command register, 7...7-T return delay value register, 8...Sub-control unit B, 9-...Mode return delay counter unit, 10--Mode register, 11-
---Mode save register, 30---11i111d1
1 part B (second control part).

Claims (4)

[Claims] (1) The above-mentioned disease of a computer system including an arithmetic processing unit and a main storage device that stores a program executed by the arithmetic processing unit is 1. A mode register that displays the operating mode of the processing device, a mode switching address register, a setting mode value register, a mode save register, and an address value that the arithmetic processing device outputs as an instruction code read cycle from the main storage device. and the contents of the mode switching address register are compared, and if they match, the contents of the mode register are stored in the mode save register, and after storing, the contents of the setting mode value register are all stored in the mode register written in FJ. comparing data (instruction code) when the control unit and the arithmetic processing unit access the unique device as an instruction code reading cycle with a return instruction code;
An operation mode display device comprising: a second control block that stores the contents of the mode save register in the mode register at the Nth operation cycle of the arithmetic processing unit that occurs after a match is detected. (2) Mode switching address register, setting mode value register, first control
An operation mode display device according to claim (1). (3) The operation mode display device according to claim 1, wherein the unit of N is an instruction code reading cycle of an arithmetic processing unit. (4) il+i21fff of a patent claim characterized in that the unit of N is a machine cycle possessed by an arithmetic processing device t.
The operation mode display device according to item (1) or item (2).