JPH0528038A - Cache memory control system - Google Patents

Abstract

PURPOSE:To adopt a multiprocessor electronic computer to use a cache memory space without dividing by providing a specific data cache memory control mechanism. CONSTITUTION:In a processor 1, when a CPU does not set a store through control inhibit flag to a store through control inhibit flag register 10, the writing on a memory 5 of the CPU4 is performed simultaneously with the writing on the data cache memory 2 and the writing on the memory 5 so as to maintain the data coincidence between the data cache memory 2 and the memory 5. When a store through control inhibit flag is set to a store through control inhibit flag register 10, the memory writing from the CPU 4 for the data block of the data cache memory 2 controlled by this store through control inhibit flag performs the operation as an exclusive memory for the data cache memory 2, not for the memory 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control system, and more particularly to a cache memory control system for a multiprocessor computer having a plurality of processors each having a built-in cache memory.

[0002]

2. Description of the Related Art Scientific and technological calculations using electronic computers include calculations by the finite element method. As an example, in building structure calculation, a structure is subdivided into calculation elements, the influence between calculation elements is given as a boundary condition, and exactly the same calculation is performed for the calculation elements.

In such scientific and technological calculation, in the conventional single processor type electronic computer, calculation for the calculation elements was sequentially performed for the number of calculation elements.

In a multiprocessor type computer,
In order to increase the calculation speed, the memory space used for each processor is divided and the calculation for the calculation elements is performed in parallel.

In a parallel processor type computer in which independent processors each having a dedicated memory are connected to each other by a memory or a bus connection, the processor has its own dedicated memory. In the case of a multiprocessor type electronic computer, the calculation of calculation elements was performed in parallel by the multiprocessors without the need to divide the space used by the memory.

Further, in each of the above-mentioned electronic computers,
By providing a cache memory that has an access time faster than that of the memory, the memory access speed of the processor is increased, the calculation speed of the processor is increased, and the time required for calculation of the calculation elements is shortened. In the conventional cache memory control method at this time, in the case of a multiprocessor type electronic computer, since calculation is performed in parallel on the calculation elements, the memory space to be used is divided and used for each processor. For this reason, the cache memory added to each processor cannot be treated as a local memory of the processor itself because of the data consistency guarantee function of the memory, which is the original function of the cache memory. The memory space was divided and used for each processor.

[0007]

When the conventional cache memory control method described above is applied to a multiprocessor type electronic computer, the calculation time can be shortened because calculation can be performed on the calculation elements in parallel, but it is used in advance. Memory space must be divided for each processor,
In addition, even if a cache memory is added to each processor, the cache memory cannot be treated as a local memory of the processor itself due to the function of guaranteeing data consistency with the memory, which is the original function of the cache memory. The memory space must be divided for each processor, resulting in a functional division loss.

An object of the present invention is to provide a cache memory control system that can be applied to a multiprocessor type computer and can be used without dividing the memory space of the cache memory.

[0009]

According to the cache memory control system of the present invention, in a multiprocessor computer having a plurality of processors, the processor has a data cache memory, a store-through control prohibition flag register, and According to the state of the store-through control prohibition flag register, store-through control for guaranteeing data consistency between the data cache memory and the memory commonly used by the plurality of processors is prohibited for each data block of the data cache memory. It is a configuration including a data cache memory control mechanism that enables it.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

The processors 1 and 6 are respectively provided with data cache memories 2 and 7, cache memory control mechanisms 3 and 8, CPUs 4 and 9, store through control prohibition flag registers 10 and 11, and a data bus 12. It is connected to the memory 5 via.

Next, the operation will be described.

In the processor 1, when the CPU 4 has not set the store-through control prohibition flag in the store-through control prohibition flag register 10, the CPU 4 causes the memory 5 to move.
In order to maintain the data consistency between the data cache memory 2 and the memory 5, the write to the data cache memory 2 and the memory 5 are simultaneously performed. Further, when the store-through control prohibition flag is set in the store-through control prohibition flag register 10, the memory write from the CPU 4 to the data block of the data cache memory 2 controlled by the store-through control prohibition flag is performed by the data cache memory. The write operation is performed only on the memory cell 2, and the write operation is not performed on the memory cell 5. Further, the data block of the data cache memory 2 in which the store through control prohibition flag is set in the store through control prohibition flag register 10 is fixed in the data cache memory 2 and is swapped out by another cache access miss from the CPU 4. Not subject. Store-through control prohibition flag register 1
By setting the store-through control prohibition flag to 0, the data block in which the flag is set can be used not as a copy of the area of the memory 5 but as a dedicated memory of the processor 1. The above operation is the same in the CPU 6.

The CPUs 4 and 6 read in advance the data block of the memory 5 to be accessed respectively, store the copy of the data block in the data cache memories 2 and 7, and then store the store-through control prohibition flag 10 therein. , 11 are set, access to each data block does not affect each other's processors, and exactly the same program is executed by the CPUs 4, 6 at the same time.
It will be possible to access each data block by running in.

[0016]

As described above, according to the present invention, each processor of a multiprocessor type computer equipped with a plurality of processors has a data cache memory, a store-through control prohibition flag register, and this store-through control prohibition. A data cache memory that can prohibit store-through control for guaranteeing data consistency between the data cache memory and the memory commonly used by multiple processors depending on the state of the flag register for each data block of the data cache memory. By providing a control mechanism to perform scientific and technical calculations such as the finite element method described above, when applied to a multiprocessor computer, the same program is run by multiple processors at the same time, Address the same memory area In order to prevent destruction of data arising from the processes, it is not necessary to the division of memory space,
Moreover, it can be equipped with the features of a parallel processor type computer, and can be used as a multiprocessor type computer with a normal cache memory if the store-through control prohibition flag is not set. It also has the effect of being easy to use.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1,6 processor 2,7 data cache memory 3,8 cache memory control mechanism 4,9 CPU 5 memory 10,11 store through control prohibition flag register 12 data bus

Claims (1)

Claim: What is claimed is: 1. In a multiprocessor type computer equipped with a plurality of processors, the processor includes a data cache memory, a store-through control prohibition flag register, and a store-through control prohibition flag register. Data cache memory control that enables store-through control for guaranteeing data consistency between the data cache memory and the memory commonly used by the plurality of processors depending on the state, for each data block of the data cache memory And a cache memory control method.