JPS63231650A - Cache memory control system - Google Patents

Abstract

PURPOSE:To improve the performance by providing with the function which retries a lock instruction to a CPU. CONSTITUTION:Plural CPUs 11-13 retry shared data access instruction on demand at the time of accessing shared data to attain the same effect as lock of shared data on cache memories 21-23, thereby to execute the instruction effectively. Cache memories 21-23 are controlled in accordance with the write back system. CPUs 11-13 have the function to retry instructions requiring lock such as an update reference instruction (TEST & SET, COMPARE & SWAP or the like) on demand.

Description

[Detailed Description of the Invention] [Summary] A main storage device and a plurality of processors are connected to a common bus, each processor has a cache memory, and when updating the contents of the cache memory, first , change only the cache memory,
After that, in a write-back multiprocessor that is controlled so that the contents of the main memory are updated when the block is returned to the main memory, changes (writes) to the shared data of each processor in the cache memory are performed. In order to maintain its identity when trying to
It is necessary to notify other processors of the invalidation of the corresponding data. Such invalidation is performed by a lock instruction or the like, and this type of instruction consists of processing of fetching common data (FETCH), then performing a test, and performing a store based on the result.

Therefore, if the result of the test is that no storage is to be performed, the invalidation process is completely wasteful, resulting in problems such as a decrease in the processing efficiency of the processor.

In order to solve these conventional problems, the present invention discloses a control method that has fewer restrictions on access to shared data from other processors when executing a lock instruction.

[Industrial Field of Application] The present invention relates to control of memory access in a multiprocessor system, and particularly relates to control of updating the content of shared data in a cache memory in a write-back system.

[Prior Art] In a multiprocessor in which multiple CPUs are connected via a common bus, the multiple CPUs write to a shared data area in their respective cache memories (STOR).
If E) is attempted, it is necessary to invalidate the shared data for other CPUs. When accessing such shared data, CPUs that follow the conventional architecture use TEST & SET, COMPA, etc.
Instructions such as RE&5WAP are used to lock shared data. It consists of 5TORE etc. according to the following. In this case, when a certain CPU is executing such an instruction, the system prohibits other CPUs from accessing the shared data between that FETCH and 5TORE using a similar instruction. .

[Problems to be Solved by the Invention] The conventional control system related to the lock command as described above has the following problems that affect performance.

That is, when executing a lock instruction, before executing that instruction, instruct other CPUs to invalidate the block containing the shared data.
If the result of testing the data is that 5TORE is not performed, invalidation by other CPUs will be in vain, and furthermore, the CPU whose block was invalidated will If you wanted to access a block, you had to FETCH that block again.

Also, after data FETCH, as a result of the data test, when performing 5TORE to the shared data area, other CP
Instructs U to invalidate the block containing the shared data, but in that case, it is necessary to lock the shared data, so L is sent before FETCHing the data.
It was necessary to notify other CPUs that OCK was to be taken.

In view of these conventional problems, the present invention addresses the limitations of the architecture of conventional systems, specifically, ``When a certain CPU is executing the above LOCK instruction,
Between TCH and 5TORE, access to the shared data from other CPUs by similar instructions is prohibited.'' By changing the lock command FETCH and 5TORE, access to the shared data from other CPUs is prohibited. In addition, it disables other CPUs at the timing of the test result after fetching data, and it also allows other CPUs to access LOCK before data FETCH.
The purpose is to provide a method that does not require notification to the U.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims.

That is, in a multiprocessor configuration in which a plurality of CPUs (each CPU has a cache memory) are connected via a common bus, the present invention provides instructions for accessing shared data when the plurality of CPUs access the shared data. The purpose of this method is to achieve the same effect as locking shared data on the cache memory and execute instructions efficiently by retrying according to the cache memory.The cache memory is controlled using the write-back method. In addition, the CPU has a function to retry instructions that require locking, such as update reference instructions (for example, TEST & SET, COMPARE & 5WAP, etc.), as necessary.

[Examples] Hereinafter, the structure, operation, etc. of the present invention will be described in detail based on Examples.

FIG. 1 is a diagram showing an example of the configuration of a multiprocessor system to which the present invention is applied.

In FIG. 1, 1. ~1. are CPU0 to CP, respectively.
U2.21-2. 3 represents a cache memory, 3 represents a common bus, 4 represents a memory control unit, and 5 represents a memory storage unit.

In FIG. 1, each CPU has its own cache memory, and each of the cache memories in multiple CPUs is saved at $1gJ using the write-to-task method.

FIG. 2 shows the configuration of one of CPU0 to CPU2 in FIG. 1 in more detail.

That is, FIG. 2 is a block diagram showing the configuration of a CPU according to an embodiment of the present invention, in which 6 is an instruction unit, 7 is a storage@control unit, and 8 is a lock instruction i! IN Gobe, 9
10 represents a common bus command control unit, 10 represents a cache memory control unit, and 11 represents a cache memory.

In FIG. 2, the instruction unit 6 is the cache memory 1.
1 or the memory storage unit 5 and executes the instruction, and when a memory access occurs, it notifies the storage control unit 7 to that effect.

Here, the lock instructions are decomposed (FETCH and 5TORE)
Don't use L, send it as is.

Storage control unit 7 controls cache memory 2
Controls 0-tsk commands, common bus commands, etc.

The lock instruction controller 8 holds the access coming from the instruction unit 6 and operates as if it were a lock instruction access.

・As a result of the test of shared data that was FETCH, 5
If there is no need to perform TORE, the instruction unit 6 is informed of the result.

・As a result of testing the shared data that was FETCHed, 5TO
When it becomes necessary to perform RE, and an invalidation command to another CPU is accepted on the common bus, the data is sent to 5TOREL, and the instruction unit is notified of this fact.

・As a result of the FETCH shared data test, 5TOR
If it becomes necessary to do E, but the invalidation command to other CPUs is not accepted on the common bus (because the invalidation commands issued by other CPUs are accepted on the common bus), Waiting as is. When an invalidation command for that block comes from another CPU, the 5TORE is canceled and the block is invalidated. Then, the lock instruction access is performed again.

The common bus command control section 9 controls commands to the common bus generated by the storage control unit 7, and also controls invalidation of the quiche block.

Now, consider an example in which CPUs 0 and 1 issue a lock instruction to shared data existing in their cache memories.

(1) When both CPUs do not need to perform 5TORE as a result of the FETCH test: In this case, nothing is done.

(2) If one side (for example, CPU0) needs to perform 5TORH as a result of the test for FETCH, and the other side (for example, CPUI) does not need to perform STORH, as shown in Figure 3, CPU0 5TOR to that block
Before doing H, issue a command to other CPUs to invalidate that block.

Here, "before 5TORE" means that other CPUs
However, this is because there may be a CPU that performs a lock instruction on the shared data and attempts to perform 5TOREL as a result. After the invalidation command is accepted on the common bus, the CPUO performs 5TOREs on the shared data. C.P.
The UI receives the invalidation command and invalidates the shared data cache block.

(3) If it is necessary to perform 5TORH as a result of the test for both CPU O21 and FETCH, the fourth
As shown in the figure, CPUs 0 and 1 have 5T in their blocks.
Before performing the ORE, issue a command to other CPUs to invalidate the block.Currently, when the command from CPU0 is accepted on the common bus, CPU0 performs 5 TOREs on the shared data.

On the other hand, the CPUI receives the invalidation command and invalidates the shared data cache block. Then, the block command is executed again from the beginning.

[Effects of the Invention] As explained above, according to the method of the present invention, the CPU is provided with a function to retry the locking command, so it is similar to locking shared data by using the block invalidation command. can bring about effects. As a result, instructions can be processed more effectively than in the past, and since there is no need to provide commands between CPUs for locking, performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a multiprocessor system to which the present invention is applied, and FIG. 2 is a diagram showing a CPU according to an embodiment of the present invention.
3 and 4 are diagrams illustrating invalidation control. ], ~13...cpuo~CPU2.21~2
゜...Cache memory, 3...Common bus, 4...Memory control unit, 5...-
...Memory storage unit, 6...Instruction unit, 7...Storage control unit, 8
...Lock instruction control unit, 9...Common bus command control unit, 10...Cache memory control unit, 11...Cache memory agent Patent attorney Mr. Sada Igeta, 4"i-:, -/ 1-1/ Figure f shows the configuration of the multiprocessor system used in this application. This is an example of a CPU that has been used as an example of a series of CPUs. structure) #, block diagram rate showing grass 2 figure

Claims (1)

[Claims] A main storage device and a plurality of processors each having a cache memory are connected to a common bus, and when updating the contents of the cache memory, only the cache memory is changed, and then the block is transferred to the main memory. In a multiprocessor system that employs a write-back method in which changes are controlled so that they are reflected in main memory when returned to the main memory, each processor issues an instruction that requires a lock, such as an update reference instruction, to each processor. 1. A cache memory control system comprising means for invalidating the block and then executing the instruction again when an invalidation command is received from another CPU.