JP3378270B2 - Multiprocessor system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a register bank on a bank RAM, and more particularly to a multiprocessor system capable of performing coherency control of a register bank.

[0002]

2. Description of the Related Art Recently, register banks have been changed to bank RA.
Development of multiprocessor system on M has been actively carried out. The register bank coherency control method in this multiprocessor system is the same as the cache memory coherency control method.

As a coherency control method for the cache memory, write-through or copy-back is generally used.

The write-through is to write to the main memory at the same time when the write operation is performed from the processor to the cache memory. On the other hand, copyback is
The main memory is not written at the time of a write operation, but is written to the main memory when being evicted from the cache due to the occurrence of a cache miss.

In write-through, the content of the cache memory and the content of the main memory always match, but the bus usage rate between the cache memory and the main memory becomes high. On the other hand, in copy back, the bus utilization rate between the cache memory and the main memory is low, but when the same data is held in another cache, it becomes necessary to invalidate it.

Such a cache memory coherency control method is applied to register bank coherency control. According to this method, when a write operation is performed on a register file, write-through is also performed on the bank RAM. And copyback controls invalidation.

Further, when the register bank is changed, the write-through does not require saving to the bank RAM, but the copy-back requires saving.

[0008]

As described above, in the conventional register bank coherency control method in the multiprocessor system, the coherency control is always performed when the register file is accessed. Therefore, in consideration of frequent access to the registers, there is a problem that the usage rate of the bank bus with the bank RAM becomes high.

The present invention has been made in view of such conventional circumstances, and an object thereof is to reduce the usage rate of a bank bus when coherency controlling a register bank on a bank RAM. It is to provide a multiprocessor system capable of performing.

[0010]

To achieve the above object, the present invention relates to a multiprocessor system in which a plurality of processors are connected to a main memory device and a register bank storage RAM via a system bus and a bank bus. Each processor has a system bus interface that controls data transfer between the inside of the processor and the main storage device, an instruction register, an instruction decoder, an operation execution unit, and a data storage unit that temporarily stores operation data. When,
A first register that holds a value indicating which bank on the register bank storage RAM the data stored in the data storage unit corresponds to, and a specific area of the register bank storage RAM Second to hold information
Of the register bank, an address generation unit that generates an address on the register bank storage RAM from the register access information from the instruction decoder and the value of the first register, and the generated address and the second register. A coherency determination unit that determines whether or not coherency control is required from the value, and a coherency control of the register bank on the register bank storage RAM when coherency control is required as a result of the determination by the coherency determination unit. And a coherency control unit for executing.

Alternatively, in the present invention, in a multiprocessor system in which a plurality of processors are connected to a main memory device and a register bank storing RAM via a system bus and a bank bus, each processor has an internal processor and the main memory device. A system bus interface for controlling data transfer between devices, an instruction register, an instruction decoder, an operation execution section, a data storage section for temporarily storing operation data, and a part of this data storage section. Holding a value indicating which bank on the register bank storing RAM the corresponding data corresponds to
Register, an address generation unit that generates an address on the register bank storage RAM from the register access information from the instruction decoder and the values of the first and second registers, and a specific register of the data storage unit. A third register holding a number, a register access information from the instruction decoder and a value of the third register, a coherency judging unit for judging whether coherency control is necessary, and a judgment in this coherency judging unit. As a result, when the coherency control is required, the coherency control unit executes the coherency control of the register bank on the register bank storing RAM.

[0012]

According to the present invention, the first register holds the value indicating which bank on the register bank storage RAM the operation data stored in the data storage unit matches. Further, the second register holds information indicating a specific area of the register bank storage RAM. The address generation unit generates an address on the register bank storage RAM from the register access information from the instruction decoder and the value of the first register.

The coherency determination unit determines whether or not the coherency control is necessary from the address generated by the address generation unit and the value of the second register. When coherency control is required as a result of the judgment by the coherency judgment unit, the coherency control unit executes the coherency control of the register bank on the register bank storage RAM.

Alternatively, according to the present invention, the first and second registers hold a value indicating which bank on the register bank storage RAM the operational data stored in a part of the data storage unit matches. ing. Further, the third register holds a specific register number of the data storage section. The address generation unit generates an address on the register bank storage RAM from the register access information from the instruction decoder and the values of the first and second registers.

The coherency determination unit determines whether or not the coherency control is necessary based on the register access information from the instruction decoder and the value of the third register. When coherency control is required as a result of the judgment by the coherency judgment unit, the coherency control unit executes the coherency control of the register bank on the register bank storage RAM.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment First, a coherency control method in the multiprocessor system of the first embodiment will be described.

FIG. 1 is a block diagram showing the configuration of the multiprocessor system of the first embodiment.

In the figure, in this multiprocessor system, a plurality of CPUs (processors) 1a to 1n are connected via a system bus 101 and a bank bus 102 to a main memory 2 and a bank RAM (register bank storage RA).
M) 3 is connected.

The internal configurations of the CPUs 1a to 1n are all the same, and the figure shows only the internal configuration of the CPU 1a.

The CPU 1a includes an SIU (system bus interface) 4 for controlling data transfer between the inside of the CPU 1a and the main storage device 2, and an IR (instruction register) 5.
, ID (instruction decoder) 6, and EXU (operation execution unit)
7, REG (register file / data storage unit) 8 for temporarily storing operation data, and BP (which holds a value indicating which bank on the bank RAM 3 the data stored in the REG 8 matches) First register) 9 and
SB holding information indicating a specific area of the bank RAM3
A P (second register) 10, an AG (address generation unit) 11 that generates an address on the bank RAM 3 from the register access information from the ID 6 and the value of the BP 9.
Based on the generated address and the value of SBP10, a CJ (coherency determination unit) 12 that determines whether or not coherency control is required, and, as a result of the determination by this CJ12, if coherency control is required CX for coherency control of register bank
(Coherency controller) 13.

The multiprocessor system of the first embodiment is constructed in this way, and the operation of this multiprocessor system will be described below. CPU1a for simplicity
Only the operation of will be described.

The CPU 1a adopts a register bank system, and the contents of the REG 8 match the data in the area on the bank RAM 3 pointed to by BP9.

The CPU 1a uses the main memory 2 to the SIU 4
The instruction is fetched into IR5 via. ID6 decodes the fetched instruction, and if it is an instruction to access REG8, the access information is CX13 and RE.
The register number is transmitted to G8 and the register number is transmitted to AG11 and REG8. In REG8, access is executed according to the transmitted information.

In CJ12, the generated bank RAM3
It is determined whether or not the coherency control is necessary based on the address of 1 and the address information that is stored in advance in the SBP 10 and indicates a specific area of the bank RAM 3, and the determination result is transmitted to the CX 13.

When the CX 12 determines that the coherency control is necessary, the CX 13 executes the coherency control based on the register access information transmitted from the ID 6 and the address of the bank RAM 3 transmitted from the AG 11.

In the first embodiment, whether or not the generated bank address is included in the specific area of the bank RAM 3 is used as a judgment element for determining whether or not the coherency control is necessary. The data stored in the bank RAM3 is C
Each of the CPUs 1a to 1n commonly used by the PUs 1a to 1n
There is something uniquely used in 1n.

Conventionally, when accessing data uniquely used by each of the CPUs 1a to 1n, each of the CPUs 1a to 1n is accessed.
Although the coherency control of the register bank between the two is not necessary, the coherency control is executed,
There was wasted access.

According to the present invention, as shown in FIG. 2, the data uniquely used by each of the CPUs 1a to 1n is converted into SBP10.
Since it is placed outside the area pointed to by and only the data uniquely used by each CPU 1a to 1n is placed in the area pointed to by SBP10, no wasteful bus cycle occurs.

Second Embodiment Next, a coherency control method in the multiprocessor system of the second embodiment will be described.

FIG. 3 is a block diagram showing the configuration of the multiprocessor system of the second embodiment. The blocks denoted by the same reference numerals as those in FIG. 1 have the same functions as those in FIG.

Similar to the first embodiment, this multiprocessor system has a plurality of CPUs (processors) 1a to 1n.
Via the system bus 101 and bank bus 102
It is connected to the main storage device 2 and the bank RAM (register bank storage RAM) 3.

The internal configurations of the CPUs 1a to 1n are all the same, and the figure shows only the internal configuration of the CPU 1a.

Each CPU 1a has an SIU (system bus interface) 4 for controlling data transfer between the inside of the CPU 1a and the main memory 2, and an IR (instruction register) 5
, ID (instruction decoder) 6, and EXU (operation execution unit)
7, REG (register file / data storage unit) 8 for temporarily storing operation data, and a value indicating which bank on the bank RAM 3 the data stored in a part of this REG 8 matches. BPL (first register) 14 and BPS (second register) 15 which are held, and I
Register access information from D6 and BPL14 and BP
An AG (address generation unit) 16 that generates an address on the bank RAM 3 from the value of S15 and a SAR (third register) 17 that holds a specific register number of the REG 8
And register access information from ID6 and SAR17
CJ (coherency determination unit) 18 that determines whether or not coherency control is required from the value of, and if the coherency control is required as a result of the determination in CJ 18, the coherency control of the register bank on the bank RAM 3 is performed. It is composed of a CX (coherency controller) 13 that executes.

The multiprocessor system of the second embodiment is constructed in this way, and the operation of this multiprocessor system will be described below. CPU1a for simplicity
Only the operation of will be described.

The CPU 1a adopts a register bank system, and the contents of REG8 match the data in the area on the bank RAM3 pointed to by BP9.

The CPU 1a uses the main memory 2 to SIU4.
The instruction is fetched into IR5 via. ID6 decodes the fetched instruction, and if it is an instruction to access REG8, the access information is CX13 and RE.
Send register number to G8 and AG16, CJ18, and REG8.

In AG16, the register number is BPL14.
If it is in the area pointed to by, register number and BPL
The address of the bank RAM3 is generated at 14, and BPS1
If it is in the area indicated by 5, register number and BP
An address is generated in S15. In REG8, access is executed according to the transmitted information.

In CJ18, the register number sent from ID6 and REG8 stored in advance in SAR17
It is determined whether coherency control is necessary based on the register number information indicating a specific area of
Send to X13.

When the CJ 18 determines that the coherency control is necessary, the CX 13 executes the coherency control based on the register access information transmitted from the ID 6 and the address of the bank RAM 3 transmitted from the AG 11.

In the second embodiment, whether or not the register number from ID6 is included in the specific area of REG8 is used as a judgment element for determining whether coherency control is necessary. Similar to the first embodiment, the data uniquely used by the CPUs 1a to 1n are arranged in the registers other than those designated by the SAR17, and the data commonly used by the CPUs 1a to 1n are arranged in the register designated by the SAR17. By doing so, useless bus cycles can be prevented.

Here, the BPL 14 has a bank RAM 3
A pointer is set in the area for storing the data uniquely used by each of the above CPUs 1a to 1n, and the BPL 15 is set to
It is necessary to set a pointer that points to the area that stores common data.

[0043]

As described above, according to the multiprocessor system of the present invention, when the register file is accessed, the coherency control is not always executed, but only when necessary. As a result, the usage rate of the bank bus used when accessing the bank RAM can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a multiprocessor system according to a first embodiment.

FIG. 2 is a memory map on the bank RAM shown in FIG.

FIG. 3 is a block diagram showing a configuration of a multiprocessor system according to a second embodiment.

[Explanation of symbols]

1a to 1n CPU (processor) 2 main memory 3 bank RAM (register bank storage RAM) 4 SIU (system bus interface) 5 IR (instruction register) 6 ID (instruction decoder) 7 EXU (arithmetic execution unit) 8 REG (register file / data storage) 9 BP (first register) 10 SBP (second register) 11 AG (address generator) 12 CJ (coherency judgment unit) 13 CX (coherency controller) 14 BPL (first register) 15 BPS (second register) 16 AG (address generator) 17 SAR (third register) 18 CJ (Coherency Judgment Department) 101 system bus 102 bank bus

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A 1-266643 (JP, A) JP-A 3-119447 (JP, A) JP-A 4-175946 (JP, A) JP-A 1- 201751 (JP, A) JP 1-263735 (JP, A) JP 2-116951 (JP, A) JP 3-17770 (JP, A) JP 63-298638 (JP, A) JP-A-1-287768 (JP, A) JP-A-59-86966 (JP, A) JP-A-4-373025 (JP, A) JP-A-4-299440 (JP, A) JP-A-4-296962 (JP, A) JP-A-6-67886 (JP, A) JP-A-5-210512 (JP, A) Hisaoka et al., High-performance 16-bit original microcomputer TLCS9000 / 16 CPU core, IEICE Tech. The Institute of Electronics, Information and Communication Engineers, April 23, 1993, Vol. 93, No. 16, p. 17-24 (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 12/08 G06F 9 / 34,9 / 38,9 / 46 G06F 15/16-15/177

Claims (2)

(57) [Claims] 1. In a multiprocessor system in which a plurality of processors are connected to a main memory device and a register bank storage RAM via a system bus and a bank bus, each processor is connected between the inside of the processor and the main memory device. The system bus interface that controls the data transfer of, the instruction register, the instruction decoder, the operation execution unit, the data storage unit that temporarily stores the operation data, and the data stored in this data storage unit are A first register that holds a value indicating which bank on the register bank storage RAM matches; a second register that holds information indicating a specific area of the register bank storage RAM; and the instruction decoder R for storing the register bank from the register access information and the value of the first register.
An address generation unit that generates an address on AM, and the generated address and the value of the second register,
A coherency determination unit that determines whether or not coherency control is required, and executes coherency control of a register bank on the register bank storage RAM when coherency control is required as a result of the determination by the coherency determination unit. A multiprocessor system comprising a coherency controller. 2. In a multiprocessor system in which a plurality of processors are connected to a main memory device and a register bank storing RAM via a system bus and a bank bus, each processor is connected between the inside of the processor and the main memory device. System bus interface that controls the data transfer of, the instruction register, the instruction decoder, the operation execution unit, the data storage unit that temporarily stores the operation data, and the data stored in a part of this data storage unit. Are the first and second registers holding a value indicating which bank on the register bank storage RAM matches, register access information from the instruction decoder and the values of the first and second registers. From an address generation unit that generates an address on the register bank storage RAM; Third to hold a specific register number
Of the register, the register access information from the instruction decoder and the value of the third register, a coherency determination unit that determines whether or not coherency control is required, and the coherency control determines whether the coherency control is performed. A multiprocessor system comprising: a coherency control unit that executes coherency control of a register bank on the RAM for storing the register bank when necessary.