JP2017016285A - Data control apparatus which shares buffer among plural data processing units, and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide fast data communication which allows plural arithmetic units to share the data of an intermediate buffer.SOLUTION: The present invention relates to a data control apparatus equipped with plural intermediate buffer (BF) control means. The intermediate BF control means comprises: input means for controlling data transfer from a DRAM to data processing means via an intermediate BF; output means for controlling data transfer from the data processing means to the DRAM via an intermediate BF; and synchronous execution means for controlling the operation of the input and output means, according to each BF status information set. The synchronous execution means, upon reception of an execution completion notification from the input means, sets the BF status information of the input means to a write-in status; and upon reception of an execution completion notification from the output means, sets the BF status information of the output means to a read-out status. The synchronous execution means transmits the BF status information mutually with the synchronous execution means of other intermediate BF control means when an intermediate BF is shared, and transmits the BF status information of the output means mutually with the BF status information of the input means such that the BF status information is updated by a synchronization signal when the intermediate BF is not shared.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a data processing device and a control method thereof, and more particularly to a data control device and a control method in the case where a buffer that holds data to be supplied to a data processing unit is shared by a plurality of data processing units.

  When various modules such as CPU (Central Processing Unit), DRAM (Random Access Memory), and data processing unit are connected to the system bus, if the data communication on the system bus increases, the bandwidth of the system bus is compressed and smooth. Data communication will be hindered. Thus, for example, in a single core processor, data communication between the DRAM and the core is reduced by transferring data on the DRAM to the cache memory and performing data communication between the cache memory and the core. However, in order for a plurality of single core processors to share data on the cache, it is necessary to communicate via DRAM.

  For this reason, when data is shared among a plurality of cores, communication with the DRAM is enlarged, and the bandwidth of the system bus is compressed. Therefore, a method has been developed in which coherency control is performed in which cache memory data is shared by a plurality of cores, such as a multi-core processor, to reduce data communication on the system bus (Patent Document 1). The CELL processor disclosed in Patent Document 2 also takes measures to reduce data communication with the system bus.

  The CELL processor includes a plurality of SPEs (Synergistic Processor Elements) having an arithmetic unit and an LS (Local Store), and these are connected by an EIB (Element Interconnect Bus) that performs high-speed data communication between the SPEs. Further, when the SPE performs data communication with the DRAM, it is performed from a MIC (Memory Interface Controller) connected to the EIB via the system bus. Because of such a configuration, when data held in the LS of a certain SPE is transferred to the LS of another SPE, it is performed via the EIB. That is, since the EIB, which is a high-speed data communication bus independent of the system bus, is used between the SPEs, data communication on the system bus can be reduced.

Japanese Patent No. 3378270 Japanese Patent No. 4719655

However, in multi-core processors, when performing coherency control, control of several clock cycles is required for coherency control, which may be an overhead of data sharing. In addition, since the CELL processor requires data communication via the EIB in order for other SPEs to refer to data held in the LS of a certain SPE, many clock cycles are consumed for data communication control. .
In view of the above-described problems, the present invention provides a buffer control method and control apparatus that perform high-speed data sharing with a simple configuration even in a system that includes a plurality of systems having local memories.

A data control device comprising a plurality of intermediate buffer control means,
The intermediate buffer control means includes
Input means for controlling data transfer from the DRAM to the intermediate buffer and data transfer from the intermediate buffer to the data processing means;
Output means for controlling data transfer from the data processing means to the intermediate buffer and data transfer from the intermediate buffer to the DRAM;
Synchronization holding means for holding buffer status information of the input means and the output means, respectively, and controlling operations of the input means and the output means according to the buffer status information,
The synchronization execution means includes
When the execution completion notification is received from the input means, the buffer status information of the input means is set to the write state,
When the execution completion notification is received from the output means, the buffer status information of the output means is set as a read state,
When the intermediate buffer is shared with other intermediate buffer control means, the synchronization execution means of the other intermediate buffer control means and the buffer status information are mutually transmitted,
When the intermediate buffer is not shared with other intermediate buffer control means, the buffer status information of the input means and the buffer status information of the output means are sent to each other,
The buffer status information of each synchronization execution means is updated by the synchronization signal.

  A plurality of intermediate buffer control units hold the intermediate buffer state information, and the intermediate buffer control unit communicates the write state signal, the read state signal, and the synchronization signal of the intermediate buffer state information to each other. The intermediate buffer status information is updated at the timing received at the time. As a result, one intermediate buffer can be shared by a plurality of intermediate buffer control units with a simple configuration, and high-speed data sharing becomes possible.

It is a block diagram which shows the image processing apparatus of the Example in this invention. It is explanatory drawing of image data. It is a block diagram which shows the detailed structure of an image process part. It is a block diagram which shows the detailed structure of an image input part and an image output part. It is a block diagram which shows the detailed structure of a synchronous execution part. It is a flowchart of synchronous execution. It is a flowchart of input control. It is a flowchart of output control. FIG. 10 is a diagram illustrating an operation when an intermediate buffer is shared in the first embodiment. FIG. 10 is a diagram illustrating an operation when an intermediate buffer is shared in the first embodiment. FIG. 10 is a diagram illustrating an operation when an intermediate buffer is shared in the second embodiment. FIG. 10 is a diagram illustrating an operation when an intermediate buffer is shared in the second embodiment. FIG. 10 is a diagram illustrating an operation when an intermediate buffer is shared in the second embodiment. FIG. 10 is a diagram illustrating a detailed configuration of a synchronization execution unit according to a third embodiment. 10 is a flowchart of synchronization execution in the third embodiment. 10 is a flowchart of input control in the third embodiment. 10 is a flowchart of output control in Embodiment 3. It is a figure regarding the case where the number of pixels decreases compared with an input image in an output image. It is a figure explaining the effect when a plurality of intermediate buffers operate in parallel.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments.
<Example 1>
(Image processing device)
FIG. 1 is a block diagram illustrating a configuration example of an image processing apparatus according to the first embodiment of the present invention. The image processing apparatus 100 includes a system control unit 110, a scanner control unit 120, an image processing unit 130, and a printer control unit 140.
The system control unit 110 includes a CPU 111 that controls each module connected to the system bus 170 of the image processing apparatus, a DRAM 112 that stores temporary data such as image data and setting values of each module, and a control program described later. It consists of a ROM 113 that holds it.

  The scanner control unit 120 is a module that controls the connected scanner 121 and writes the obtained image data to the DRAM 112 by DMA (Direct Memory Access) transfer. When a scan start command is received from the CPU 111, the scanner 121 is activated to scan the reading medium. The scanner 121 performs analog / digital conversion on an analog image signal obtained from a CCD sensor or the like by scanning to generate digital image data (hereinafter referred to as image data). This image data is received by the scanner control unit 120 and written to the DRAM 112 by DMA transfer. When the above scan processing is completed, a scan end signal is transmitted to the CPU 111 and the image processing unit 130.

  The printer control unit 140 is a module that controls the connected printer 141 and records image data on the DRAM on a print medium. When a print start command is received from the CPU 111, image data for printing is taken out from the DRAM 112 by DMA transfer, and the printer 141 is activated. Then, ink is ejected from a print header or the like provided in the printer 141, and an image is recorded on the print medium. When the above print processing is completed, a print end signal is transmitted to the CPU 111.

  Here, the image data to be handled may be read and written from a USB memory, a flash card, or the like, and the USB control unit 150 or the media control unit 160 is connected to the system bus 170 as shown in FIG. You may forward to. In any case, it is obvious that these modules can be realized in various forms, and the present invention is not limited to the illustrated configuration.

  The image processing unit 130 is a data control device including an image processing control unit 131 including control of an intermediate buffer, which is a feature of the present invention, a scanner image processing circuit group 132, and a printer image processing circuit group 133. When the image processing unit 130 receives a command to start image processing execution from the CPU 111, the image processing control unit 131 acquires part of the image data on the DRAM by DMA transfer and writes it in an intermediate buffer described later. Then, the data held in the intermediate buffer is transferred to the scanner image processing circuit group 132 and the printer image processing circuit group 133 to execute image processing. Thereafter, the image processing result is written to the intermediate buffer, and the image processing result held in the intermediate buffer by DMA transfer is written back to the DRAM 112. The image processing is completed by applying the above operation to the entire image data.

  Here, as an example, the operation of the image processing apparatus when the scan process and the print process are continuously executed will be briefly described. In order to simplify the explanation, it is assumed that the DRAM and the intermediate buffer have enough capacity to hold image data. First, the CPU 111 reads a program from the ROM 113 and starts execution. The CPU 111 sets the scanner control unit 120, the image processing unit 130, and the printer control unit 140 according to the program.

  Thereafter, the scanner control unit 120 is activated and the scanned image data is written into the DRAM 112. Thereafter, the image processing unit 130 is activated, and appropriate image processing is performed on the image data held in the DRAM 112, and the processing result is written to the DRAM 112. Finally, the printer control unit 140 is activated to read and print image data on the DRAM subjected to image processing.

The scan process and the print process are executed as described above. The system control unit 110 controls each module in accordance with a program, and can implement various processes by using an appropriate program.
Next, an operation in a capacity where the capacity of the DRAM 112 and the intermediate buffer cannot hold the entire image data 200 will be described. When the capacity of the DRAM 112 or the intermediate buffer is small, image processing is performed by dividing the image data.

(Band processing)
In a device that needs to be provided at a low cost such as a home printer, there is a case where it is not possible to mount a memory having a capacity enough to store one piece of digital image data in order to reduce hardware costs. Therefore, one digital image data is divided into a plurality of strip-shaped band areas, and only the band areas are sequentially developed in a memory (hereinafter referred to as a band memory) to perform various image processing, so-called band processing. May be performed.

Here, although the DRAM has a capacity that can hold the entire band area 210 shown in FIG. 2, the operation when the capacity of the intermediate buffer is a capacity that can hold only a part of the band area will be described.
First, as described above, the CPU 111 reads a program from the ROM 113 and sets the scanner control unit 120, the image processing unit 130, and the printer control unit 140. Thereafter, the scanner control unit 120 is activated to scan the band area 210 which is a part of the image data and write it in the DRAM 112.

  Thereafter, the image processing unit 130 is activated to perform image processing on the band region 210. However, since the intermediate buffer of the image processing unit 130 has a capacity sufficient to hold a part of the band area, the band area 210 is divided into three parts, a band division area A230, a band division area B231, and a band division area C232. Apply image processing. (Fig. 2 (h) to (j))

First, the image processing unit 130 reads the band division area A230 from the DRAM 112, and writes image data to which image processing is applied to the DRAM 112.
Subsequently, the image processing unit 130 reads the next band division region B231 from the DRAM 112, and writes image data to which image processing is applied to the DRAM 112.
By repeating this, the image processing for the band region 210 is completed.
Thereafter, the printer control unit 140 is activated to read and print the image-processed band area on the DRAM.

When the processing of the band area 210 (FIG. 2A) is completed in this way, the band area 211 (FIG. 2B) is read by the scanner, and the band area 211 is divided in the same manner as the processing of the band area 210. Image processing.
By repeating the above processing and applying it to the entire image, the image processing can be applied to the entire image 200 even when the capacity of the DRAM 112 or the intermediate buffer is a capacity that cannot hold the entire image data 200.

(Image processing unit)
Next, details of the image processing unit 130 will be described with reference to FIG.
As described above, the image processing unit 130 is a data control device including the image processing control unit 131, the scanner image processing circuit group 132, and the printer image processing circuit group 133. The scanner image processing circuit group 132 and the printer image processing circuit group 133 serve as a data processing unit.

  The scanner image processing circuit group 132 includes image processing circuits 132-1 to 132-n such as a gamma conversion for correcting CCD sensor characteristics for each scanner 121 to be connected and a filter for removing noise at the time of scanning. The scanner image processing circuit group 132 is connected to the intermediate buffer control unit a320, and when executing scan processing, image data is input from the intermediate buffer control unit a320 to each image processing circuit, and the result calculated by each image processing circuit is intermediate. The data is output to the buffer control unit a320.

  The image processing circuit group for printer 133 performs image processing such as color space conversion for converting image data into a color space for printing ink, and halftone processing for converting multi-gradation image data into a form expressing low gradation. Circuits 133-1 to 133-n are included. The printer image processing circuit group 133 is connected to the intermediate buffer control unit b330, and performs input / output of setting commands and image data to and from the intermediate buffer control unit b330 at the time of execution of print processing.

  The image processing control unit 131 is a circuit that controls data communication between the DRAM 112 and the image processing circuit via a built-in intermediate buffer. The image processing control unit 131 includes a DMA controller 310, an intermediate buffer control unit a320, an intermediate buffer control unit b330, and an intermediate buffer group 340.

  The DMA controller 310 performs an operation of writing data on the DRAM to the intermediate buffer and an operation of writing the data of the intermediate buffer to the DRAM 112 by DMA transfer in response to requests from the intermediate buffer control units a and b. Which address on the DRAM is accessed and which intermediate buffer is accessed are specified by a request from the intermediate buffer control units a and b.

The intermediate buffer group 340 includes a plurality of intermediate buffers 342-1 to 342-4 that temporarily hold image data, and an arbiter 341 that arbitrates access requests to each buffer and transmits an access result to the request issuer. Composed.
The arbiter 341 is connected to the intermediate buffer 342, the DMA controller 310 that issues a request to the intermediate buffer 342, the intermediate buffer control unit a320, and the intermediate buffer control unit b330. The arbiter 341 arbitrates write and read requests from the request issuer to the intermediate buffer 342 and executes them. Specifically, when there is an access request to the same buffer from a plurality of modules at the same time, arbitration is performed such that the module with higher priority is executed first. However, the arbitration method is not limited to this.

  The intermediate buffer control unit a320 is a module that controls communication between the DRAM 112 and the intermediate buffer and communication between the intermediate buffer 342 and the image processing circuit. The intermediate buffer control unit a320 includes an image input unit 321 and an image output unit 322, and a synchronization execution unit 333 that performs setting and execution management thereof. Further, since the intermediate buffer control unit b330 has the same configuration and operation, the intermediate buffer control unit a320 will be mainly described below.

(Image input part)
The image input unit 321 is a module that issues a request for operating the intermediate buffer in accordance with an instruction from the synchronization execution unit 323. There are two types of requests. One is a request for acquiring image data from the DRAM 112 and writing it to the intermediate buffer 342, which is issued to the DMA controller 310. The other is a request for reading the image data held in the intermediate buffer 342 and transmitting it to the image processing circuit 132, which is issued to the intermediate buffer group 340.

Details of the image input unit 321 will be described with reference to FIG.
The image input unit 321 includes a DMA receiver 411 and a packet transmitter 412.

  The DMA receiver 411 controls a request issued to the DMA controller 310. At the time of image processing, an address where image data on the DRAM is placed and which intermediate buffer is used are set from the synchronization execution unit 323. Thereafter, when an execution start command is received from the synchronization execution unit 323, a predetermined amount of image data is acquired from the set address area of the DRAM 112, and a request is issued to the DMA controller 310 to write to the intermediate buffer 342. When the completion of execution of the request is notified from the DMA controller 310, the execution completion is notified to the synchronization execution unit 323.

(Packet transmitter)
The packet transmission unit 412 is a module that controls a request issued to the intermediate buffer group 340 and data output to the image processing circuit 132. At the time of image processing, the synchronization execution unit 323 sets which buffer to use and the image format and image size to be handled. Thereafter, when an execution start command is received from the synchronization execution unit 323, a request is generated to extract data from any of the set intermediate buffers 342 according to the image format, and is issued to the intermediate buffer group 340.

At the same time, packet data in which information for specifying the pixel position is added to the image data read from the intermediate buffer group 340 in accordance with the image size set by the synchronization execution unit 323 is generated and transmitted to the image processing unit 132. To do. When the transmission is completed, the synchronization execution unit 323 is notified of the execution completion.
Here, information for specifying a pixel position added to the image data by the packet transmission unit 412 will be described with reference to FIG.

  FIG. 2K shows image data 240 that the packet transmission unit 412 transmits to the image processing unit 132. The packet transmitting unit 412 is set to handle image data of v pixels in the main scanning direction and h pixels in the sub scanning direction from the synchronization execution unit 323 as the amount of data to be transferred. The packet transmission unit 412 transmits pixel data from the pixel 240-1 in the sub-scanning direction. When the h-th pixel is transmitted, one pixel is moved in the main scanning direction, and the first pixel is sequentially transmitted in the sub-scanning direction.

At the start of transfer, when data of the first pixel 240-1 is transferred, a transfer start signal and a line start signal are added as information for specifying the pixel position.
When the data of the last pixel 240-n is transmitted at the end of transfer, a transfer end signal and a line end signal are added.
In addition, when transmitting data of the first pixel when viewed in the sub-scanning direction, only the line start signal is added.
Only the line end signal is added when transmitting the data of the h-th pixel which is the final pixel when viewed in the sub-scanning direction.
These signals for specifying the pixel position are used by the image processing circuit and the image output unit 322, and the image output unit 322 uses them when calculating the size of the image data after the image processing.

(Image output part)
The image output unit 322 is a module that issues a request to operate the intermediate buffer in accordance with a command from the synchronization execution unit 323. There are two types of requests, one for receiving image data processed by the image processing circuit 132 and issuing a request for writing to the intermediate buffer 342 to the intermediate buffer group 340. The other is to issue a request to the DMA controller 310 to write the processed image data held in the intermediate buffer 342 to the DRAM 112. Here, details of the image output unit 322 will be described with reference to FIG.
The image output unit 332 includes a packet reception unit 422 and a DMA transmission unit 421.

(Packet receiver)
The packet receiving unit 422 is a module that receives image data from the image processing circuit 132 and controls a request issued to the intermediate buffer group 340. At the time of image processing, settings such as which intermediate buffer 342 to use and an image format to be handled are set from the synchronization execution unit 323.

  Thereafter, when an execution start command is received from the synchronization execution unit 323, the image data from the image processing unit 132 is received, a request is generated to write the data to the intermediate buffer 243 in accordance with the set image format, and the intermediate buffer group Issued to 340. When the transfer end signal added by the image input unit 321 is received, the execution completion and the output image size are notified to the synchronization execution unit 323. Here, a method for calculating and using an output image size will be described with reference to FIG.

  The image data 240 ′ shown in FIG. 2 (l) is image data obtained by processing the image data 240 shown in FIG. 2 (k) by the image processing circuit group, and the image data received by the packet receiving unit. Show. The image data 240 ′ is image data of v ′ pixels in the main scanning direction and h ′ pixels in the sub scanning direction. The packet receiving unit 422 receives pixel data from the pixel 240-1 ′ in the sub scanning direction. When the h'th pixel is received, the pixel is moved by one pixel in the sub-scanning direction, and received in order from the first pixel in the main scanning direction.

When the packet receiving unit 422 receives the first pixel in the sub-scanning direction, it detects the line start signal added by the image input unit and starts counting the number of received pixels.
Each time the pixels 240-2 ′ and 240-3 ′ are received, the number of received pixels is counted up.
When the h'th pixel is received in the main scanning direction, the line end signal added by the image input unit 321 is detected, and the count up of the number of received pixels is completed.
In this way, the packet receiving unit 422 calculates the number h ′ of pixels in the main scanning direction as the size of the output image obtained by processing by the image processing circuit.

Thereafter, the pixel number h ′ is transmitted from the image output unit 322 including the packet receiving unit 422 to the execution control unit 510 as a signal 5113a. The execution control unit 510 uses the received data amount when calculating the address on the DRAM when the DMA reception unit 411 continuously processes a plurality of band areas. The calculated DRAM address is set in the DMA receiver 411 by the signal 511 from the execution controller 510.
As will be described in detail later, a method of using the number of output pixels when the intermediate buffer control units a and b share the intermediate buffer 342 when the scan process and the print process are continuously executed will be described.
First, the preceding scan process is executed for the band region.
Thereafter, the intermediate buffer control unit b330 in charge of the subsequent printing process calculates the pixel number h ′ of the output image.
The number h ′ of pixels is received by the signal line 5113b of the intermediate buffer control unit a320 that is in charge of the preceding scan process.
The intermediate buffer control unit a320 calculates an address on the DRAM of the band area to be acquired next using the received value (number of pixels h ′).

Specifically, as shown in FIG. 2E, as a result of performing image processing on the band region 210 of h pixels in the sub-scanning direction, output image data of h ′ pixels in the sub-scanning direction is obtained. . In this case, the execution control unit 510 calculates the band region to be processed next by using the number of pixels h ′ calculated by the image output unit 422, and moves the band from the band region 220 by h ′ pixels in the sub-scanning direction. Control is performed to acquire the area 221.
By this mechanism, even when there is image processing in which the size of the output image changes like a filter in the image processing circuit, by autonomously switching the address reference destination on the DRAM within the image processing unit 130, The continuity of the output image can be ensured. That is, in order to ensure the continuity of the output image, it is not necessary to switch the setting of the execution control unit 510 from the CPU 111 each time the band region to be processed is switched, and a plurality of band regions can be created without waiting for control of the CPU 111. It is possible to transfer continuously.
This point will be described in detail below.

FIG. 15A shows input image data 1500 and a first input band area 1511 and a second input band area 1521 input to the image processing unit.
FIG. 15B shows a first output band region 1512 and a second output band region 1522 output from the image processing unit.
The input band region 1511 (data) is processed to output the output band region 1512 (data), the input band region 1521 is processed, and the output band region 1522 is output.
When the input band region 1511 is input, the input band region 1521 is input next.

As shown in FIG. 15 (a), the number of pixels in the sub-scanning direction of the input band regions 1511 and 1521 is h, respectively, and as shown in FIG. 15 (b), the output band regions 1512 and 1522 in the sub-scanning direction. Assume that the number of pixels is h ′.
As shown in FIGS. 15A and 15B, the output band region 1512 has {(h−h ′) / 2} pixels above and below in the sub-scanning direction as compared with the input band region 1511, and one pixel in this example. Suppose it is small.
Similarly, the output band region 1522 is smaller than the input band region 1521 by {(h−h ′) / 2} pixels above and below in the sub-scanning direction, one pixel in this example.

In such a case,
As shown in FIG. 15B, in order for the pixel at the lower end of the output band region 1512 and the pixel at the upper end of the output band region 1522 to be continuous without a gap,
As shown in FIG. 15A, it is necessary to overlap the input band region 1511 and the input band region 1521 by (h−h ′) pixels, two pixels in this example.

  Further, the method for calculating the output image data size is not limited to the above, and it may be calculated by the image processing circuit group and set in the execution control unit 510. The execution control unit 510 refers to the setting of each image processing circuit. Thus, the output image size may be calculated. In any case, it suffices to have a method for autonomously calculating the size of the output image data by the synchronization control unit.

  The DMA transmission unit 421 controls a request issued to the DMA controller 310. At the time of image processing, an address on the DRAM for writing the processed image data from the synchronization execution unit 323 and which intermediate buffer to use are set. Thereafter, when an execution start command is received from the synchronization execution unit 323, a predetermined amount of image data is acquired from the set intermediate buffer 342 and a request is issued to the DMA controller 310 to write it out to the DRAM 112. When the completion of execution of the request is notified from the DMA controller 310, the execution completion is notified to the synchronization execution unit 323.

(Synchronous execution part)
The synchronization execution unit 323 is a module that controls the management of the intermediate buffer 342 and the execution of the image input unit 321 and the image output unit 322. The synchronization execution unit 323 is connected to the CPU 111, the image input unit 321, the image output unit 322, and the synchronization execution unit 333 of the other intermediate buffer control unit 330.
The CPU 111 receives an image processing execution start command and transmits an image processing execution end signal.
Connected to the image input unit 321 are a buffer used by the image input unit, a signal for setting an address on the DRAM to be accessed, a size of image data, and a signal for controlling the operation of the image input unit 321. Is done.

Similarly, the image output unit 322 includes a signal used for setting a buffer used by the image output unit, an address on the DRAM to be accessed, a size of the image data, and a signal for controlling the operation of the image output unit 322. Connected.
The other intermediate buffer control unit 330 is connected with a signal for updating buffer status information for sharing the intermediate buffer among a plurality of image processing circuit groups, and a synchronization signal.

A detailed configuration of the synchronization execution unit 323 will be described with reference to FIG.
The synchronization execution unit 323 includes an execution control unit 510, an input control unit 520, and an output control unit 530.

The execution control unit 510 is a module that performs setting of the image input unit 321 and the image output unit 322 and execution control of the input control unit 520 and the output control unit 530.
The image input unit 321 is set by signals 511 (DMA reception unit setting) and 512 (packet transmission unit setting), and the image output unit 322 is set by signals 513 (DMA transmission unit setting) and 514 (packet reception). Part setting).

An execution start command to the input control unit is transmitted by a signal 515, and an execution completion notification from the input control unit is received by a signal 516.
An execution start command to the output control unit is transmitted by a signal 517, and an execution completion notification from the output control unit is received by a signal 518.
An image processing execution start signal from the CPU 111 is received by a signal 519, and an image processing end signal to the CPU 111 is transmitted from a signal 5110.

A control sequence of the execution control unit 510 will be described with reference to FIG.
In step S601, the CPU waits for an interruption of image processing start from the CPU, and if detected, the process proceeds to step S602.
In S602, an execution start command is issued to the input control unit 520 and the output control unit 530, and the process proceeds to S603.
In S603, it waits for the execution end signal from the input side control part 520 and the output side control part 530, and when both signals are received, it changes to S604.
In step S604, the input / output control is ended, and the CPU 111 is notified of an interruption for the end of image processing.

(Input control unit)
The input control unit 520 is a module that performs synchronization control of the DMA reception unit 411 and the packet transmission unit 412 of the image input unit 321 and management of the intermediate buffer 342. An execution start command to the DMA receiver 411 is transmitted by a signal 521, and an execution end from the DMA receiver is received by a signal 522. An execution start command to the packet transmission unit 412 is transmitted by a signal 523, and an execution end from the packet transmission unit is received by a signal 524.

When sharing the intermediate buffer 342 with another intermediate buffer control unit 330, the signal 5111 is set to share the intermediate buffer, and the synchronization signal transmitted by the signal 525 and the synchronization received by the signal 526 are set. Synchronous control is performed using the signal.
At the same time, update information for setting the buffer state information to the write state is transmitted to another intermediate buffer control unit 330 by signal 527, and update information for setting the buffer state information to the read state is transmitted to other intermediate buffer control unit 330 by signal 528b. By receiving from 330, the buffer status information is also synchronized.
When the packet transmission unit 412 completes the transmission of the image data and the band area, the signal 529 receives a signal for ending the execution of the input control unit 520.

The control sequence of the input control unit will be described with reference to FIG.
In S701, the process waits for the execution start instruction 515 from the execution control unit 510. When the execution start instruction 515 is received, the process proceeds to S702.
In S702, if the setting does not share the intermediate buffer with another intermediate buffer control unit, the process proceeds to S703-0, and if the setting is shared, the process proceeds to S710.
In S703-0, referring to the buffer status information held in the buffer status holding unit 520b of the input control unit 520,
If it is empty, an execution start command is issued from the signal 521 to the DMA receiver 411,
If it is full, an execution start command is issued from the signal 523 to the packet transmission unit 412 and the process proceeds to S704-0.
In S704-0, the process waits until receiving an end-of-execution notification from the module that has issued the execution start instruction using the signals 522 and 524. When the end signal is detected, the process proceeds to S707-0.
In S707-0, the buffer status information held in the buffer status holding unit 520b used by the module that issued the execution start command is updated. When the DMA receiving unit 411 updates the buffer, the buffer state information write state signal 528 is asserted to make the buffer state information held in the buffer state holding unit 520b full. When the packet transmission unit 412 updates the buffer, the read state signal 527 is asserted to empty the buffer state information held in the buffer state holding unit 520b. When the buffer status information is updated, the process proceeds to S708.
In S708, if the processing end signal 529 from the image input unit 321 is not transmitted, the process proceeds to S702, and if it is transmitted, the process proceeds to S709.

Returning to the description of the transition to S710, when transitioning to S710, the buffer state information held in the buffer state holding unit 520b of the input control unit 520 is referred to, and if full, the process proceeds to S703-1. If it is empty, the process proceeds to S705-2.
When the process proceeds to S703-1, the input control unit 520 issues an execution start command from the signal 523 to the packet transmission unit 412, and the process proceeds to S704-1.
In S704-1, it waits until the execution end signal of the packet transmission part 412 is received by the signal 524, and if an end signal is detected, it will transfer to S705-1.
In S705-1, the synchronization signal 525 with the other intermediate buffer control unit 330 and the buffer read state signal 527 are asserted, and the process proceeds to S706-1.

  Returning to the description of the transition to S705-2, when transitioning to S705-2, the synchronization signal 525 with the other intermediate buffer control unit 330 is asserted, the buffer read state signal 527 is negated, and S706. Transition to -1.

In step S706-1, the process waits for the synchronization signal 526 from the other intermediate buffer control unit 333, and if it is received, the process proceeds to step S707-1.
In S707-1, the buffer state holding unit 520b holds the read state signal 527 issued by the input synchronization unit 520a and the asserted signal among the write state signal 528 issued by the other intermediate buffer control unit 330. Update the buffer status information. When the buffer status information is updated, the process proceeds to S708.
In S708, the execution control unit 510 is notified of execution completion from the signal 516, and the input control is terminated.

(Output control unit)
The output control unit 530 is a module that performs synchronization control of the DMA transmission unit 421 and the packet reception unit 422 of the image output unit 322 and management of the intermediate buffer. The execution start command to the DMA transmission unit 421 is transmitted by a signal 531, and the execution end from the DMA transmission unit 421 is received by a signal 532. The execution start command to the packet receiving unit 422 is transmitted by a signal 533, and the execution end from the packet receiving unit 422 is received by a signal 534. When sharing the intermediate buffer 342 with another intermediate buffer control unit 330, the signal 5112 is set to share the intermediate buffer, and the synchronization signal transmitted by the signal 536 and the synchronization received by the signal 535 are set. Synchronous control is performed using signals.

  At the same time, update information that sets the buffer state information to the write state is transmitted by the signal 538, and update information that sets the buffer state information to the read state is received by the signal 537a, thereby being held in the buffer state holding unit 530b. Also synchronizes buffer status information. Further, when reception of image data or a band region is completed in the packet receiving unit 422, a signal for terminating the execution of the output control unit 530 is received by a signal 539. When this signal shares the intermediate buffer 342 with another intermediate buffer control unit 330, the end signal of the image input unit 529b of the other intermediate buffer control unit 330 is selected and used.

A control sequence of the output control unit 530 will be described with reference to FIG.
In step S801, the process waits for an execution start instruction 517 from the execution control unit 510. When the execution start instruction 517 is received, the process proceeds to step S802.
If the setting is not to share the intermediate buffer 342 with the other intermediate buffer control unit 330 in S802, the process proceeds to S803-0, and if the setting is to be shared, the process proceeds to S810.

In S803-0, referring to the buffer status information held in the buffer status holding unit 530b of the output control unit 530,
If it is empty, an execution start command is issued from the signal 533 to the packet receiving unit 422,
If it is full, an execution start command is issued from the signal 531 to the DMA transmitter 421, and the process proceeds to S804-0.

  In S804-0, it waits until it receives from the signals 532 and 534 an execution end signal from the module that issued the execution start command, and when an end signal is detected, the process proceeds to S807-0.

In S807-0, the buffer status information held in the buffer status holding unit 530b used by the module that issued the execution start command is updated.
When the packet receiving unit 422 updates the buffer, the write state signal 538 is asserted to make the buffer state information held in the buffer state holding unit 530b full. When the DMA transmission unit 421 updates the buffer, the read state signal 537a is asserted to empty the buffer state information held in the buffer state holding unit 530b.
When the buffer status information held in the buffer status holding unit 530b is updated, the process proceeds to S808.

  In S808, if the processing end signal 539a from the packet receiving unit 422 is not transmitted, the process proceeds to S802, and if it is transmitted, the process proceeds to S809.

  Returning to the description of the transition to S810, when transitioning to S810, the buffer status information held in the buffer status holding unit 530b of the output control unit 530 is referred to, and if empty, the procedure transits to S803-1. If it is full, the process proceeds to S805-2.

When the process proceeds to S803-1, the output control unit 530 issues an execution start command from the signal 533 to the packet receiving unit 422, and the process proceeds to S804-1.
In step S804-1, the process waits until the execution end signal of the packet transmission unit 422 is received by the signal 534. If the end signal is detected, the process proceeds to step S805-1.
In S805-1, the synchronization signal 536 with the other intermediate buffer control unit 330 and the buffer write state signal 538 are asserted, and the process proceeds to S806-1.

  Returning to the description of the transition to S805-2, when transitioning to S805-2, the synchronization signal 536 with the other intermediate buffer control unit 330 is asserted, the buffer write state signal 538 is negated, The process proceeds to S806-1.

In step S806-1, the process waits for the synchronization signal 535 from the other intermediate buffer control unit 330. If it is received, the process proceeds to step S807-1.
In S807-1, the buffer state holding unit 530b uses the asserted signal among the write state signal 538 issued by the output synchronization unit 530a and the read state signal 537 issued from the other intermediate buffer control unit 330. Update the buffer status information. When the buffer state information held in the buffer state holding unit 530b is updated, the process proceeds to S808.
In step S808, an execution completion notification is sent from the signal 518 to the execution control unit 510, and the output control ends.

  An example of an operation for transmitting the output of the scanner image processing group 132 to the printer image processing group 133 via the intermediate buffer will be described with reference to FIG. FIG. 9 is a simplified diagram in which elements necessary for explaining the buffer sharing operation are extracted from FIG. 5 in order to explain a case where the output synchronization unit 530 on the scanner side and the input synchronization unit 520 on the printer side share the buffer. ing. First, when the intermediate buffer control unit a320 and the intermediate buffer control unit b330 receive an image processing execution start command from the CPU 111, the output control unit 530 and the input control unit 520 are activated.

Initially, as shown in FIG. 9A, since the intermediate buffer 342 contains no data, the buffer status information held in the buffer status holding unit 530b and the buffer status information held in the buffer status holding unit 520b are It becomes empty.
Therefore, the output synchronizer 530a on the scanner side activates the packet receiver, and asserts the write status signal 538 and the sync signal 536 of the buffer status information when reception of the packet is completed.
Since the buffer state information held in the buffer state holding unit 520b is empty in the input synchronization unit 520a on the printer side, the synchronization signal 525 is output without starting the packet transmission unit 412, and the other intermediate buffer control unit 330 is output. Wait for the synchronization signal 526 from.
When the synchronization signals are sent to each other, the buffer state information held in each of the buffer state holding units 530b and 520b is switched to full by the buffer write state signal 538, and the next execution is started in the state of FIG. 9B.

In FIG. 9B, since the buffer status information held in each of the buffer status holding units 530b and 520b is full, the synchronization signal 536 is output without starting the packet receiving unit 422 on the scanner side, and the other intermediate Wait for the synchronization signal 535 from the buffer controller. In the input synchronization unit 520 on the printer side, since the buffer status information held in the buffer status holding unit 520b is full, the packet transmission unit 412 is activated, and when the packet transmission is completed, the buffer status information read status signal 527 and Assert synchronization signal 525. When the synchronization signals are sent to each other, the buffer status information held in each of the buffer status holding units 530b and 520b is switched to empty by the buffer read status signal 527, and the next execution is started in the state of FIG. 9A.
As described above, it is possible to realize high-speed data transfer via the intermediate buffer 342 (without going through the DRAM) by synchronously updating the buffer status information in the different intermediate buffer control units 320 and 330, respectively. I can do it.

<Example 2>
In the first embodiment, the case where the image output unit 322 and the image input unit 331 on the scanner side access the same buffer 342 has been described as an example.
In the second embodiment, a configuration for realizing high-speed data sharing using a buffer efficiently will be described. In the second embodiment, the image output unit 322 and the image output unit 342 have a buffer configuration in which two buffers (for example, 342-1 and 342-2) are alternately accessed, and are synchronously controlled.

With reference to FIG. 10, a buffer sharing configuration in the second embodiment will be described. In the second embodiment, the buffer status information is arranged by the number of buffers to be managed, and each buffer status information is read and a write control signal is transmitted to realize a double buffer configuration.
A specific operation will be described below with reference to FIG. The buffer 1 state holding units 530b-1 and 520b-1 shown in FIG. 10 hold the state information of the buffer 342-1, and the buffer 2 state holding units 530b-2 and 520b-2 are the state information of the buffer 342-2. Holding.

First, when the intermediate buffer control unit a320 and the intermediate buffer control unit b330 receive an image processing execution start command from the CPU,
The output control unit 530 of the intermediate buffer control unit a320 and the input control unit 520 of the intermediate buffer control unit b330 are activated.
As shown in FIG. 10A, since no data is initially stored in both the intermediate buffers 1 and 2, the state information held in the buffer 1 state holding unit 520b-1 and the buffer 2 state holding unit 520b-2 are both empty. .

For this reason, the output synchronizer 530a on the scanner side activates the packet receiver 422, and asserts the write status signal 538-1 and the sync signal 536 of the buffer 1 status information when reception of the packet is completed.
In the input synchronization unit 520a on the printer side, since the state information of the buffer 1 is empty, the packet transmission unit 412 is not activated, transmits the synchronization signal 525, and waits for the synchronization signal 526 from the other intermediate buffer control unit 320. .
When the synchronization signals are sent to each other, the buffer write state signal 538-1 switches the state information of each buffer 1 to full, and the next execution is started in the state of FIG. 10B.

In FIG. 10B, the output synchronization unit refers to the buffer 2 state information held in the buffer 2 state holding unit 530b-2.
Since the buffer 2 status information is empty, the scanner-side packet receiving unit 422 is activated, and when the reception of the packet is completed, the buffer 2 status information write status signal 538-2 and the synchronization signal 536 are asserted.
The input synchronization unit 520 on the printer side refers to the buffer 1 status information held in the buffer 1 status holding unit 520b-1. Since the buffer 1 status information is full, the packet transmission unit 412 is activated, and when the packet transmission is completed, the read status signal 527-1 and the synchronization signal 525 of the buffer 1 status information are asserted.
When the synchronization signals are sent to each other, the status information of the buffer 1 is emptied by the buffer 1 read signal 527-1, the status information of the buffer 2 is made full by the write signal 538-2 of the buffer 2, and the state shown in FIG. Start the next execution.

In FIG. 10C, the output synchronization unit 530 refers to the buffer 1 state information held in the buffer 1 state holding unit 530b-1.
Since the buffer 1 status information is empty, the scanner-side packet receiving unit 422 is activated, and when the reception of the packet is completed, the writing status signal of the buffer 1 status information and the synchronization signal 538-1 are asserted.
The input synchronization unit 520 on the printer side refers to the buffer 2 status information held in the buffer 2 status holding unit 520b-2. Since the buffer 2 status information is full, the packet transmitter 412 is activated, and when the packet transmission is completed, the read status signal 527-2 and the synchronization signal 525 of the buffer 2 status information are asserted. When the synchronization signals are sent to each other, the buffer 2 read signal 527-2 empties the buffer 2 status information, the buffer 1 write status signal 538-1 fills the buffer status information 1 and the status shown in FIG. 10B. Starts the next execution.

  By adding a simple configuration as described above, even in a configuration in which two buffers are alternately accessed, high-speed data communication that simultaneously executes packet transmission and reception can be realized. Of course, the number of buffers shared by the plurality of intermediate buffer control units is not limited to two.

The effect of the parallel operation in the second embodiment will be described.
FIG. 16A shows a case where there is only one intermediate buffer (in the case of only intermediate buffer 1), and FIG. 16B shows a case where there are two intermediate buffers (in the case of intermediate buffers 1 and 2).

  As shown in FIG. 16A, when only the intermediate buffer 1 is used, writing from the output unit cannot be started unless the intermediate buffer 1 is empty, and the intermediate buffer 1 is full. If not, reading to the input unit cannot be started.

In particular,
The intermediate buffer 1 becomes full, and reading from the intermediate buffer 1 to the input unit is started (T11).
Reading from the intermediate buffer 1 to the input unit is completed (T12),
The intermediate buffer 1 becomes empty, and writing from the output unit to the intermediate buffer 1 is started (T13).
When the intermediate buffer 1 becomes full, reading from the intermediate buffer 1 to the input unit is started (T14).

On the other hand, as shown in FIG. 16B, when the intermediate buffer 1 and the intermediate buffer 2 are used, even if the intermediate buffer 2 does not become empty, if the intermediate buffer 1 becomes empty, the output is performed. Writing to the intermediate buffer 1 can be started. Even if the intermediate buffer 1 does not become empty, if the intermediate buffer 2 becomes empty, writing from the output unit to the intermediate buffer 2 can be started.
Even if the intermediate buffer 2 does not become full, reading from the intermediate buffer 1 to the input unit can be started if the intermediate buffer 1 becomes full. Even if the intermediate buffer 1 is not full, reading from the intermediate buffer 2 to the input unit can be started if the intermediate buffer 2 is full.

In particular,
The intermediate buffer 1 becomes full, and reading from the intermediate buffer 1 to the input unit is started (T21).
Writing from the output unit to the intermediate buffer 2 is started (T22),
Reading from the intermediate buffer 1 to the input unit is completed (T23),
Reading from the intermediate buffer 2 to the input unit is started (T24),
Writing from the output unit to the intermediate buffer 1 is started (T25),
Reading from the intermediate buffer 2 to the input unit is completed (T26).
Reading from the intermediate buffer 1 to the input unit is started (T27).

By using intermediate buffer 1 and intermediate buffer 2,
End of reading from the intermediate buffer 1 to the input unit (T23),
Between the start of reading from the intermediate buffer 1 to the input unit (T27),
Reading from the intermediate buffer 2 to the input unit has started (T24), and reading from the intermediate buffer 2 to the input unit has been completed (T26).

Similarly,
End of writing from the output unit to the intermediate buffer 1 (T21),
Between the start of writing to the intermediate buffer 1 from the output unit (T25),
Writing from the output unit to the intermediate buffer 2 has started (T22), and writing from the output unit to the intermediate buffer 2 has been completed (T24).

  As described above, the output unit uses the intermediate buffer 1 and the intermediate buffer 2 alternately, and the input unit also uses the intermediate buffer 1 and the intermediate buffer 2 alternately, thereby enabling high-speed data communication. .

<Example 3>
In the first embodiment, the sharing method of the intermediate buffer 342 in the case where the scan process and the print process are continuously executed has been described. In the third embodiment, a case where the image processing function included in the scan image processing circuit group 132 and the printer image processing circuit group 133 is applied to the image data a plurality of times will be described.

  In the scanner image processing circuit group 132, filter processing for reducing noise during scanning is applied to image data. The filter processing can remove noise having a low spatial frequency as the number of taps is increased. However, since the circuit scale increases as the number of taps of the filter increases, it is necessary to consider a configuration that balances the cost and the number of taps.

  Therefore, it is conceivable to apply a filter process with a large number of taps in a pseudo manner by applying a filter process with a small number of taps to image data a plurality of times. In the third embodiment, a configuration for realizing this processing using the intermediate buffer 342 efficiently will be described. However, description of portions having the same configuration as in the first embodiment will be omitted.

  FIG. 11 is a diagram illustrating the configuration of the synchronization execution unit 323 according to the third embodiment. Parts equivalent to the configuration of the synchronization execution unit 323 in the first embodiment illustrated in FIG. 5 are denoted by the same reference numerals and description thereof is omitted. The synchronization execution unit 323 of FIG. 11 includes a state information exchange unit 540 in addition to the configuration of the synchronization execution unit 323 of the first embodiment. The status information exchange unit 540 is a module that exchanges the buffer status information 520b of the input control unit 520 and the buffer status information 530b of the output control unit 530.

  Specifically, when the state information exchange unit 540 receives a state information exchange command from the execution control unit 510 from the signal 541, the state information exchange unit 540 performs control to switch the buffer state information 520b of the input control unit 520 and the buffer state information 530b of the output control unit 530. Do. When the exchange of the buffer status information is completed, completion is notified from the signal 541 to the execution control unit 510.

Here, the control sequence of the execution control unit 510 will be described with reference to FIG.
In step S1201, the execution control unit 510 sets the number of times the filter process is executed as the number of loops from the CPU 111, and waits for an interrupt signal 519 for starting image processing. If an interrupt is detected, the process proceeds to S1202.
In S1202, it is determined whether or not the CPU 111 has issued a specified number of execution start instructions. If it has been executed or if loop execution is unnecessary, the process proceeds to S1203-1, and if the specified number of times has not been executed, The process proceeds to S1203-0.

In step S1203-0, if the loop execution is the first time, the input side is set to share the intermediate buffer, and the output side is set not to share the intermediate buffer. If it is after the first loop execution, the input side and the output side are set not to share the intermediate buffer, and the process proceeds to S1204-0.
In S1204-0, an execution start command is issued to the input control unit 520 and the output control unit 530, and the process proceeds to S1205-0.

In step S1205-0, the process waits for execution end signals from the input-side control unit 520 and the output-side control unit 530. If both signals are received, the process proceeds to S1206.
In step S1206, the status information exchanging unit 540 is instructed to exchange buffer status information, and at the same time, settings such as which buffer the image input unit 321 and the image output unit 322 use are also exchanged. When the exchange is completed, the process proceeds to S1202.

Here, the case where the process proceeds to S1203-1 in S1202 will be described.
In S1203-1, the input side is set not to share the intermediate buffer, and the output side is set to share the intermediate buffer, and the process proceeds to S1204-1.
S1204-1 is the same as S1204-0, and S1205-1 and S1205-0 perform the same control and shift to S1207.
In step S <b> 1207, the CPU 111 is notified of an image processing end interrupt.

Next, the control sequence of the input control unit 520 will be described with reference to FIG.
In S1301, the execution control unit 510 waits for the execution start command 515, and when it is received, the process proceeds to S1302.
If it is determined in S1302 that loop execution is not performed for the first time or loop processing, the process proceeds to S1303-0, and if loop execution is performed for the second time to the last time, the process proceeds to S1310.
In S1303-0, referring to the input sharing setting, if the setting is made so that the intermediate buffer 342 is shared, the process proceeds to S1310, and if the setting is set not to share, the process proceeds to S1304-0.
Since steps S1304-0 and S1310 are the same as those in steps S703-0 and S710 in FIG.

Next, the control sequence of the output control unit 530 will be described with reference to FIG.
In step S1401, the execution control unit 510 waits for the execution start instruction 517. When the execution start instruction 517 is received, the process proceeds to step S1402.
If the loop process is not performed in S1402 or if the final loop process is executed, the process proceeds to S1403. If the loop process is executed immediately before the first to the last process, the process proceeds to S1410.
In S1403, with reference to the output sharing setting, if the setting is made so that the intermediate buffer is shared, the process proceeds to S1404-1, and if the setting is set not to share, the process proceeds to S1410.
Since S1404-0 and S14010 and after are the same controls as S803-0 and S810 in FIG.
With the configuration described above, the same image processing can be applied to image data a plurality of times while efficiently using the intermediate buffer.
<Other examples>
The present invention can also be realized by supplying a storage medium storing a computer program code of software that implements the functions of the above-described embodiments to a system or apparatus. In this case, the function of the above-described embodiment is realized by reading and executing the computer program code stored in the storage medium so as to be readable by the computer (or CPU or MPU) of the system or apparatus.

100 image processing apparatus 110 system control unit 120 scanner control unit 130 image processing unit 140 printer control unit 310 DMA controller 320 intermediate buffer control unit a
321 Image input unit 322 Image output unit 323 Synchronization execution unit

Claims (6)

A data control device comprising a plurality of intermediate buffer control means,
The intermediate buffer control means includes
Input means for controlling data transfer from the DRAM to the intermediate buffer and data transfer from the intermediate buffer to the data processing means;
Output means for controlling data transfer from the data processing means to the intermediate buffer and data transfer from the intermediate buffer to the DRAM;
Synchronization holding means for holding buffer status information of the input means and the output means, respectively, and controlling operations of the input means and the output means according to the buffer status information,
The synchronization execution means includes
When the execution completion notification is received from the input means, the buffer status information of the input means is set to the write state,
When the execution completion notification is received from the output means, the buffer status information of the output means is set as a read state,
When the intermediate buffer is shared with other intermediate buffer control means, the synchronization execution means of the other intermediate buffer control means and the buffer status information are mutually transmitted,
When the intermediate buffer is not shared with other intermediate buffer control means, the buffer status information of the input means and the buffer status information of the output means are sent to each other,
A data control apparatus for updating buffer status information of each synchronization execution means by a synchronization signal. When the data is transferred from the intermediate buffer to the data processing unit, the input unit adds a transfer start signal to the data at the start of transfer and transfers the data to the data processing unit. When the transfer of a predetermined amount of data is completed, the transfer ends. Adding a signal to the data and transferring it to the data processing means;
The output means, when transferring data from the data processing means to the intermediate buffer control means, receives a received data amount from a data amount transferred between receiving the transfer start signal and receiving the transfer end signal. Calculating the received data amount to the synchronization execution means,
The data control apparatus according to claim 1, wherein the synchronization execution unit calculates an address on a DRAM accessed by the input unit based on the received data amount. The first intermediate buffer control means shares the intermediate buffer with the second intermediate buffer control means;
The synchronization execution means of the second intermediate buffer control means is accessed by the input means of the second intermediate buffer control means based on the received data amount calculated by the output means of the first intermediate buffer control means. 3. The data control apparatus according to claim 2, wherein an address on the DRAM is calculated. As the amount of data transferred by the input means, the number of pixels in the main scanning direction and the number of pixels in the sub-scanning direction of the image data are set,
At the start of transfer of the image data, a transfer start signal and a line start signal are added to the image data,
At the end of the transfer of the image data, a transfer end signal and a line end signal are added to the image data,
When data transfer of the first pixel in the sub-scanning direction of the image data is performed, a line start signal is added,
When data transfer of the final pixel in the sub-scanning direction of the image data is performed, a line end signal is added and transferred to the data processing unit,
The output means uses the number of pixels from detection of the line start signal added to data transferred from the data processing means to detection of the line end signal as the received data amount. Item 4. The data control device according to Item 2 or 3. A first data processing unit related to scan processing and a second data processing unit related to print processing;
The first intermediate buffer control means controls data transfer related to the first data processing means;
5. The data control apparatus according to claim 3, wherein the second intermediate buffer control unit controls data transfer related to the second data processing unit. A control method of a data control device comprising a plurality of intermediate buffer control means,
The intermediate buffer control means includes
Input means for controlling data transfer from the DRAM to the intermediate buffer and data transfer from the intermediate buffer to the data processing means;
Output means for controlling data transfer from the data processing means to the intermediate buffer and data transfer from the intermediate buffer to the DRAM;
Synchronization holding means for holding buffer status information of the input means and the output means, respectively, and controlling operations of the input means and the output means according to the buffer status information,
The synchronization execution means includes
When the execution completion notification is received from the input means, the buffer status information of the input means is set to the write state,
When the execution completion notification is received from the output means, the buffer status information of the output means is set as a read state,
When the intermediate buffer is shared with other intermediate buffer control means, the synchronization execution means of the other intermediate buffer control means and the buffer status information are mutually transmitted,
When the intermediate buffer is not shared with other intermediate buffer control means, the buffer status information of the input means and the buffer status information of the output means are sent to each other,
A data control method characterized by updating buffer status information of each synchronization execution means by a synchronization signal.

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