JP2014130425A - Image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image forming apparatus which performs arbitration control in a format where a command is separated from data and the data is transferred after transferring the command, without software load.SOLUTION: In an image forming apparatus relating to this invention, exclusive control modules 312, 313 which perform exclusive control between a NAND controller (NANDC) 303, an HDD controller (HDDC) 304, and a bus arbiter 306 in an image controller (SoC) 301, are provided with buffers for storing a plurality of commands and image data. Only when receiving image data corresponding to the commands and controlled by the same CPU (one of a CPUA309, and a CPUB310), the modules 312, 313 transfer sets of commands and image data, and the NAND controller (NANDC) 303 and the HDD controller (HDDC) 304 perform control to store the sets of commands and image data on a NAND memory and an HDD memory.

Description

  The present invention relates to an image forming apparatus having a function in which command and data are separated and arbitration control is performed in a transfer format in which data is transferred after command transfer.

  2. Description of the Related Art Conventionally, in a controller ASIC in an MFP (multifunction printer) that has developed a usage form of an image forming apparatus, if a plurality of masters simultaneously access an area, data transfer cannot be performed normally. Arbitration control is performed to prevent access to the same address at the same time. For example, a case where arbitration control is performed by a bus interconnect, a PCI interface, a PCI Express interface, or the like is known.

  As a well-known technique related to such arbitration control, for example, there is an “image forming apparatus” (see Patent Document 1) that can easily execute data transfer between applications with a low-cost configuration.

  In the technology of the image forming apparatus according to Patent Document 1 described above, a plurality of applications such as a facsimile application and a printer application and each unit configuring the apparatus are managed as a shared resource in units of functions, and the plurality of applications use the shared resource. A main controller that performs arbitration, an application bus that connects the main controller and a plurality of applications, and a memory that is arranged as one of the shared resources. It manages data transfer when performing data transfer, and has a function capable of realizing arbitration control in the controller of a multi-function printer having a plurality of masters.

  However, in the technique according to Patent Document 1, arbitration control is made to correspond to a transfer format in which commands and data such as a NAND interface connected to a NAND circuit (NAND memory) are separated, for example, without software intervention. In such a case, since it is necessary to perform semaphore control with software, a problem arises in that a software load is generated and performance is degraded.

  That is, the existing arbitration control has a problem that it is difficult to cope with a transfer format in which commands and data such as a NAND interface are separated. For example, if slave device A receives a command from master A after receiving a command from master A and then receives data from master A, the command from master A will be overwritten and correct. This can be explained with an example in which transfer is not performed. Therefore, when arbitration control is performed using a transfer format in which commands and data are separated, software semaphore control must be performed. This causes performance degradation due to software load. End up.

  The present invention has been made to solve such problems, and its technical problem is that command and data are separated, and arbitration control can be implemented without a software load in a format in which data is transferred after command transfer. An object is to provide an image forming apparatus.

  In order to solve the above technical problem, according to the present invention, an image forming apparatus having a function of storing input image data in a negative AND storage means by a plurality of control instruction means provided in the image control means. The image control means includes a negative logical product control means capable of transferring the image data to the negative logical product storage means by sequentially inputting a command and image data, a data buffer, and a command buffer. And an exclusive control means for converting the image data and the command into a sequence received by the negative AND control means when the image data and the command are transferred asynchronously from the plurality of control instruction means, and a plurality of control instruction means And bus arbitration means for arbitrating a plurality of control systems connected to the exclusive control means by a bus, and a plurality of exclusive control means are provided via the bus arbitration means. Only when image data under the control of the same control instruction means matching the command to the data buffer in the control instruction means is received, the command and the image data are set and transferred to the negative AND control means. It is characterized by.

  According to the image forming apparatus of the present invention, a plurality of commands and image data are stored in the slave function exclusive control means that performs exclusive control between the negative logical product control means and the bus arbitration means in the image control means. Because the exclusive control means has a function to transfer the command and the image data as a set only when image data is received under the control of the same control instruction means that matches those commands. It is possible to implement exclusive control without performing software semaphore control, the command and data are separated, and the arbitration control can be implemented without software load with a format interface that transfers data after command transfer, and high performance Will be able to provide.

1 is a block diagram illustrating a basic configuration of an image forming apparatus according to Embodiment 1 of the present invention. FIG. 2 is a block diagram illustrating a detailed configuration of an image controller according to a comparative example as an application example of the image controller provided in the image forming apparatus illustrated in FIG. 1. FIG. 3 is a comparison diagram of transactions shown for explaining a transfer result at a transfer timing by a NAND controller (NANDC) and a DDR controller (DDRC) in the image controller shown in FIG. 2. FIG. 2 is a block diagram illustrating a detailed configuration of the image controller according to the first embodiment as an application example of the image controller provided in the image forming apparatus illustrated in FIG. 1. FIG. 5 is a schematic diagram illustrating a flow of processing functions in a detailed configuration of the exclusive control module according to the first embodiment as an application example of the exclusive control module provided in the image controller illustrated in FIG. 4. FIG. 6 is a comparison diagram of transactions shown for explaining a transfer function by the exclusive control module shown in FIG. 5.

  Hereinafter, an image forming apparatus of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a basic configuration of an image forming apparatus according to Embodiment 1 of the present invention. In this image forming apparatus, image data input from the scanner 101 serving as an image reading unit is read in accordance with a program read from the ROM 105 by a plurality of control instruction units (CPU) provided in an image controller (SoC) 102 serving as an image control unit. Accumulated and stored in the DDR memory 106, which is the main storage means connected to the image controller (SoC) 102, the HDD memory 104, which is the auxiliary storage means, and the NAND memory 103, which is the negative AND storage means, according to applications. In addition, it has an MFP function for outputting image data to a plotter 107 as image output means connected to an image controller (SoC) 102. The image controller (SoC) 102 here has a function of performing arbitration control with the MFP function.

FIG. 2 is a block diagram illustrating a detailed configuration of an image controller (SoC) 201 according to a comparative example as an application example of the image controller (SoC) 102 provided in the image forming apparatus. The image controller (SoC) 201 includes a scanner input PCI Express controller (PCIe) 202 connected to the scanner 101 serving as an image reading unit, a NAND controller (NANDC) 203 connected to the NAND memory 103, and the HDD memory 104. Controller (HDDC) 204 connected to, a local bus controller (LBC) 205 connected to the local bus shown schematically, and a DDR controller (DDRC) 208 connected to DDR memory 207 (same as DDR memory 106). When the control instruction first _CPU is means - A209 and the second _CPU - and B 210, and the plotter output PCI eexpress controller (PCIe) 211 to be connected to the plotter 107, but is a bus regulating means It is formed by connecting in common to Suabita 206.

In the image controller (SoC) 201, the image data input from the scanner input PCI Express controller (PCIe) 202 is stored in the DDR memory 207 via the bus arbiter 206 and the DDR controller (DDRC) 208. The image data stored in the DDR memory 207 is sent to the NAND controller (NANDC) 203 and the HDD controller via the DDR controller (DDRC) 208 and the bus arbiter 206 according to the control instructions of the first CPU _- A209 and the second CPU _- B210. After being stored in the external NAND memory 103 and HDD memory 104 from the (HDDC) 204, the NAND controller (NANDC) 203 and the HDD controller (HDDC) 204 are stored in the DDR memory 207 via the bus arbiter 206 and DDR controller (DDRC) 208. The accumulated data is further output to the plotter 107 via a plotter output PCI Express controller (PCIe) 211 in accordance with control instructions from the first CPU _-A 209 and the second CPU _- B 210.

  Incidentally, the scanner input PCI Express controller (PCIe) 202 in FIG. 2 can access the NAND controller (NANDC) 203 or the HDD controller (HDDC) 204 via the bus arbiter 206. The NAND controller (NANDC) 203 can transfer image data to the NAND memory 103 by sequentially inputting a command and image data. The HDD controller (HDDC) 204 can transfer image data to the HDD memory 104 by sequentially inputting a command and image data. A plotter output PCI Express controller (PCIe) 211 can access the NAND controller (NANDC) 203 or the HDD controller (HDDC) 204 via the bus arbiter 306.

  FIG. 3 is a comparison diagram of transactions 501, 502, and 503 shown to explain the transfer results at the transfer timings of the NAND controller (NANDC) 203 and the DDR controller (DDRC) 208 in the image controller (SoC) 201 described above. It is.

Referring to FIG. 3, the NAND controller (NANDC) 203 and the HDD controller (HDDC) 204 perform the arbitration control synchronously from the first CPU _-A 209 and the second CPU _- B 210, thereby As shown in the transaction 501 from the CPU _-A 209 and the transaction 502 from the second CPU _- B 210, the commands (CmdA, CmdB) are first transferred via the bus arbiter 206, and then the data (DataA, DataB) are transferred. The operation is performed.

However, when the arbitration control is asynchronously turned down from the first CPU _-A 209 and the second CPU _- B 210, which are a plurality of control instruction systems, the NAND controller (NANDC) 203 and the HDD controller (HDDC) 204 have transactions. As shown in 505, the order of the command and the data is not guaranteed, and the command (CmdA), the command (CmdA), not the command (CmdA), the data (DataA), the command (CmdB), and the data (DataB) in regular order. As shown in the order of CmdB), data (Data A), and data (Data B), transfer in the normal order is not established.

  In order to prevent such a problem, the existing technology creates a flag area of “Which CPU has the bus right of the NAND controller (NANDC) 203 and the HDD controller (HDDC) 204” on the memory such as the ROM 105 by software. Then, a flag is set each time the transfer of each CPU is started, and the CPU that cannot obtain the access right by dropping the flag at each completion performs exclusive control by monitoring this flag area by polling or the like.

  However, in such exclusive control involving software, when one CPU occupies the access right, transfer by the other CPU is not performed, so the NAND controller (NANDC) 203, the HDD controller (HDDC) The transfer bandwidth of 204 itself is not effectively used, and the transfer performance of the entire apparatus is degraded. If the transfer performance of the entire apparatus is deteriorated, for example, in an applied copying machine, an abnormal image is generated, which causes a problem.

FIG. 4 is a block diagram illustrating a detailed configuration of an image controller (SoC) 301 according to the first embodiment as an application example of the image controller (SoC) 102 provided in the above-described image forming apparatus. The image controller (SoC) 301 has a scanner input PCI Express controller (PCIe) 302, NAND controller (NANDC) 303, HDD controller (similar to the configuration of the comparative example of FIG. HDDC) 304, local bus controller (LBC) 305, bus arbiter 306, first CPU _-A 309 and second CPU _- B 310 as control instruction means, and a PCI Express controller (PCIe) 311 for plotter output.

In addition, the image controller (SoC) 301 includes a data buffer and a command buffer between the NAND controller (NANDC) 303 and the bus arbiter 306, and the first CPU _-A 309 and the second buffer via the bus arbiter 306. An exclusive control module 312 is interposed as an exclusive control means for performing exclusive control when the image data and the command are transferred asynchronously from the CPU _- B 310 and converting them into the order received by the NAND controller (NANDC) 303. together comprise a data buffer and a command buffer also between the HDD controller (HDDC) 304 and bus arbiter 306, the first _CPU via a bus arbiter 306 - A309 and the second _CPU - image data from the B310 and commands Is different in that an exclusive control module 313 is interposed as another exclusive control means for performing exclusive control and converting to the order received by the HDD controller (HDDC) 304 when the data is transferred asynchronously. .

The exclusive control module 312 here only receives image data by the same control that matches the command to the data buffer in the first CPU _-A 309 and the second CPU _- B 310 via the bus arbiter 306. The command and image data are set and transferred to the NAND controller (NANDC) 303. The exclusive control module 313 receives the image data by the same control that matches the command to the data buffer in the first CPU _-A 309 and the second CPU _- B 310 via the bus arbiter 306 only. The command and image data are set and transferred to the HDD controller (HDDC) 304.

  FIG. 5 is a schematic diagram illustrating a flow of processing functions in a detailed configuration of the exclusive control module 401 according to the first embodiment as an application example of the exclusive control modules 312 and 313 provided in the image controller (SoC) 301. The exclusive control module 401 includes an interface (I / F) unit 402, an arbiter unit 403, a command / data buffer unit 404, and a selector unit 405.

Among these, the interface (I / F) unit 402 is configured by, for example, an AXI or OCP interface (I / F) and has an interface (I / F) function with the bus arbiter 306. The arbiter unit 403 determines which CPU has accessed the exclusive control module 401 and whether the transaction is a command or data, and sends the command and data of the determination result to the command / data buffer unit 404. Has a function to distribute. The command / data buffer unit 404 is composed of a plurality of commands, data buffers that sequentially hold the commands distributed by the arbiter unit 403, and data buffers. The selector unit 405 determines the case where the transfer of both the command and the data from the same CPU (indicating the first CPU _- A309 or the second CPU _- B310) is completed, and sets the completed command and data. Is transferred to the NAND controller (NANDC) 303 or the HDD controller (HDDC) 304.

  FIG. 6 is a comparison diagram of the transactions 601 and 602 shown for explaining the transfer function by the exclusive control module 401 described above.

In FIG. 6, as the input timing to the exclusive control module 401, the first CPU _-A 309 and the second CPU _- B 310 access asynchronously, and a set of commands and data is set as in the transaction 505 shown in FIG. Assume a condition in which the transaction is a transaction 601 that does not match and cannot be transferred correctly by the NAND controller (NANDC) 303 and the HDD controller (HDDC) 304 as they are.

Therefore, when the exclusive control module 401 first receives a command from the first CPU _-A 309, the exclusive control module 401 accumulates the command in the command buffer and then maintains the command until the data from the first CPU _-A 309 is transferred. In the meantime, even if a command is input from the second CPU _- B 310, it is only stored in the command buffer, and is not output to the NAND controller (NANDC) 303 and the HDD controller (HDDC) 304.

Thereafter, when the data transfer from the first CPU _-A 309 is completed, the command and data are output as a set to the NAND controller (NANDC) 303 and the HDD controller (HDDC) 304 to complete the correct transfer. It has a function to let you.

That is, in the image forming apparatus according to the first embodiment, the first CPU _-A 309 and the second CPU _- B 310 transmit commands to the NAND controller (NANDC) 303 via the bus arbiter 306 and the exclusive control module 312. Thereafter, the image data is read from the DDR memory 307 via the DDR controller (DDRC) 308 and transferred to the NAND controller (NANDC) 303 via the exclusive control module 312 via the bus arbiter 306. At this time, when the exclusive control module 312 receives a command from one of the first CPU _-A 309 and the second CPU _- B 310, the command is accumulated in the command buffer, and then the first CPU _-A 309, the first CPU _-A 309, The image data from one of the two CPUs _- B310 is maintained until it is transferred, and even if a command is input from the other of the first CPU _- A309 and the second CPU _- B310 during that time, it is only stored in the command buffer. Is not output to the NAND controller (NANDC) 303, and when the transfer of image data from one of the first CPU _- A309 and the second CPU _- B310 is completed, a command is sent to the NAND controller (NANDC) 303. And image data are output as a set. As a result, the NAND controller (NANDC) 303 performs control to store a set of commands and image data in the NAND memory 103.

According to this image forming apparatus, in the image controller (SoC) 301, a plurality of commands and image data are transmitted to the slave function exclusive control module 312 that performs exclusive control between the NAND controller (NANDC) 303 and the bus arbiter 306. Only when image data is received under the control of the same CPU (in this case, one of the first CPU _- A309 and the second CPU _- B310) matching the commands. The exclusive control module 312 has a function of transferring a command and image data together as a set. For this reason, exclusive control can be implemented without performing software semaphore control, and command and image data are separated, and arbitration control is implemented without software load by an interface in a format that transfers image data after command transfer. And will be able to provide high performance.

Similarly, the first CPU _-A 309 and the second CPU _- B 310 transmit a command to the HDD controller (HDDC) 304 via the exclusive control module 313 via the bus arbiter 306 and then the DDR controller (DDRC). The image data is read from the DDR memory 307 via 308 and transferred to the HDD controller (HDDC) 304 via the exclusive control module 313 via the bus arbiter 306. At this time, when the exclusive control module 313 receives a command from one of the first CPU _- A309 and the second CPU _- B310, the exclusive control module 313 accumulates the command in the command buffer, and then the first CPU _- A309, The image data from one of the two CPUs _- B310 is maintained until it is transferred, and even if a command is input from the other of the first CPU _- A309 and the second CPU _- B310 during that time, it is only stored in the command buffer. Is not output to the HDD controller (HDDC) 304, and a command is sent to the HDD controller (HDDC) 304 when transfer of image data from one of the first CPU _- A309 and the second CPU _- B310 is completed. And image data are output as a set. As a result, the HDD controller (HDDC) 304 performs control to store a set of commands and image data in the HDD memory 104. As described above, if the HDD memory 104 is also used as an exclusive control target, it is possible to store a large amount of image data as compared with the case where the NAND memory 103 is used alone.

  4 is connected to the NAND controller (NANDC) 303 or the HDD controller (HDDC) 304 via the bus arbiter 306 and the exclusive control module 312 or the exclusive control module 313. Can be accessed. By enabling access to the NAND controller (NANDC) 303 and the HDD controller (HDDC) 304 from the PCI Express controller (PCIe) 302 for scanner input, the effective bandwidth at the time of image data input in the scanner 101 is improved. The reading speed of the scanner 101 can be improved.

  The NAND controller (NANDC) 303 can transfer image data to the NAND memory 103 by sequentially inputting a command and image data. The HDD controller (HDDC) 304 can transfer image data to the HDD memory 104 by sequentially inputting a command and image data.

  Further, the PCI Express controller (PCIe) 311 for plotter output can access the NAND controller (NANDC) 303 or the HDD controller (HDDC) 304 via the exclusive control module 312 or the exclusive control module 313 via the bus arbiter 306. It is a thing. By enabling access to the NAND controller (NANDC) 303 and HDD controller (HDDC) 304 from the PCI Express controller (PCIe) 311 for plotter output, the effective bandwidth at the time of image data output by the plotter 107 is improved. The printing speed can be improved.

In addition, for the DDR controller (DDRC) 308, image data is read from the DDR memory 307 and transferred to the NAND controller (NANDC) 303 via the exclusive control module 312 via the bus arbiter 306, or via the exclusive control module 313. It is preferable to provide a DMAC function that can be transferred to the HDD controller (HDDC) 304. In this case, since the transfer function of the image data can be substituted by the DMAC function instead of the control instruction by the first CPU _- A309 and the second CPU _- B310, the load of software control can be reduced. In addition, for the exclusive control modules 312, 313, the bandwidth assigned by the transfer of the control instruction by the first CPU _- A309 and the second CPU _- B310 can be set by software (the bandwidth assigned to each CPU can be set). Thus, the bus bandwidth can be used effectively. In other words, the image forming apparatus of the present invention is not limited to the one in the form of the first embodiment described with reference to FIGS.

101 Scanner 102, 201, 301 Image controller (SoC)
103 NAND memory 104 HDD memory 105 ROM
106, 207, 307 DDR memory 107 Plotter 202, 302 PCI Express controller (PCIe) for scanner input
203, 303 NAND controller (NANDC)
204, 304 HDD controller (HDDC)
205,305 Local bus controller (LBC)
206, 306 Bus arbiter 208, 308 DDR controller (DDRC)
209, 309 First CPU
210, 310 Second CPU
211, 311 PCI Express controller (PCIe) for plotter output
312, 313, 401 Exclusive control module 402 Interface (I / F) unit 403 Arbiter unit 404 Command / data buffer unit 405 Selector unit

JP 2000-122881 A

Claims (6)

An image forming apparatus having a function of storing input image data in a negative AND storage means by a plurality of control instruction means provided in the image control means,
The image control means includes a negative logical product control means capable of transferring the image data to the negative logical product storage means by sequentially inputting a command and the image data, a data buffer, and a command buffer. And exclusive control means for performing exclusive control when the image data and the command are transferred asynchronously from the plurality of control instruction means and converting them into an order received by the negative AND control means, and Bus arbitration means for arbitrating a plurality of control systems connected to the plurality of control instruction means and the exclusive control means,
The exclusive control means receives the image data only when receiving the image data under the control of the same control instruction means that matches the command to the data buffer in the plurality of control instruction means via the bus arbitration means. And the image data are transferred as a set to the negative logical product control means. 2. The image forming apparatus according to claim 1, wherein the image control unit is connected to the bus arbitration unit and transfers the image data to the auxiliary storage unit by sequentially inputting a command and the image data. Auxiliary storage control means, a data buffer and a command buffer that can be used, and are connected to the bus arbitration means and exclusive when the image data and the command are transferred asynchronously from the plurality of control instruction means And other exclusive control means for controlling and converting to the order received by the auxiliary storage control means,
Only when the other exclusive control means receives the image data by the control of the same control instruction means that matches the command to the data buffer in the plurality of control instruction means via the bus arbitration means, An image forming apparatus, wherein the command and the image data are transferred as a set to the auxiliary storage control unit. 3. The image forming apparatus according to claim 1, wherein the image control unit is connected to the bus arbitration unit, stores the image data in a main storage unit, and performs control for reading the image data. Main memory control means,
The main memory control means reads the image data from the main memory means and transfers the image data to the negative logical product control means via the exclusive control means, or the auxiliary memory control via the other exclusive control means. An image forming apparatus having a DMAC function for transfer to a means.   4. The image forming apparatus according to claim 3, wherein the exclusive control unit or the other exclusive control unit can set a band to be allocated by transfer of the plurality of control instruction units by software.   4. The image forming apparatus according to claim 3, wherein the image control unit includes the negative logical product control unit or the auxiliary storage control unit via the bus arbitration unit and the exclusive control unit or the other exclusive control unit. An image forming apparatus comprising an image reading control unit capable of accessing the image forming apparatus.   4. The image forming apparatus according to claim 3, wherein the image control unit includes the negative logical product control unit or the auxiliary storage control unit via the bus arbitration unit and the exclusive control unit or the other exclusive control unit. An image forming apparatus comprising an image output control unit capable of accessing the image forming apparatus.

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