JP4909839B2 - Image processing apparatus and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor and an image processing method for efficiently transferring data by switching DMA controllers as necessary whose transfer speeds are different. <P>SOLUTION: A multifunction machine preferentially transfers image data processed by an image processing part 11 by using a high speed DMAC 15, and when it is detected that the transfer of the image data processed by the image processing means 11 has been completed by a data input detection part 11a, a management part 14 controls a selector 13 on the basis of the transfer state of the image data processed by an image processing part 12 detected by a data processing progress detection part 12a, and transfers the image data processed by the image processing part 12 by selecting a low speed DMAC 16 and a high speed DMAC 15 as necessary for use. Therefore, it is possible to improve the overall productivity of the image processing by processing the image data processed by the image processing part 12 according to the flow of the image data of the image processing step of the whole multifunction machine. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to an image processing apparatus and an image processing method, and more particularly, to an image processing apparatus and an image processing method that perform efficient data transfer by appropriately using DMA controllers having different transfer rates.

  In recent years, various image processing using a semiconductor memory such as a RAM (Random Access Memory) has been performed in an image processing apparatus such as a copying apparatus, a printer apparatus, a facsimile apparatus, or a composite apparatus in accordance with the combination and digitization. It is becoming. There is DMA (Direct Memory Access) as a technique for transferring data to the memory or transferring data on the memory at high speed. In DMA, generally, a memory address and a transfer amount are specified. Data transfer is performed without intervention of a CPU (Central Processing Unit), but when data is scattered on the memory, the data scattered on the memory is connected continuously using the descriptor method. To transfer to.

  The image processing apparatus incorporates a DMA controller (hereinafter referred to as “DMAC”) in each image processing unit, but its performance varies, and a high-speed machine such as a composite apparatus has a mechanical structure. Depending on conditions, there is an image processing module with a high processing speed due to the need to ensure high productivity. Such a high-priority image processing module includes a DMAC (hereinafter referred to as a high-speed DMAC) with a relatively high transfer speed. In other image processing modules, a DMAC having a relatively low transfer rate (hereinafter referred to as a low-speed DMAC) is inevitably mounted.

  In an image processing apparatus such as a copying apparatus having an image input unit, an interval of an image input time is defined due to restrictions on its mechanical operation and the like, and a high-speed DMAC is assigned to the image input processing unit (video controller). ing.

  However, no matter how much high-speed DMAC is installed in the image input processing unit and image input processing is performed at high speed, if image processing in the subsequent image processing unit (for example, a compression / decompression unit) does not end, the next image input Can not do.

  Therefore, as shown in FIG. 6A, when the image processing in the subsequent image processing unit such as the compression / decompression unit is performed following the image processing in the video controller as the preceding image processing unit, Although an appropriate processing speed can be maintained, as shown in FIG. 6B, when image processing in the subsequent image processing unit such as a compression / decompression unit is slow, image processing in the subsequent image processing unit is performed. Waiting for the end of the image processing, it is necessary to perform the image processing of the previous stage, that is, the image input processing by the video controller, the interval of the image input time becomes irregular, and the productivity is reduced. Become.

  Conventionally, common control is performed on storage devices having a common configuration regardless of the configuration of the image forming apparatus, and information transfer between devices of the image forming apparatus (necessary for control between image signals and devices). There has been proposed a technique for more efficiently performing (including information) (see Patent Document 1).

JP 2005-72987 A

  However, in the prior art described in the above publication, it is possible to improve the data use efficiency among a plurality of image forming apparatuses, but the image processing speed and DMAC transfer speed in one image processing apparatus are improved. Due to the difference, the stagnation of data generated between the image processing modules cannot be eliminated, and improvement is necessary to improve the productivity of the entire image processing apparatus.

  Accordingly, an object of the present invention is to provide an image processing apparatus and an image processing method that improve the overall productivity by efficiently transferring data in consideration of the image processing speed and data transfer speed of each stage. .

Billing an image processing apparatus of the present invention in a first aspect, the first image processing means for processing images in the image data, located in the flow direction downstream of the image data than the first image processing means and the first and second image processing means for image processing at a slower processing speed than the image processing unit, DMA image data and the first DMA controller for D MA transfer image data at a slower rate than the first DMA controller the second DMA controller for transferring, causes transferred in preference to the image data processed in the first image processing unit to the first DMA controller, the processed image data of the first image processing means Based on the transfer status of the image data processed by the second image processing means, the second DMA controller and the first DMA controller are appropriately selected and the selection is made. Transfer control means for transferring the image data processed by the second image processing means to the DMA controller, and the first DMA controller and the second DMA controller each temporarily store image data. A buffer status detecting means for detecting the image data storage status of the buffer; and a notifying means for notifying the detection result of the buffer status detecting means to each other; Based on the detection result of the buffer state detection unit and the notification result from the notification unit of the partner DMA controller, the image data from the second image processing unit is sequentially switched to transfer the image data. The transfer amount of the image data processed by the second image processing means, the first DMA controller, and the first As the DMA controller for transferring the image data processed by the second image processing means according to the comparison result with the threshold set according to the buffer capacity of the DMA controller, the first DMA controller and the The above object is achieved by switching and selecting the second DMA controller .

In this case, for example, as described in claim 2, the image processing apparatus includes a transfer end detection unit that detects a transfer end of image data processed by the first image processing unit, and the second image processing. comprising a transfer state detecting means for detecting the transfer status of the image data to be processed means, said transfer control means, based on a detection result of the transfer completion detecting means and said transfer status detecting means, the second image A DMA controller used for transferring image data processed by the processing means may be selected.

In the case of claim 2, for example, as described in claim 3, the transfer end detection unit acquires in advance the amount of image data processed by the first image processing unit or the transfer time of the image data. The transfer end may be detected based on the image data amount or the transfer time.

Further, in the case of claim 2 or claim 3, for example, as described in claim 4, after the transfer end detection unit detects the transfer end, the transfer control unit detects the transfer state detection unit. When it is detected that there is untransferred image data processed by the second image processing means, the first DMA is used as a DMA controller used for transferring the image data processed by the second image processing means. A controller may be selected.

In the case of claims 1 to 4, for example, as described in claim 5, the transfer control means includes the first image processing means, the second image processing means, and the first DMA. There may be provided switching connection means for selectively connecting the controller and the second DMA controller, and control means for controlling a connection state by the switching connection means.

The image processing method of the invention described in claim 6, the first image processing step of processing images in the image data, located in the flow direction downstream of the image data than the first image processing step the first a second image processing step of the image processing at a slower processing speed than the image processing steps, thereby transferring the first image processed image data processed in step in preference to the first DMA controller for D MA transfer At the same time, based on the transfer status of the image data processed in the first image processing step and the image data processed in the second image processing step, DMA transfer is performed at a slower speed than the first DMA controller. A second DMA controller and the first DMA controller are appropriately selected, and the selected DMA controller is processed in the second image processing step. A transfer control processing step for transferring the processed image data; a buffer amount of the first DMA controller and the second DMA controller; and the first DMA controller and the second DMA controller. The image data from the second image processing means is sequentially switched based on the detection result of the buffer state detection means including the detection result of the buffer state detection means notified from one DMA controller from the other DMA controller. A result of comparison between the transfer step and the transfer amount of the image data processed by the second image processing means and a threshold set in accordance with the capacity of the buffers of the first DMA controller and the second DMA controller According to the DMA controller for transferring the image data processed by the second image processing means. As over la, by a step of selecting by switching to the first DMA controller and the second DMA controller, it has achieved the above objects.

According to the present invention, the image data processed by the first image processing unit is preferentially transferred by the first DMA controller, and the image data processed by the first image processing unit and the second image processing unit Since the second DMA controller and the first DMA controller are appropriately selected based on the transfer status of the processed image data and the image data processed by the second image processing means is transferred, the first image processing means In consideration of the image processing speed of the second image processing means and the data transfer speed of the first DMA controller and the second DMA controller, the image data processed by the second image processing means is efficiently transferred. it can, by the image data processing of the second image processing unit to transfer processing in accordance with the flow of image data of the entire image processing steps, improve image processing overall productivity Door can be.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The scope of the present invention limits this invention especially in the following description. As long as there is no description of the effect, it is not restricted to these aspects.

  1 to 3 are diagrams showing a first embodiment of an image processing apparatus and an image processing method according to the present invention, and FIG. 1 applies the first embodiment of the image processing apparatus and the image processing method according to the present invention. 2 is a block diagram of the main part of the composite apparatus 1. FIG.

  In FIG. 1, the composite apparatus 1 includes an image input unit 2, an ASIC 3, an arithmetic processing unit 4, a main storage unit 5, a storage unit 6, an ASIC 7, an image output unit 8, and the like. Each unit necessary for function processing as a composite apparatus such as a facsimile unit is provided.

  The image input unit 2 irradiates the original with reading light from a light source and photoelectrically converts the reflected light reflected by the original with a CCD (Charge Coupled Device), thereby main-scanning and sub-scanning the original, A scanner that reads the selected image at a specified resolution, for example, 100, 150, 200, 300, 400, or 600 dpi, is used, and the image data of the read document is output to the ASIC 3.

  The ASIC 3 performs predetermined image processing such as image compression processing on the image data input from the image input unit 2 and transfers the image data to the arithmetic processing unit 4 via the PCI bus.

  A main storage unit 5 and a storage unit 6 are connected to the arithmetic processing unit 4, and the storage unit 6 is composed of a ROM (Read Only Memory) or the like, and a basic program or book as a composite device 1 such as a BIOS. The data transfer control processing program of the embodiment and necessary system data are stored.

  The main storage unit 5 is constituted by a RAM (Random Access Memory) or the like, and is used as a work memory of the arithmetic processing unit 4 or a memory for temporarily storing image data.

  Based on the program stored in the storage unit 6, the arithmetic processing unit 4 controls each unit of the composite device 1 to operate as the composite device 1 while using the main storage unit 5 as a work memory. The arithmetic processing unit 4 particularly performs data transfer control processing in the image processing of the ASIC 3 or ASIC 4.

  The ASIC 7 includes an image processing unit, an arbiter, a DMAC, and the like. The image data of the original read by the image input unit 2, the image data transferred from an external host device (not shown), and the facsimile received by a facsimile unit (not shown) The image data is converted into data that can be processed by the image output unit 8 and output to the image output unit 8.

  The image output unit 8 uses, for example, an electrophotographic printer or the like, outputs a laser beam modulated based on the image data processed by the ASIC 7 from a semiconductor laser element, and passes it to a photoreceptor through a polygon mirror or the like. Irradiation forms an electrostatic latent image on the surface of the photoreceptor. The image output unit 8 applies toner to the electrostatic latent image on the photosensitive member to develop it as a toner image, transfers and fixes the toner image onto a sheet, forms an image, and discharges the sheet on which the image has been formed. Paper is discharged onto the tray.

  As shown in FIG. 2, the ASIC 3 includes image processing units 11 and 12, a selector 13, a management unit 14, a high-speed DMAC 15, a low-speed DMAC 16, an arbiter 17, a peripheral component interconnect controller (PCIC) 18, and the like. Image data from the image input unit 2 is input to the image processing unit 11.

  The image processing unit 11 performs necessary image processing on the image data of the document input from the image input unit 2 at a relatively high speed, and the image data after the image processing is sent to the selector 13, the arbiter 17, and the PCIC 18 by the high speed DMAC 15. To the arithmetic processing unit 4. The image processing unit 11 needs to process and transfer the image data from the image input unit 2 in accordance with the image reading operation processing of the image input unit 2, and performs high-speed image processing means for performing relatively high-speed image processing. Is functioning as

  The image processing unit 11 includes a data input detection unit (transfer end detection unit) 11a. The data input detection unit 11a is input to the image processing unit 11 from the image input unit 2 and is necessary for the image processing unit 11. The completion of the transfer of the processed image data to the high-speed DMAC 15 is detected, and a transfer end detection signal Sh is output to the management unit 14. That is, the data input detection unit 11a includes a down-count register, and sets the total transfer data amount input from the image input unit 2 and transferred by the high-speed DMAC 15 in the down-count register. When the image data is transferred by the high-speed DMAC 15, the data input detection unit 11a counts down the transferred actual transfer data amount from the down-count register, and when the value of the down-count register becomes “0”, the management unit The transfer end detection signal Sh output to 14 is changed from “1” to “0”. For example, when the document read by the image input unit 2 is a standard size document such as A4, the amount of image data can be determined. Therefore, the total transfer before the image data of the document read by the image input unit 2 starts to be transferred to the ASIC 3 The amount of data is notified to the image processing unit 11 side. When the total transfer data amount is notified from the image input unit 2, the data input detection unit 11a sets the total transfer data amount in the down count register. In addition, when the image input unit 2 notifies the standard size information of the original document instead of the total transfer data amount, the data input detection unit 11a refers to the standard size and data amount database previously stored therein. The data amount is acquired, and the data amount is set in the downcount register. Then, when data transfer is started thereafter, the data input detection unit 11a down-counts the actual transfer data amount transferred from the data amount of the down-count register, and when the value of the down-count register becomes “0”. The transfer end detection signal Sh output to the management unit 14 is changed from “1” to “0”.

  The image processing unit 12 relatively changes the processing speed of the image data transferred from the arithmetic processing unit 4 via the PCIC 18, the arbiter 17, and the selector 13 by the low-speed DMAC 16 depending on the content of the image data such as compression / decompression processing. It functions as a low-speed image processing means for performing low-speed image processing. The image processing unit 12 transfers the image data after the image processing to the arithmetic processing unit 4 through the arbiter 17 and the PCIC 18 by the high speed DMAC 15 or the low speed DMAC 16 connected through the selector 13.

  The image processing unit 12 includes a data processing progress detection unit (transfer status detection means) 12a. The data processing progress detection unit 12a detects the data transfer processing progress status and outputs a status signal Ss to the management unit 14. To do. That is, the data processing progress detection unit 12a includes a down-count register, and when the total transfer data amount is notified from the program of the arithmetic processing unit 4 before the transfer of the image data from the arithmetic processing unit 4 starts. The total transfer data amount is set in the downcount register. After that, when the data transfer is started and the data transfer is received via the low-speed DMAC 16, the data processing progress detection unit 12a counts down the actual transfer data amount transferred from the data amount of the down count register, When the value of the downcount register becomes “0”, the status signal Ss output to the management unit 14 is changed from “1” to “0”. Note that the function of the data processing progress detection unit 12a may be appropriately turned on / off by the software of the arithmetic processing unit 4. For example, the data processing progress detection unit 12a includes a function on / off register, and when the function on / off register is enabled by the program, the function becomes valid, and the function on / off register is disabled by the program. When disabled is set, the function is disabled. When the function is set to disabled, “1” is continuously output as the status signal Ss.

  The management unit (control means) 14 receives the transfer end detection signal Sh from the data input detection unit 11a and the status signal Ss from the data processing progress detection unit 12a, and inverts the transfer end detection signal Sh and the status signal Ss. Thereafter, an AND process is performed, and a selection signal Sc that switches between “1” and “0” depending on the values of the transfer end detection signal Sh and the status signal Ss is output to the selector 13. That is, when at least one of the transfer end signal Sh and the status signal Ss is “1”, the management unit 14 outputs the select signal Sc of “0” to the selector 13, and the transfer end detection signal Sh and the status signal If Ss is both “0”, a select signal Sc of “1” is output to the selector 13.

  As shown in FIG. 3, the selector (switching connection means) 13 includes two bus selectors 21 and 22, and the bus selector 21 includes two input terminals a and b and one output terminal c. . The bus selector 22 includes one input terminal c and two output terminals a and b. The bus selector 21 and the bus selector 22 receive the select signal Sc from the management unit 14 at the select terminal d. The bus selector 21 has the input terminal a connected to the image processing unit 11, the input terminal b connected to the output terminal b of the bus selector 22, and the output terminal c connected to the high-speed DMAC 15. . The bus selector 22 receives image data from the image processing unit 12 at its input terminal c, its output terminal a is connected to the input terminal b of the bus selector 21 as described above, and its output terminal b is low speed. It is connected to the DMAC 16.

  The bus selector 21 and the bus selector 22 connect the terminal a and the terminal c when the select signal Sc from the management unit 11 is “0”, and connect the terminal b and the terminal c when the select signal Sc is “1”. Connect. The management unit 14 and the selector 13 function as a transfer control unit as a whole.

  The high-speed DMAC 15 has, for example, a 128-bit × 4-stage buffer, and performs DMA transfer of data at a relatively high speed. The low-speed DMAC 16 has, for example, a 128-bit × 1 stage buffer, and performs DMA transfer of data at a relatively low speed.

  The descriptor information registers used by the DMACs 15 and 16 are provided in the image processing unit 11 and the image processing unit 12.

  The arbiter 17 arbitrates bus acquisition requests from the image processing unit 11 and the image processing unit 12 and controls use permission of the PCI bus.

  The PCIC 18 controls a high-speed split transaction bus that can issue a next request without waiting for a response by separating a request called PCI (Peripheral Component Interconnect) Express (PCIe) and the response. The processing unit 4 is connected. The arithmetic processing unit 4 and the ASIC 7 are also connected by PCIe.

  Next, the operation of this embodiment will be described. The composite apparatus 1 according to this embodiment performs data transfer from the image processing unit 12 that performs image processing at a relatively low speed, data transfer status of the image processing unit 11 that performs image processing at a relatively high speed, and data transfer of the image processing unit 12. Depending on the situation, the high-speed DMAC 15 and the low-speed DMAC 16 are switched appropriately.

  That is, the multifunction apparatus 1 reads an image of a document with the image input unit 2, sends the read image data from the ASIC 3 to the main storage unit 5 via the arithmetic processing unit 4, and sends the image data in the main storage unit 5 to the ASIC 3. The image input unit performs the necessary image processing, temporarily stores it in the main storage unit 5, then sends it to the ASIC 7 to perform the necessary image processing, and prints the image on the paper by the image output unit 8. 2 is sent from the ASIC 3 to the main memory 5 via the arithmetic processing unit 4, and the image data in the main memory 5 is returned to the ASIC 3 to perform necessary image processing. 5 and then sent by facsimile transmission, scanner operation, and network computer etc. Image data by performing image processing necessary ASIC3 and ASIC 7, performs a printer operation such as to print out on paper by the image output unit 8.

  In the composite apparatus 1, the initial state, the image processing unit 11 is transferring image data from the image input unit 2 at high speed, or the image processing unit 12 receives image data transfer from the arithmetic processing unit 4. In this case, the management unit 14 sets the select signal Sc to “0” and connects the terminal a and the terminal c to the bus selectors 21 and 22 of the selector 13.

  That is, the management unit 14 performs an AND process after inverting the transfer end detection signal Sh from the data input detection unit 11a of the image processing unit 11 and the status signal Ss from the data processing progress detection unit 12a of the image processing unit 12. The selection signal Sc is output to the selector 13 when the image processing unit 11 is transferring the image data from the image input unit 2 at high speed or the image processing unit 12 receives the transfer of the image data from the arithmetic processing unit 4. If it is in the middle, at least one of the transfer end signal Sh and the status signal Ss is “1”, so that the select signal Sc of “0” is output to the selector 13. When the select signal Sc is “0”, the bus selectors 21 and 22 of the selector 13 are connected to the terminal a and the terminal c, so that the image processing unit 11 and the high-speed DMAC 15 are connected. It is assumed that the image processing unit 12 and the low-speed DMAC 16 are connected.

  In this state, when the image input unit 2 reads the document and outputs the image data to the ASIC 3, when the document is a standard size document such as A4, the total transfer is performed before the image data of the document is started to be transferred to the ASIC 3. The data amount or the standard size information of the document is notified to the image processing unit 11, and the data input detection unit 11 a of the image processing unit 11 is based on the total transfer data amount or the document size information notified from the image input unit 2. The total transfer data amount determined in the above is set in the internal downcount register.

  Thereafter, when data transfer from the image input unit 2 is started, the data input detection unit 11a performs necessary image processing on the image data, and is transferred by the high-speed DMAC 15 via the selector 13. When the transfer data amount is down-counted from the data amount of the down-count register and the value of the down-count register becomes “0”, that is, all the image data of the original for one page is processed using the high-speed DMAC 15 When transferred to the fourth side, the transfer end detection signal Sh output to the management unit 14 is changed from “1” to “0”.

  On the other hand, the image processing unit 12 changes the processing speed of the image data transferred from the arithmetic processing unit 4 via the PCIC 18, the arbiter 17 and the selector 13 by the low-speed DMAC 16 depending on the content of the image data such as compression / decompression processing. A relatively low-speed image processing is performed, and the image data after the image processing is transferred to the arithmetic processing unit 4 via the selector 13 mainly using the low-speed DMAC 16 via the arbiter 17 and the PCIC 18. Before the transfer of image data from the processing unit 4 starts, the total transfer data amount is notified from the program of the arithmetic processing unit 4, and the data processing progress detection unit 12a of the image processing unit 12 counts down the total transfer data amount. Set to register. When data transfer is started and data transfer is received via the low-speed DMAC 16, the data processing progress detection unit 12a down-counts the actual transfer data amount transferred from the data amount of the down-count register, and counts down. When the value of the register becomes “0”, the status signal Ss output to the management unit 14 is changed from “1” to “0”.

  As described above, when the transfer end detection signal Sh from the data input detection unit 11a of the image processing unit 11 is “0” and the status signal Ss from the data processing progress detection unit 12a of the image processing unit 12 is “0”, The management unit 14 switches the select signal Sc from “0” to “1”. When the select signal Sc from the management unit 14 is switched from “0” to “1”, the selector 13 switches the terminals b and c from the state where the terminals a and c are connected. Switch to connected state.

  Therefore, the image processing unit 12 is connected to the high-speed DMAC 15 via the bus selector 21 and the bus selector 22, and the processed image data can be transferred to the arithmetic processing unit 4 using the high-speed DMAC 15.

  As described above, the composite apparatus 1 according to the present exemplary embodiment transfers image data processed by the image processing unit 11 that performs high-speed image processing with priority by the high-speed DMAC 15, and also processes the image data processed by the image processing unit 11 and the low-speed image. The low-speed DMAC 16 and the high-speed DMAC 15 are appropriately selected based on the transfer status of the image data processed by the image processing unit 12 that performs processing, and the image data processed by the image processing unit 12 is transferred.

  Therefore, in consideration of the image processing speed of the image processing unit 11 and the image processing unit 12 and the data transfer speed of the high speed DMAC 15 and the low speed DMAC 16, the image data processed by the image processing unit 12 is efficiently transferred to perform image processing. The image data processed by the unit 12 can be processed in accordance with the flow of image data in the image processing process of the entire multifunction apparatus 1, and the productivity of the entire image processing can be improved.

  Further, in the composite apparatus 1 of the present embodiment, the data input detection unit 11a that detects the end of transfer of the image data processed by the image processing unit 11 detects the transfer status of the image data processed by the image processing unit 12. Based on the detection results of the data input detection unit 11a and the data processing progress detection unit 12a, the management unit 14 detects the DMAC used for transfer of the image data processed by the image processing unit 12 based on the detection by the progress detection unit 12a. Selected.

  Therefore, the image data processed by the image processing unit 12 can be transferred more efficiently, and the image data processed by the image processing unit 12 can be more appropriately matched to the flow of image data in the entire image processing process. Processing can further improve the productivity of the entire image processing.

  Furthermore, in the multifunction apparatus 1 of the present embodiment, the data input detection unit 11a acquires in advance the amount of image data processed by the image processing unit 11, and detects the end of transfer based on the amount of image data.

  Therefore, the data transfer of the image processing unit 11 can be detected appropriately and easily, and the productivity of the entire image processing can be further improved.

  In the multifunction apparatus 1 according to the present embodiment, the data input detection unit 11a detects the end of transfer of the image data processed by the image processing unit 11, and then the data processing progress detection unit 12a performs untransferred processing performed by the image processing unit 12. Is detected, the high-speed DMAC 15 is selected as the DMAC used to transfer the image data processed by the image processing unit 12.

  Therefore, the image data processed by the image processing unit 12 having a low processing speed can be quickly transferred by the high-speed DMAC 15 and processed in accordance with the flow of image data in the entire image processing process. Can be improved.

  Furthermore, in the composite apparatus 1 of the present embodiment, the management unit 14 controls the connection state of the selector 13 that selectively connects the image processing unit 11 and the image processing unit 12 to the high speed DMAC 15 and the low speed DMAC 16.

  Therefore, the image data processed by the image processing unit 11 can be preferentially transferred by the high-speed DMAC 15 with a simple configuration, and the low-speed DMAC 16 and the high-speed DMAC 15 are appropriately selected and connected, and the image processing unit 12 The processed image data can be transferred at high speed, and the productivity of the entire image processing can be improved.

  The function of the data processing progress detection unit 12a may be appropriately turned on / off by the software of the arithmetic processing unit 4. When the function is turned off, the status signal Ss is “1”. Will continue to be output. In this case, the management unit 14 always outputs “0” to the selector 13 as the select signal Sc, and the bus selectors 21 and 22 of the selector 13 continue to connect the terminal a and the terminal c. .

  In this way, the switching function between the high-speed DMAC 15 and the low-speed DMAC 16 can be stopped according to the overall image processing status of the composite apparatus 1, and the usability can be improved.

  Furthermore, in the above description, the data input detection unit 11a determines whether the transfer of the input image is confirmed based on the total transfer data amount notified from the image input unit 2 or the total transfer data amount determined based on the document size information. This is done by setting the count register and down-counting the down-count register with the actual transfer data. However, the transfer confirmation of the input image is not limited to the above method. For example, the data transfer time is counted by a timer. It may be done by doing. For example, when the data input detection unit 11a holds a default value required for transfer of input image data in an internal register, and the image input unit 2 notifies the start of transfer of image data, the default time of the internal register is set in a timer. Then, the timer counts down the default time in synchronization with the rising edge of the clock for each transfer of image data using the high-speed DMAC 15, and when the default time becomes “0”, the transfer end detection signal Sh is set to “1”. ”To“ 0 ”.

  In this way, the data transfer of the image processing unit 11 can be detected appropriately and easily based on the transfer time of the image data, and the productivity of the entire image processing can be easily improved.

  4 and 5 are diagrams showing a second embodiment of the image processing apparatus and the image processing method of the present invention, and FIG. 4 applies the second embodiment of the image processing apparatus and the image processing method of the present invention. It is a block block diagram of ASIC30 of a compound apparatus.

  The present embodiment is applied to a composite apparatus similar to the composite apparatus 1 of the first embodiment. In the description of the present embodiment, the same components as those of the first embodiment are the same. The detailed description will be omitted, and portions not shown will be described using the same reference numerals used in the description of the first embodiment as necessary.

  As in the first embodiment, the composite apparatus 1 of the present embodiment includes an image input unit 2, an arithmetic processing unit 4, a main storage unit 5, a storage unit 6, an ASIC 7, an image output unit 8, and the like. 4, the ASIC 30 performs image processing on the image data from the image input unit 2 of the composite apparatus 1 and transfers the image data to the arithmetic processing unit 4.

  The ASIC 30 includes the image processing unit 11, the arbiter 17, and the PCIC 18 similar to the ASIC 3 of the first embodiment, and also includes an image processing unit 31, a selector 32, a management unit 33, a high-speed DMAC 34, a low-speed DMAC 35, and the like. The image processing unit 11 includes a data input detection unit 11a similar to the above.

  The image processing unit 31 relatively changes the processing speed of the image data transferred from the arithmetic processing unit 4 via the PCIC 18, the arbiter 17, and the selector 32 by the low-speed DMAC 35 depending on the content of the image data such as compression / decompression processing. It performs low-speed image processing and functions as low-speed image processing means. The image processing unit 31 transfers the image data after the image processing to the arithmetic processing unit 4 via the arbiter 17 and the PCIC 18 by the high speed DMAC 34 or the low speed DMAC 35 connected via the selector 32.

  The image processing unit 31 includes a data processing progress detection unit (transfer status detection unit) 31 a. The data processing progress detection unit 31 a detects the data transfer processing progress status and outputs a status signal Ss to the management unit 33. At the same time, the interlock select signal Sr is output to the selector 32. That is, the data processing progress detection unit 31a includes a status signal down-count register and a linked select signal down-count register, and before the transfer of image data from the arithmetic processing unit 4 starts, the program of the arithmetic processing unit 4 Is notified of the total transfer data amount, the total transfer data amount is set in the status signal down-count register. Thereafter, when the data transfer from the arithmetic processing unit 4 is started and data transfer is received via the low-speed DMAC 16, the data processing progress detection unit 31a receives the data transfer from the data count of the downcount register. When the value of the downcount register becomes “0”, that is, when reception of all data from the arithmetic processing unit 4 is completed, the status signal Ss output to the management unit 14 is set to “1”. To “0”. In addition, the data processing progress detection unit 31a sets a default value in the linked select signal down-count register in the initial state, and when data transfer from the image processing unit 31 to the arithmetic processing unit 4 is started, the transfer data amount Down-counting is performed by subtracting the value of the down-count register for interlocking select signal. The default value set in the interlock select signal down-count register is the capacity of the buffer provided in the high-speed DMAC 34, for example, 128 bits × 4 stages, and the capacity of the buffer provided in the low-speed DMAC 35, for example, 128 bits × 1 stage. In the above example, the default value is a data amount of 128 bits × (5-1). The data processing progress detection unit 31a outputs the interlock select signal Sr of “1” to the selector 32 when the data amount of the down count register for the interlock select signal is 128 bits × 1 or more, and when the data amount is less than 128 bits × 1. , “0” interlocking select signal Sr is output to selector 32. When the register value of the interlock select signal downcount register becomes “0”, the data processing progress detection unit 31a resets and sets a default value.

  The function of the data processing progress detection unit 31a may be appropriately turned on / off by software of the arithmetic processing unit 4. For example, the data processing progress detection unit 31a includes a function on / off register. When the function on / off register is enabled by a program, the function becomes valid, and the function on / off register is disabled by the program. When disable is set, the function is disabled. When the function is set to disabled, “1” is continuously output as the status signal Ss, and “0” is output as the interlock select signal Sr. to continue.

  The management unit (control unit) 33 receives the transfer end detection signal Sh from the data input detection unit 11a and the status signal Ss from the data processing progress detection unit 31a, and inverts the transfer end detection signal Sh and the status signal Ss. Thereafter, an AND process is performed, and a selection signal Sc that switches between “1” and “0” depending on the values of the transfer end detection signal Sh and the status signal Ss is output to the selector 13. That is, when at least one of the transfer end signal Sh and the status signal Ss is “1”, the management unit 33 outputs the select signal Sc of “0” to the selector 32, and the transfer end detection signal Sh and the status signal If both Ss are “0”, a select signal Sc of “1” is output to the selector 32.

  As shown in FIG. 5, the selector (switching connection means) 32 includes two bus selectors 41 and 42 and an AND circuit 43. The bus selector 41 has two input terminals a and b and one output terminal c. It has. The bus selector 42 includes one input terminal c and two output terminals a and b, and the bus selector 41 receives a select signal Sc from the management unit 33 at its select terminal d. In the bus selector 41, the image data from the image processing unit 11 is input to the input terminal a, the output terminal b of the bus selector 42 is connected to the input terminal b, and the output terminal c is connected to the high-speed DMAC 34. It is connected. In the bus selector 42, the image processing unit 31 is connected to the input terminal c, the output terminal a is connected to the input terminal b of the bus selector 41, and the output terminal b is connected to the low-speed DMAC 35 as described above. ing. The output of the AND circuit 43 is connected to the select terminal d of the bus selector 42. The input of the AND circuit 43 is connected to the select signal Sc from the management unit 33 and the interlocked select signal Sr from the data processing progress detection unit 31a. Is entered. The AND circuit 43 outputs an output signal of “1” to the select terminal d of the bus selector 42 only when both the select signal Sc and the interlocked select signal Sr are “1”. The management unit 33 and the selector 32 function as a transfer control unit as a whole.

  The bus selector 41 and the bus selector 42 connect the terminal a and the terminal c when the signal input to the select terminal d is “0”, and the signal input to the select terminal d is “1”. ", The terminal b and the terminal c are connected. Specifically, when the select signal Sc from the management unit 11 is “0”, the bus selector 41 and the bus selector 42 connect the terminals a and c, respectively, and when the select signal Sc is “1”. The bus selector 41 connects the terminal b and the terminal c. At this time, when the interlock select signal Sr is “0”, the bus selector 41 connects the terminal a and the terminal c, and the interlock select signal Sr is When “1”, the terminal b and the terminal c are connected.

  The high-speed DMAC 34 has, for example, a 128-bit × 4-stage buffer, and performs DMA transfer of data at a relatively high speed. The high-speed DMAC 34 includes a buffer detection unit (buffer state detection means, notification means) 34a, detects whether the internal buffer is full or empty, and outputs a ready signal RSh to the low-speed DMAC 35. Specifically, the buffer detection unit 34a has a down counter register in which the data amount of the buffer is set, and counts down the data amount transferred by the high-speed DMAC 34 and the data amount transferred from the image processing unit 31 to the buffer. Then, one clock before the buffer becomes full is detected, and the ready signal RSh output to the low-speed DMAC 35 is switched from “0” to “1”. Further, when the high-speed DMAC 34 starts transferring the data in the buffer to the arithmetic processing unit 4, the buffer detection unit 34a monitors the amount of data in the buffer, and one clock before the data in the buffer becomes empty, The ready signal RSh output to the low-speed DMAC 35 is switched from “1” to “0”.

  The low-speed DMAC 35 has, for example, a 128-bit × 1 stage buffer, and performs DMA transfer of data at a relatively low speed. The low speed DMAC 35 includes a buffer detection unit 35a (buffer state detection unit, notification unit). The buffer detection unit 35a detects whether the internal buffer is full or empty, and sends the ready signal RSl to the high speed DMAC 34. Output to. Specifically, the buffer detection unit 35a has a down counter register in which the buffer data amount is set, and counts the data amount transferred by the low-speed DMAC 35 and the data amount transferred from the image processing unit 31 to the buffer. Thus, one clock before the buffer becomes full is detected, and the ready signal RS1 output to the high-speed DMAC 34 is switched from “0” to “1”. Further, when the low speed DMAC 35 starts transferring the data in the buffer to the arithmetic processing unit 4, the buffer detection unit 35a monitors the amount of data in the buffer, and one clock before the data in the buffer becomes empty, The ready signal RSl output to the high-speed DMAC 34 is switched from “0” to “1”.

  Next, the operation of this embodiment will be described. The composite apparatus 1 according to this embodiment performs data transfer from the image processing unit 12 that performs image processing at a relatively low speed, data transfer status of the image processing unit 11 that performs image processing at a relatively high speed, and data transfer of the image processing unit 12. Depending on the situation, the high-speed DMAC 15 and the low-speed DMAC 16 are switched appropriately, and data transfer from the low-speed image processing unit 12 to the arithmetic processing unit 4 is performed by efficiently switching between the high-speed DMAC 34 and the low-speed DMAC 35.

  That is, as described above, the image processing unit 11 transfers the image data input from the image input unit 2 to the arithmetic processing unit 4 using the high-speed DMAC 34, and the data input detection unit 11 a is transferred to the image processing unit 11. When the transfer using the high-speed DMAC 34 is completed for all the image data of one page of the original document, the transfer end detection signal Sh output to the management unit 33 is changed from “1” to “0”.

  On the other hand, the image processing unit 12 performs relatively low-speed image processing such as compression / decompression processing on the image data transferred from the arithmetic processing unit 4 via the PCIC 18, the arbiter 17, and the selector 32 by the low-speed DMAC 35. The image data after image processing is transferred to the arithmetic processing unit 4 via the arbiter 17 and the PCIC 18 by switching between the low speed DMAC 35 and the high speed DMAC 34 via the selector 32. At this time, the image data from the arithmetic processing unit 4 is transferred. Before the transfer of the image data starts, the total transfer data amount is notified from the program of the arithmetic processing unit 4, and the data processing progress detection unit 12a of the image processing unit 12 sets the total transfer data amount in the downcount register. When data transfer is started and data transfer is received via the low-speed DMAC 16, the data processing progress detection unit 12a down-counts the actual transfer data amount transferred from the data amount of the down-count register, and counts down. When the value of the register becomes “0”, the status signal Ss output to the management unit 33 is changed from “1” to “0”.

  The management unit 33 inverts the transfer end detection signal Sh from the data input detection unit 11a and the status signal Ss from the data processing progress detection unit 31a, and performs an AND process to obtain the transfer end detection signal Sh and the status signal Ss. A select signal Sc that switches between “1” and “0” depending on the value is output to the selector 32. That is, when at least one of the transfer end signal Sh and the status signal Ss is “1”, the management unit 33 outputs the select signal Sc of “0” to the selector 32, and the transfer end detection signal Sh and the status signal If both Ss are “0”, a select signal Sc of “1” is output to the selector 32. Now, the transfer end detection signal Sh from the data input detection unit 11a is “0”, and the data Since the status signal Ss from the process progress detection unit 31a is switched to “0”, the select signal Sc to the selector 32 is switched from “0” to “1”.

  When the select signal Sc from the management unit 33 is switched from “0” to “1”, the selector 32 connects the terminal b and the terminal c from the state where the terminal a and the terminal c are connected. The high-speed DMAC 34 is switched to the state connected to the bus selector 42 side.

  The bus selector 42 receives the select signal Sc and an AND output of an AND circuit 43 that AND-processes the select signal Sr from the data processing progress detection unit 31a, and the select signal Sc is “ Therefore, the switching operation is performed by the interlocking select signal Sr. That is, the bus selector 42 connects the terminal a and the terminal c when the interlocking select signal Sr is “0”, connects the image processing unit 12 to the low-speed DMAC 35a, and when the interlocking select signal Sr is “1”. The terminals b and c are connected, and the image processing unit 12 is connected to the high-speed DMAC 34 via the bus selector 41.

  Then, the data processing progress detection unit 31a sets a default value (128 bits × 4 in the above example) in the linked select signal down-count register in the initial state, and the data from the image processing unit 31 to the arithmetic processing unit 4 When the transfer is started, the value of the interlock select signal down-count register is down-counted according to the transfer data amount. The data processing progress detection unit 31a outputs the interlock select signal Sr of “1” to the selector 32 when the data amount of the interlock select signal down-count register is 128 bits × 1 or more. Therefore, the bus selector 42 connects the terminal b and the terminal c, connects the image processing unit 31 to the high-speed DMAC 34, and the image processing unit 31 transfers data to the buffer of the high-speed DMAC 34.

  Thereafter, the data processing progress detection unit 31a counts down the interlocked select signal downcount register based on the data transfer amount, and when the data amount of the interlocked select signal downcount register becomes less than 128 bits × 1, “0”. ”Is output to the selector 32. Therefore, the bus selector 42 connects the terminal a and the terminal c, connects the image processing unit 31 to the low speed DMAC 35, and the image processing unit 31 transfers data to the buffer of the low speed DMAC 35.

  The data processing progress detection unit 31a counts down the interlock select signal down-count register, and when the register value of the interlock select signal down-count register becomes “0”, it resets and sets a default value. The select signal Sr is switched from “0” to “1”. Therefore, the image processing unit 12 is sequentially switched to and connected to the high-speed DMAC 34 and the low-speed DMAC 35 based on the data transfer corresponding to the buffer amounts of the high-speed DMAC 34 and the low-speed DMAC 35.

  When the data is transferred from the image processing unit 31, the high speed DMAC 34 stores the data in a buffer. The buffer detection unit 34a monitors the data amount of the buffer using a down counter register, and the buffer is stored in the buffer. When one clock before becoming full is detected, the ready signal RSh output to the low-speed DMAC 35 is switched from “0” to “1”.

  When the ready signal RSh that is input is switched to “1”, the low-speed DMAC 35 enters a transfer data waiting state, the bus selector 42 of the selector 32 connects the image processing unit 31 to the low-speed DMAC 35, and data is transferred to the image processing unit 31. When the data is transferred from, the data is stored in a buffer. When the storage of data in the buffer is started, the buffer detection unit 35a monitors the amount of data in the buffer using a down counter register, and outputs the data to the high-speed DMAC 34 when detecting one clock before the buffer becomes full. The ready signal RS1 is switched from “0” to “1”.

  The high-speed DMAC 34 starts transferring the buffer data to the arithmetic processing unit 4 and switches the ready signal RSh output to the low-speed DMAC 35 from “1” to “0” one clock before the buffer becomes empty. The low-speed DMAC 35 starts to transfer the buffer data to the arithmetic processing unit 4, and the high-speed DMAC 34 enters a data standby state.

  The low-speed DMAC 35 starts transferring the buffer data to the arithmetic processing unit 4 and switches the ready signal RSl output to the high-speed DMAC 34 from “1” to “0” one clock before the buffer becomes empty. .

  During this time, as described above, the high speed DMAC 34 stores the data in the buffer when the data is transferred from the image processing unit 31, and the buffer detection unit 34a outputs the data to the low speed DMAC 35 when detecting one clock before the buffer becomes full. The ready signal RSh being switched is switched from “0” to “1”.

  By sequentially repeating the above processing, the high-speed DMAC 34 buffer and the low-speed DMAC 35 buffer are virtually combined, and the high-speed DMAC 34 and the low-speed DMAC 35 are alternately used as a 128-bit × 5-stage buffer. Can be transferred.

  As described above, in the composite apparatus 1 of this embodiment, the high-speed DMAC 34 and the low-speed DMAC 35 detect the buffer for temporarily storing the image data and the image data storage status of the buffer, and notify the other DMACs 34 and 35 of the buffer. The buffer detection units 34a and 35a are provided, and the DMACs 34 and 35 are sequentially switched based on the buffer amount, the detection results of the buffer detection units 34a and 35a, and the notification results from the partner buffer detection units 34a and 35a. The image data from the image processing unit 31 is transferred via the buffer, and the management unit 33 sequentially switches the connection state of the selector 32 to the high speed DMAC 34 and the low speed DMAC 35 based on the buffer amounts of the high speed DMAC 34 and the low speed DMAC 35, The image data processed by the image processing unit 31 is connected to the image processing unit 31. We have selected the DMAC to be sent.

  Therefore, by combining the buffers of the high-speed DMAC 34 and the low-speed DMAC 35, the image data of the image processing unit 31 can be DMA-transferred, and the transfer rate of the data transfer can be further improved.

  Also in the present embodiment, as described above, the function of the data processing progress detection unit 31a may be appropriately turned on / off by the software of the arithmetic processing unit 4.

  In this way, the switching function between the high-speed DMAC 34 and the low-speed DMAC 35 can be stopped according to the overall image processing status of the composite apparatus 1, and the usability can be improved.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to the above, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used in an image processing apparatus and an image processing method such as a printer apparatus, a copying apparatus, and a composite apparatus provided with image processing modules having different processing speeds and DMACs having different transfer speeds.

The principal part block block diagram of the compound apparatus to which 1st Example of this invention is applied. The principal part block block diagram of ASIC of FIG. The circuit block diagram of the selector of FIG. The principal part block block diagram of ASIC used for the compound apparatus to which 2nd Example of this invention is applied. The circuit block diagram of the selector of FIG. FIG. 7 is a timing chart in a state where a timing shift between the image input and the subsequent image processing does not occur (FIG. 6A) and a state where a shift occurs (FIG. 6B).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Compound apparatus 2 Image input part 3 ASIC
4 Arithmetic processing unit 5 Main storage unit 6 Storage unit 7 ASIC
8 Image output unit 11, 12 Image processing unit 11a Data input detection unit 12a Data processing progress detection unit 13 Selector 14 Management unit 15 High-speed DMAC
16 Low speed DMAC
17 Arbiter 18 PCIC
21, 22 Bus selector 30 ASIC
31 Image processing unit 31a Data processing progress detection unit 32 Selector 33 Management unit 34 High-speed DMAC
34a Buffer detection unit 35 Low speed DMAC
35a Buffer detection unit 41, 42 Bus selector 43 AND circuit

Claims (6)

A first image processing means for processing images in the image data,
And second image processing means for image processing at a slower processing speed than located in the flow direction downstream of the image data of the first image processing means than said first image processing means,
A first DMA controller for transferring image data to a DMA;
A second DMA controller for DMA transfer of image data at a slower rate than the first DMA controller;
The image data processed by the first image processing means is preferentially transferred to the first DMA controller, and the image data processed by the first image processing means and the second image processing means are processed. Transfer that appropriately selects the second DMA controller and the first DMA controller based on the transfer status of image data, and transfers the image data processed by the second image processing means to the selected DMA controller Control means ,
Each of the first DMA controller and the second DMA controller includes a buffer for temporarily storing image data, a buffer state detecting unit for detecting the image data storage state of the buffer, and a detection result of the buffer state detecting unit. A notification means for notifying each other, and sequentially switching based on the buffer amount of each DMA controller, the detection result of the buffer status detection means, and the notification result from the notification means of the partner DMA controller Transferring the image data from the second image processing means;
The transfer control unit compares a transfer amount of the image data processed by the second image processing unit with a threshold set in accordance with a capacity of a buffer included in the first DMA controller and the second DMA controller. According to a result, the first DMA controller and the second DMA controller are switched and selected as a DMA controller for transferring the image data processed by the second image processing means. apparatus. The image processing apparatus includes: a transfer end detection unit that detects a transfer end of image data processed by the first image processing unit; and a transfer state that detects a transfer state of image data processed by the second image processing unit. Detecting means, and the transfer control means is a DMA controller used for transferring image data processed by the second image processing means based on detection results of the transfer end detecting means and the transfer status detecting means. The image processing apparatus according to claim 1, wherein: The transfer end detection means acquires in advance the amount of image data processed by the first image processing means or the transfer time of the image data, and detects the transfer end based on the amount of image data or the transfer time. The image processing apparatus according to claim 2. The transfer control means detects that there is untransferred image data processed by the second image processing means after the transfer end detection means detects the transfer end. 4. The image processing apparatus according to claim 2, wherein the first DMA controller is selected as a DMA controller used for transferring image data processed by the second image processing means. The transfer control means includes switching connection means for selectively connecting the first image processing means and the second image processing means to the first DMA controller and the second DMA controller, and the switching connection. The image processing apparatus according to claim 1, further comprising a control unit that controls a connection state by the unit.   A first image processing step for performing image processing on the image data;
  A second image processing step that is positioned downstream of the first image processing step in the flow direction of image data and that performs image processing at a processing speed slower than that of the first image processing step;
  The image data processed in the first image processing step is preferentially transferred to the first DMA controller that performs DMA transfer, and the image data processed in the first image processing step and the second image processing are transferred. Based on the transfer status of the image data processed in the step, the second DMA controller and the first DMA controller that perform DMA transfer at a slower speed than the first DMA controller are appropriately selected, and the selected DMA A transfer control processing step for causing the controller to transfer the image data processed in the second image processing step;
  The amount of buffers that the first DMA controller and the second DMA controller have, the detection result of the buffer state detection means included in the first DMA controller and the second DMA controller, and one DMA controller Switching sequentially based on the detection result of the buffer state detection means notified from the other DMA controller, and transferring the image data from the second image processing means;
  According to the comparison result between the transfer amount of the image data processed by the second image processing means and the threshold value set according to the buffer capacity of the first DMA controller and the second DMA controller. An image processing method comprising: switching between the first DMA controller and the second DMA controller as a DMA controller for transferring image data processed by the second image processing means.

Images